[clang] [llvm] Revert "[SME] Add intrinsics for FCVT(wid.) and FCVTL" (PR #93196)
llvmbot wrote:
@llvm/pr-subscribers-clang
Author: None (Lukacma)
Changes
Reverts llvm/llvm-project#90215
---
Full diff: https://github.com/llvm/llvm-project/pull/93196.diff
7 Files Affected:
- (modified) clang/include/clang/Basic/arm_sve.td (-11)
- (modified) clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvt.c (-22)
- (removed) clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvtl.c (-40)
- (modified) llvm/include/llvm/IR/IntrinsicsAArch64.td (+1-13)
- (modified) llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp (-6)
- (modified) llvm/test/CodeGen/AArch64/sme2-intrinsics-cvt.ll (+1-10)
- (removed) llvm/test/CodeGen/AArch64/sme2-intrinsics-cvtl.ll (-11)
``diff
diff --git a/clang/include/clang/Basic/arm_sve.td
b/clang/include/clang/Basic/arm_sve.td
index 4f28547998550..03570f94de666 100644
--- a/clang/include/clang/Basic/arm_sve.td
+++ b/clang/include/clang/Basic/arm_sve.td
@@ -2265,10 +2265,6 @@ let TargetGuard = "sme2" in {
def SVCVT_S32_F32_X4 : SInst<"svcvt_{d}[_f32_x4]", "4.d4.M", "i",
MergeNone, "aarch64_sve_fcvtzs_x4", [IsStreaming,
IsOverloadWhileOrMultiVecCvt], []>;
}
-let TargetGuard = "sme-f16f16" in {
- def SVCVT_F32_X2 : SInst<"svcvt_{d}[_f16_x2]", "2h", "f", MergeNone,
"aarch64_sve_fcvt_widen_x2", [ IsStreaming],[]>;
-}
-
//
// Multi-vector floating-point convert from single-precision to interleaved
half-precision/BFloat16
//
@@ -2277,13 +2273,6 @@ let TargetGuard = "sme2" in {
def SVCVTN_BF16_X2 : SInst<"svcvtn_bf16[_f32_x2]", "$2", "f", MergeNone,
"aarch64_sve_bfcvtn_x2", [IsOverloadNone, IsStreaming],[]>;
}
-//
-//Multi-vector floating-point convert from half-precision to deinterleaved
single-precision.
-//
-let TargetGuard = "sme-f16f16" in {
- def SVCVTL_F32_X2 : SInst<"svcvtl_f32[_f16_x2]", "2h", "f", MergeNone,
"aarch64_sve_fcvtl_widen_x2", [ IsStreaming],[]>;
-}
-
//
// Multi-vector saturating extract narrow
//
diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvt.c
b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvt.c
index e26499d3a63cc..4a5ee7e021f74 100644
--- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvt.c
+++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvt.c
@@ -497,25 +497,3 @@ svuint8_t test_qcvt_u8_s32_x4(svint32x4_t zn)
__arm_streaming {
svuint16_t test_qcvt_u16_s64_x4(svint64x4_t zn) __arm_streaming {
return SVE_ACLE_FUNC(svqcvt_u16,_s64_x4,,)(zn);
}
-
-// CHECK-LABEL: @test_cvt_f32_x2(
-// CHECK-NEXT: entry:
-// CHECK-NEXT:[[TMP0:%.*]] = tail call { , } @llvm.aarch64.sve.fcvt.widen.x2.nxv4f32(
[[ZN:%.*]])
-// CHECK-NEXT:[[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0
-// CHECK-NEXT:[[TMP2:%.*]] = tail call
@llvm.vector.insert.nxv8f32.nxv4f32( poison, [[TMP1]], i64 0)
-// CHECK-NEXT:[[TMP3:%.*]] = extractvalue { , } [[TMP0]], 1
-// CHECK-NEXT:[[TMP4:%.*]] = tail call
@llvm.vector.insert.nxv8f32.nxv4f32( [[TMP2]], [[TMP3]], i64 4)
-// CHECK-NEXT:ret [[TMP4]]
-//
-// CPP-CHECK-LABEL: @_Z15test_cvt_f32_x2u13__SVFloat16_t(
-// CPP-CHECK-NEXT: entry:
-// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call { , } @llvm.aarch64.sve.fcvt.widen.x2.nxv4f32(
[[ZN:%.*]])
-// CPP-CHECK-NEXT:[[TMP1:%.*]] = extractvalue { ,
} [[TMP0]], 0
-// CPP-CHECK-NEXT:[[TMP2:%.*]] = tail call
@llvm.vector.insert.nxv8f32.nxv4f32( poison, [[TMP1]], i64 0)
-// CPP-CHECK-NEXT:[[TMP3:%.*]] = extractvalue { ,
} [[TMP0]], 1
-// CPP-CHECK-NEXT:[[TMP4:%.*]] = tail call
@llvm.vector.insert.nxv8f32.nxv4f32( [[TMP2]], [[TMP3]], i64 4)
-// CPP-CHECK-NEXT:ret [[TMP4]]
-//
-__attribute__((target("sme-f16f16"))) svfloat32x2_t
test_cvt_f32_x2(svfloat16_t zn) __arm_streaming {
- return SVE_ACLE_FUNC(svcvt_f32,_f16_x2,,)(zn);
-}
diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvtl.c
b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvtl.c
deleted file mode 100644
index 1142065614b8f..0
--- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvtl.c
+++ /dev/null
@@ -1,40 +0,0 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-
-// REQUIRES: aarch64-registered-target
-
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme
-target-feature +sme-f16f16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o
- %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme
-target-feature +sme-f16f16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o
- -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
-check-prefix=CPP-CHECK
-// RUN: %clang_cc1 -D__SVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu
-target-feature +sme -target-feature +sme-f16f16 -S -disable-O0-optnone -Werror
-Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim |
FileCheck %s
-// RUN: %clang_cc1 -D__SVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu
-target-feature +sme
[clang] [llvm] Revert "[SME] Add intrinsics for FCVT(wid.) and FCVTL" (PR #93196)
https://github.com/Lukacma closed https://github.com/llvm/llvm-project/pull/93196 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] Revert "[SME] Add intrinsics for FCVT(wid.) and FCVTL" (PR #93196)
https://github.com/Lukacma created
https://github.com/llvm/llvm-project/pull/93196
Reverts llvm/llvm-project#90215
>From 1786075d2a347465e518cfaa04a40cb75eb75828 Mon Sep 17 00:00:00 2001
From: Lukacma
Date: Thu, 23 May 2024 15:13:01 +0100
Subject: [PATCH] Revert "[SME] Add intrinsics for FCVT(wid.) and FCVTL
(#90215)"
This reverts commit 05c154f2bcba34f002b1f0c22c7a9e9614e9d83c.
---
clang/include/clang/Basic/arm_sve.td | 11 -
.../aarch64-sme2-intrinsics/acle_sme2_cvt.c | 22 --
.../aarch64-sme2-intrinsics/acle_sme2_cvtl.c | 40 ---
llvm/include/llvm/IR/IntrinsicsAArch64.td | 14 +--
.../Target/AArch64/AArch64ISelDAGToDAG.cpp| 6 ---
.../CodeGen/AArch64/sme2-intrinsics-cvt.ll| 11 +
.../CodeGen/AArch64/sme2-intrinsics-cvtl.ll | 11 -
7 files changed, 2 insertions(+), 113 deletions(-)
delete mode 100644 clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvtl.c
delete mode 100644 llvm/test/CodeGen/AArch64/sme2-intrinsics-cvtl.ll
diff --git a/clang/include/clang/Basic/arm_sve.td
b/clang/include/clang/Basic/arm_sve.td
index 4f28547998550..03570f94de666 100644
--- a/clang/include/clang/Basic/arm_sve.td
+++ b/clang/include/clang/Basic/arm_sve.td
@@ -2265,10 +2265,6 @@ let TargetGuard = "sme2" in {
def SVCVT_S32_F32_X4 : SInst<"svcvt_{d}[_f32_x4]", "4.d4.M", "i",
MergeNone, "aarch64_sve_fcvtzs_x4", [IsStreaming,
IsOverloadWhileOrMultiVecCvt], []>;
}
-let TargetGuard = "sme-f16f16" in {
- def SVCVT_F32_X2 : SInst<"svcvt_{d}[_f16_x2]", "2h", "f", MergeNone,
"aarch64_sve_fcvt_widen_x2", [ IsStreaming],[]>;
-}
-
//
// Multi-vector floating-point convert from single-precision to interleaved
half-precision/BFloat16
//
@@ -2277,13 +2273,6 @@ let TargetGuard = "sme2" in {
def SVCVTN_BF16_X2 : SInst<"svcvtn_bf16[_f32_x2]", "$2", "f", MergeNone,
"aarch64_sve_bfcvtn_x2", [IsOverloadNone, IsStreaming],[]>;
}
-//
-//Multi-vector floating-point convert from half-precision to deinterleaved
single-precision.
-//
-let TargetGuard = "sme-f16f16" in {
- def SVCVTL_F32_X2 : SInst<"svcvtl_f32[_f16_x2]", "2h", "f", MergeNone,
"aarch64_sve_fcvtl_widen_x2", [ IsStreaming],[]>;
-}
-
//
// Multi-vector saturating extract narrow
//
diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvt.c
b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvt.c
index e26499d3a63cc..4a5ee7e021f74 100644
--- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvt.c
+++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvt.c
@@ -497,25 +497,3 @@ svuint8_t test_qcvt_u8_s32_x4(svint32x4_t zn)
__arm_streaming {
svuint16_t test_qcvt_u16_s64_x4(svint64x4_t zn) __arm_streaming {
return SVE_ACLE_FUNC(svqcvt_u16,_s64_x4,,)(zn);
}
-
-// CHECK-LABEL: @test_cvt_f32_x2(
-// CHECK-NEXT: entry:
-// CHECK-NEXT:[[TMP0:%.*]] = tail call { , } @llvm.aarch64.sve.fcvt.widen.x2.nxv4f32(
[[ZN:%.*]])
-// CHECK-NEXT:[[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0
-// CHECK-NEXT:[[TMP2:%.*]] = tail call
@llvm.vector.insert.nxv8f32.nxv4f32( poison, [[TMP1]], i64 0)
-// CHECK-NEXT:[[TMP3:%.*]] = extractvalue { , } [[TMP0]], 1
-// CHECK-NEXT:[[TMP4:%.*]] = tail call
@llvm.vector.insert.nxv8f32.nxv4f32( [[TMP2]], [[TMP3]], i64 4)
-// CHECK-NEXT:ret [[TMP4]]
-//
-// CPP-CHECK-LABEL: @_Z15test_cvt_f32_x2u13__SVFloat16_t(
-// CPP-CHECK-NEXT: entry:
-// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call { , } @llvm.aarch64.sve.fcvt.widen.x2.nxv4f32(
[[ZN:%.*]])
-// CPP-CHECK-NEXT:[[TMP1:%.*]] = extractvalue { ,
} [[TMP0]], 0
-// CPP-CHECK-NEXT:[[TMP2:%.*]] = tail call
@llvm.vector.insert.nxv8f32.nxv4f32( poison, [[TMP1]], i64 0)
-// CPP-CHECK-NEXT:[[TMP3:%.*]] = extractvalue { ,
} [[TMP0]], 1
-// CPP-CHECK-NEXT:[[TMP4:%.*]] = tail call
@llvm.vector.insert.nxv8f32.nxv4f32( [[TMP2]], [[TMP3]], i64 4)
-// CPP-CHECK-NEXT:ret [[TMP4]]
-//
-__attribute__((target("sme-f16f16"))) svfloat32x2_t
test_cvt_f32_x2(svfloat16_t zn) __arm_streaming {
- return SVE_ACLE_FUNC(svcvt_f32,_f16_x2,,)(zn);
-}
diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvtl.c
b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvtl.c
deleted file mode 100644
index 1142065614b8f..0
--- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvtl.c
+++ /dev/null
@@ -1,40 +0,0 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-
-// REQUIRES: aarch64-registered-target
-
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme
-target-feature +sme-f16f16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o
- %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme
-target-feature +sme-f16f16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o
- -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
-check-prefix=CPP-CHECK
-// RUN: %clang_cc1
