[clang-tools-extra] [llvm] [clang] [ISel] Add pattern matching for depositing subreg value (PR #75978)
@@ -561,6 +561,16 @@ def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), [(set GR64:$dst, (load addr:$src))]>; } +def : Pat<(or (and GR64:$dst, -256), topperc wrote: I meant GPR32 for the destination type def : Pat<(or (and GPR32:$dst, -256), (i32 (zextloadi8 addr:$src))), https://github.com/llvm/llvm-project/pull/75978 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang-tools-extra] [llvm] [clang] [ISel] Add pattern matching for depositing subreg value (PR #75978)
@@ -561,6 +561,16 @@ def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), [(set GR64:$dst, (load addr:$src))]>; } +def : Pat<(or (and GR64:$dst, -256), david-xl wrote: 32bit move has implicit zero extension, so won't be applicable. Moved the change to X86InstrCompiler.td https://github.com/llvm/llvm-project/pull/75978 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang-tools-extra] [llvm] [clang] [ISel] Add pattern matching for depositing subreg value (PR #75978)
@@ -0,0 +1,35 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +;RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=X64 + +define i64 @sub8(i64 noundef %res, ptr %byte) { +; X64-LABEL: sub8: +; X64: # %bb.0: # %entry +; X64-NEXT:movq %rdi, %rax +; X64-NEXT:movb (%rsi), %al +; X64-NEXT:retq +entry: + %and = and i64 %res, -256 + %d = load i8, ptr %byte, align 1 + %conv2 = zext i8 %d to i64 + %or = or i64 %and, %conv2 + ret i64 %or +} + + +define i64 @sub16(i64 noundef %res, ptr %byte) { david-xl wrote: fixed. https://github.com/llvm/llvm-project/pull/75978 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang-tools-extra] [llvm] [clang] [ISel] Add pattern matching for depositing subreg value (PR #75978)
@@ -0,0 +1,35 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +;RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=X64 + +define i64 @sub8(i64 noundef %res, ptr %byte) { david-xl wrote: done https://github.com/llvm/llvm-project/pull/75978 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits