[llvm] [clang] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU (PR #74822)

2023-12-08 Thread Jonathan Thackray via cfe-commits 

https://github.com/jthackray closed 
https://github.com/llvm/llvm-project/pull/74822
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[llvm] [clang] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU (PR #74822)

2023-12-08 Thread David Spickett via cfe-commits 

https://github.com/DavidSpickett approved this pull request.

LGTM

https://github.com/llvm/llvm-project/pull/74822
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[llvm] [clang] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU (PR #74822)

2023-12-08 Thread David Spickett via cfe-commits 


@@ -896,9 +896,13 @@ Arm and AArch64 Support
 
   Support has been added for the following processors (-mcpu identifiers in 
parenthesis):
 
-  * Arm Cortex-A520 (cortex-a520).
-  * Arm Cortex-A720 (cortex-a720).
-  * Arm Cortex-X4 (cortex-x4).
+  --target=arm
+ * Arm Cortex-M52 (cortex-m52).
+
+  --target=aarch64
+ * Arm Cortex-A520 (cortex-a520).
+ * Arm Cortex-A720 (cortex-a720).
+ * Arm Cortex-X4 (cortex-x4).

DavidSpickett wrote:

That's certainly easier to format, so go with that. Wouldn't be surprised if 
`--` looked to RST like a formatting directive.

https://github.com/llvm/llvm-project/pull/74822
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[llvm] [clang] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU (PR #74822)

2023-12-08 Thread David Green via cfe-commits 


@@ -896,9 +896,13 @@ Arm and AArch64 Support
 
   Support has been added for the following processors (-mcpu identifiers in 
parenthesis):
 
-  * Arm Cortex-A520 (cortex-a520).
-  * Arm Cortex-A720 (cortex-a720).
-  * Arm Cortex-X4 (cortex-x4).
+  --target=arm
+ * Arm Cortex-M52 (cortex-m52).
+
+  --target=aarch64
+ * Arm Cortex-A520 (cortex-a520).
+ * Arm Cortex-A720 (cortex-a720).
+ * Arm Cortex-X4 (cortex-x4).

davemgreen wrote:

Maybe just "For Arm:" and "For AArch64:" if the --target is awkward. Otherwise 
this LGTM if David Agrees

https://github.com/llvm/llvm-project/pull/74822
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[llvm] [clang] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU (PR #74822)

2023-12-08 Thread David Spickett via cfe-commits 


@@ -896,9 +896,13 @@ Arm and AArch64 Support
 
   Support has been added for the following processors (-mcpu identifiers in 
parenthesis):
 
-  * Arm Cortex-A520 (cortex-a520).
-  * Arm Cortex-A720 (cortex-a720).
-  * Arm Cortex-X4 (cortex-x4).
+  --target=arm
+ * Arm Cortex-M52 (cortex-m52).
+
+  --target=aarch64
+ * Arm Cortex-A520 (cortex-a520).
+ * Arm Cortex-A720 (cortex-a720).
+ * Arm Cortex-X4 (cortex-x4).

DavidSpickett wrote:

And if you checked that already, I'm probably just seeing a weird artifact in 
Github's rendering of it.

https://github.com/llvm/llvm-project/pull/74822
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[llvm] [clang] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU (PR #74822)

2023-12-08 Thread Jonathan Thackray via cfe-commits 


@@ -899,6 +899,7 @@ Arm and AArch64 Support
   * Arm Cortex-A520 (cortex-a520).
   * Arm Cortex-A720 (cortex-a720).
   * Arm Cortex-X4 (cortex-x4).
+  * Arm Cortex-M52 (cortex-m52).

jthackray wrote:

Sure. Something like this?

```
+  --target=arm
+ * Arm Cortex-M52 (cortex-m52).
+
+  --target=aarch64
+ * Arm Cortex-A520 (cortex-a520).
+ * Arm Cortex-A720 (cortex-a720).
+ * Arm Cortex-X4 (cortex-x4).
```

https://github.com/llvm/llvm-project/pull/74822
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[llvm] [clang] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU (PR #74822)

2023-12-08 Thread Jonathan Thackray via cfe-commits 


@@ -102,7 +102,7 @@ Changes to the AMDGPU Backend
 
 * Implemented :ref:`llvm.get.rounding `
 
-* Added support for Cortex-A520, Cortex-A720 and Cortex-X4 CPUs.
+* Added support for Cortex-A520, Cortex-A720, Cortex-X4 and Cortex-M52 CPUs.

jthackray wrote:

Thanks, David. Good spot. I added those new CPUs a month ago, and somehow 
missed they were in the wrong section. Now fixed.

https://github.com/llvm/llvm-project/pull/74822
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[llvm] [clang] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU (PR #74822)

2023-12-08 Thread Jonathan Thackray via cfe-commits 

https://github.com/jthackray updated 
https://github.com/llvm/llvm-project/pull/74822

>From 5925f180b6a8623ae1f1497f89c1f6ef35517e4a Mon Sep 17 00:00:00 2001
From: Jonathan Thackray 
Date: Thu, 23 Nov 2023 15:54:01 +
Subject: [PATCH 1/3] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU

Cortex-M52 is an Armv8.1 AArch32 CPU.

Technical specifications available at:
  https://developer.arm.com/processors/cortex-m52
---
 clang/docs/ReleaseNotes.rst|  1 +
 clang/test/CodeGen/arm-target-features.c   |  3 +++
 clang/test/Driver/arm-cortex-cpus-2.c  |  3 +++
 clang/test/Misc/target-invalid-cpu-note.c  |  2 +-
 llvm/docs/ReleaseNotes.rst |  2 +-
 llvm/include/llvm/TargetParser/ARMTargetParser.def |  3 +++
 llvm/lib/Target/ARM/ARM.td | 11 +++
 llvm/lib/Target/ARM/ARMSubtarget.cpp   |  1 +
 llvm/lib/Target/ARM/ARMSubtarget.h |  1 +
 llvm/lib/TargetParser/Host.cpp |  1 +
 llvm/unittests/TargetParser/TargetParserTest.cpp   |  8 +++-
 11 files changed, 33 insertions(+), 3 deletions(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 5c04465819713..6f3b6efbfe08c 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -899,6 +899,7 @@ Arm and AArch64 Support
   * Arm Cortex-A520 (cortex-a520).
   * Arm Cortex-A720 (cortex-a720).
   * Arm Cortex-X4 (cortex-x4).
+  * Arm Cortex-M52 (cortex-m52).
 
 Android Support
 ^^^
diff --git a/clang/test/CodeGen/arm-target-features.c 
b/clang/test/CodeGen/arm-target-features.c
index bd051059fb0cc..ad4bfd45c408b 100644
--- a/clang/test/CodeGen/arm-target-features.c
+++ b/clang/test/CodeGen/arm-target-features.c
@@ -113,6 +113,9 @@
 // RUN: %clang_cc1 -triple thumb-linux-gnueabi -target-cpu cortex-m85 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-ARMV81M-CORTEX-M85-LINUX
 // CHECK-ARMV81M-CORTEX-M85-LINUX: 
"target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+pacbti,+ras,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp"
 
+// RUN: %clang_cc1 -triple thumb-linux-gnueabi -target-cpu cortex-m52 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-ARMV81M-CORTEX-M52-LINUX
+// CHECK-ARMV81M-CORTEX-M52-LINUX: 
"target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+pacbti,+ras,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp"
+
 // RUN: %clang_cc1 -triple thumbv9.3a-linux-gnueabihf -emit-llvm -o - %s | 
FileCheck %s --check-prefix=CHECK-ARCH93
 // CHECK-ARCH93: 
"target-features"="+armv9.3-a,+thumb-mode,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v9.1a,+v9.2a,+v9.3a,+v9a"
 
diff --git a/clang/test/Driver/arm-cortex-cpus-2.c 
b/clang/test/Driver/arm-cortex-cpus-2.c
index 5b52488bc498f..4bf2b3a50412d 100644
--- a/clang/test/Driver/arm-cortex-cpus-2.c
+++ b/clang/test/Driver/arm-cortex-cpus-2.c
@@ -562,6 +562,9 @@
 // RUN: %clang -target arm -mcpu=cortex-m85 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CORTEX-M85 %s
 // CHECK-CORTEX-M85:  "-cc1"{{.*}} "-triple" "thumbv8.1m.main-{{.*}} 
"-target-cpu" "cortex-m85"
 
+// RUN: %clang -target arm -mcpu=cortex-m52 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CORTEX-M52 %s
+// CHECK-CORTEX-M52:  "-cc1"{{.*}} "-triple" "thumbv8.1m.main-{{.*}} 
"-target-cpu" "cortex-m52"
+
 // RUN: %clang -target arm -mcpu=neoverse-n2 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-NEOVERSE-N2 %s
 // CHECK-NEOVERSE-N2: "-cc1"{{.*}} "-triple" "armv8.5a-{{.*}}" "-target-cpu" 
"neoverse-n2"
 
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index c7146e63add5f..f921c4605bb97 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -1,7 +1,7 @@
 // Use CHECK-NEXT instead of multiple CHECK-SAME to ensure we will fail if 
there is anything extra in the output.
 // RUN: not %clang_cc1 -triple armv5--- -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix ARM
 // ARM: error: unknown target CPU 'not-a-cpu'
-// ARM-NEXT: note: valid target CPU values are: arm8, arm810, strongarm, 
strongarm110, strongarm1100, strongarm1110, arm7tdmi, arm7tdmi-s, arm710t, 
arm720t, arm9, arm9tdmi, arm920, arm920t, arm922t, arm940t, ep9312, arm10tdmi, 
arm1020t, arm9e, arm946e-s, arm966e-s, arm968e-s, arm10e, arm1020e, arm1022e, 
arm926ej-s, arm1136j-s, arm1136jf-s, mpcore, mpcorenovfp, arm1176jz-s, 
arm1176jzf-s, arm1156t2-s, arm1156t2f-s, cortex-m0, cortex-m0plus, cortex-m1, 
sc000, cortex-a5, cortex-a7, cortex-a8, cortex-a9, cortex-a12, cortex-a15, 
cortex-a17, krait, cortex-r4, cortex-r4f, cortex-r5, cortex-r7, cortex-r8, 
cortex-r52, sc300, cortex-m3, cortex-m4, cortex-m7, cortex-m23, cortex-m33, 
cortex-m35p, cortex-m55, cortex-m85, cortex-a32, cortex-a35,

[llvm] [clang] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU (PR #74822)

2023-12-08 Thread Jonathan Thackray via cfe-commits 

https://github.com/jthackray updated 
https://github.com/llvm/llvm-project/pull/74822

>From 5925f180b6a8623ae1f1497f89c1f6ef35517e4a Mon Sep 17 00:00:00 2001
From: Jonathan Thackray 
Date: Thu, 23 Nov 2023 15:54:01 +
Subject: [PATCH 1/2] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU

Cortex-M52 is an Armv8.1 AArch32 CPU.

Technical specifications available at:
  https://developer.arm.com/processors/cortex-m52
---
 clang/docs/ReleaseNotes.rst|  1 +
 clang/test/CodeGen/arm-target-features.c   |  3 +++
 clang/test/Driver/arm-cortex-cpus-2.c  |  3 +++
 clang/test/Misc/target-invalid-cpu-note.c  |  2 +-
 llvm/docs/ReleaseNotes.rst |  2 +-
 llvm/include/llvm/TargetParser/ARMTargetParser.def |  3 +++
 llvm/lib/Target/ARM/ARM.td | 11 +++
 llvm/lib/Target/ARM/ARMSubtarget.cpp   |  1 +
 llvm/lib/Target/ARM/ARMSubtarget.h |  1 +
 llvm/lib/TargetParser/Host.cpp |  1 +
 llvm/unittests/TargetParser/TargetParserTest.cpp   |  8 +++-
 11 files changed, 33 insertions(+), 3 deletions(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 5c04465819713..6f3b6efbfe08c 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -899,6 +899,7 @@ Arm and AArch64 Support
   * Arm Cortex-A520 (cortex-a520).
   * Arm Cortex-A720 (cortex-a720).
   * Arm Cortex-X4 (cortex-x4).
+  * Arm Cortex-M52 (cortex-m52).
 
 Android Support
 ^^^
diff --git a/clang/test/CodeGen/arm-target-features.c 
b/clang/test/CodeGen/arm-target-features.c
index bd051059fb0cc..ad4bfd45c408b 100644
--- a/clang/test/CodeGen/arm-target-features.c
+++ b/clang/test/CodeGen/arm-target-features.c
@@ -113,6 +113,9 @@
 // RUN: %clang_cc1 -triple thumb-linux-gnueabi -target-cpu cortex-m85 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-ARMV81M-CORTEX-M85-LINUX
 // CHECK-ARMV81M-CORTEX-M85-LINUX: 
"target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+pacbti,+ras,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp"
 
+// RUN: %clang_cc1 -triple thumb-linux-gnueabi -target-cpu cortex-m52 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-ARMV81M-CORTEX-M52-LINUX
+// CHECK-ARMV81M-CORTEX-M52-LINUX: 
"target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+pacbti,+ras,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp"
+
 // RUN: %clang_cc1 -triple thumbv9.3a-linux-gnueabihf -emit-llvm -o - %s | 
FileCheck %s --check-prefix=CHECK-ARCH93
 // CHECK-ARCH93: 
"target-features"="+armv9.3-a,+thumb-mode,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v9.1a,+v9.2a,+v9.3a,+v9a"
 
diff --git a/clang/test/Driver/arm-cortex-cpus-2.c 
b/clang/test/Driver/arm-cortex-cpus-2.c
index 5b52488bc498f..4bf2b3a50412d 100644
--- a/clang/test/Driver/arm-cortex-cpus-2.c
+++ b/clang/test/Driver/arm-cortex-cpus-2.c
@@ -562,6 +562,9 @@
 // RUN: %clang -target arm -mcpu=cortex-m85 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CORTEX-M85 %s
 // CHECK-CORTEX-M85:  "-cc1"{{.*}} "-triple" "thumbv8.1m.main-{{.*}} 
"-target-cpu" "cortex-m85"
 
+// RUN: %clang -target arm -mcpu=cortex-m52 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CORTEX-M52 %s
+// CHECK-CORTEX-M52:  "-cc1"{{.*}} "-triple" "thumbv8.1m.main-{{.*}} 
"-target-cpu" "cortex-m52"
+
 // RUN: %clang -target arm -mcpu=neoverse-n2 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-NEOVERSE-N2 %s
 // CHECK-NEOVERSE-N2: "-cc1"{{.*}} "-triple" "armv8.5a-{{.*}}" "-target-cpu" 
"neoverse-n2"
 
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index c7146e63add5f..f921c4605bb97 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -1,7 +1,7 @@
 // Use CHECK-NEXT instead of multiple CHECK-SAME to ensure we will fail if 
there is anything extra in the output.
 // RUN: not %clang_cc1 -triple armv5--- -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix ARM
 // ARM: error: unknown target CPU 'not-a-cpu'
-// ARM-NEXT: note: valid target CPU values are: arm8, arm810, strongarm, 
strongarm110, strongarm1100, strongarm1110, arm7tdmi, arm7tdmi-s, arm710t, 
arm720t, arm9, arm9tdmi, arm920, arm920t, arm922t, arm940t, ep9312, arm10tdmi, 
arm1020t, arm9e, arm946e-s, arm966e-s, arm968e-s, arm10e, arm1020e, arm1022e, 
arm926ej-s, arm1136j-s, arm1136jf-s, mpcore, mpcorenovfp, arm1176jz-s, 
arm1176jzf-s, arm1156t2-s, arm1156t2f-s, cortex-m0, cortex-m0plus, cortex-m1, 
sc000, cortex-a5, cortex-a7, cortex-a8, cortex-a9, cortex-a12, cortex-a15, 
cortex-a17, krait, cortex-r4, cortex-r4f, cortex-r5, cortex-r7, cortex-r8, 
cortex-r52, sc300, cortex-m3, cortex-m4, cortex-m7, cortex-m23, cortex-m33, 
cortex-m35p, cortex-m55, cortex-m85, cortex-a32, cortex-a35,

[llvm] [clang] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU (PR #74822)

2023-12-08 Thread David Spickett via cfe-commits 

DavidSpickett wrote:

Going by the page (didn't see a link to a manual, maybe I missed it), MVE and 
FPU are optional.

"Optional Helium technology (M-profile Vector Extension) supporting up to:"
"Optional FPU with support for half precision (fp16), single precision (fp32) 
and double precision (fp64) floating-point operations."

Is this following a pattern from previous CPUs where these things are optional, 
but users are expected to pass `+nomve` etc. to disable them? (I don't disagree 
with that, just want to keep it consistent)

https://github.com/llvm/llvm-project/pull/74822
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[llvm] [clang] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU (PR #74822)

2023-12-08 Thread via cfe-commits 

github-actions[bot] wrote:




:warning: C/C++ code formatter, clang-format found issues in your code. 
:warning:



You can test this locally with the following command:


``bash
git-clang-format --diff ea85345eb69f751fdfd793016c854605f14f9dfc 
5925f180b6a8623ae1f1497f89c1f6ef35517e4a -- 
clang/test/CodeGen/arm-target-features.c clang/test/Driver/arm-cortex-cpus-2.c 
clang/test/Misc/target-invalid-cpu-note.c llvm/lib/Target/ARM/ARMSubtarget.cpp 
llvm/lib/Target/ARM/ARMSubtarget.h llvm/lib/TargetParser/Host.cpp 
llvm/unittests/TargetParser/TargetParserTest.cpp
``





View the diff from clang-format here.


``diff
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp 
b/llvm/unittests/TargetParser/TargetParserTest.cpp
index acd0b9b9d6..c58a029b19 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -267,7 +267,8 @@ INSTANTIATE_TEST_SUITE_P(
 ARMCPUTestsPart2, ARMCPUTestFixture,
 ::testing::Values(
 ARMCPUTestParams("cortex-a9", "armv7-a", "neon-fp16",
-   ARM::AEK_MP | ARM::AEK_SEC | ARM::AEK_DSP, 
"7-A"),
+   ARM::AEK_MP | ARM::AEK_SEC | ARM::AEK_DSP,
+   "7-A"),
 ARMCPUTestParams("cortex-a12", "armv7-a", "neon-vfpv4",
ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT |
ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB 
|
@@ -284,25 +285,28 @@ INSTANTIATE_TEST_SUITE_P(
ARM::AEK_DSP,
"7-A"),
 ARMCPUTestParams("krait", "armv7-a", "neon-vfpv4",
-   ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | 
ARM::AEK_DSP,
+   ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB |
+   ARM::AEK_DSP,
"7-A"),
 ARMCPUTestParams("cortex-r4", "armv7-r", "none",
-   ARM::AEK_NONE | ARM::AEK_HWDIVTHUMB | 
ARM::AEK_DSP,
- "7-R"),
+   ARM::AEK_NONE | ARM::AEK_HWDIVTHUMB |
+   ARM::AEK_DSP,
+   "7-R"),
 ARMCPUTestParams("cortex-r4f", "armv7-r", "vfpv3-d16",
- ARM::AEK_NONE | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
- "7-R"),
-ARMCPUTestParams("cortex-r5", "armv7-r", "vfpv3-d16",
- ARM::AEK_MP | ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB 
|
+   ARM::AEK_NONE | ARM::AEK_HWDIVTHUMB |
ARM::AEK_DSP,
"7-R"),
+ARMCPUTestParams("cortex-r5", "armv7-r", "vfpv3-d16",
+   ARM::AEK_MP | ARM::AEK_HWDIVARM |
+   ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
+   "7-R"),
 ARMCPUTestParams("cortex-r7", "armv7-r", "vfpv3-d16-fp16",
-   ARM::AEK_MP | ARM::AEK_HWDIVARM | 
ARM::AEK_HWDIVTHUMB |
-   ARM::AEK_DSP,
+   ARM::AEK_MP | ARM::AEK_HWDIVARM |
+   ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
"7-R"),
 ARMCPUTestParams("cortex-r8", "armv7-r", "vfpv3-d16-fp16",
-   ARM::AEK_MP | ARM::AEK_HWDIVARM | 
ARM::AEK_HWDIVTHUMB |
- ARM::AEK_DSP,
+   ARM::AEK_MP | ARM::AEK_HWDIVARM |
+   ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
"7-R"),
 ARMCPUTestParams("cortex-r52", "armv8-r", "neon-fp-armv8",
ARM::AEK_NONE | ARM::AEK_CRC | ARM::AEK_MP |
@@ -314,171 +318,184 @@ INSTANTIATE_TEST_SUITE_P(
 ARMCPUTestParams("cortex-m3", "armv7-m", "none",
ARM::AEK_NONE | ARM::AEK_HWDIVTHUMB, "7-M"),
 ARMCPUTestParams("cortex-m4", "armv7e-m", "fpv4-sp-d16",
-   ARM::AEK_NONE | ARM::AEK_HWDIVTHUMB | 
ARM::AEK_DSP,
+   ARM::AEK_NONE | ARM::AEK_HWDIVTHUMB |
+   ARM::AEK_DSP,
"7E-M"),
 ARMCPUTestParams("cortex-m7", "armv7e-m", "fpv5-d16",
-   ARM::AEK_NONE | ARM::AEK_HWDIVTHUMB | 
ARM::AEK_DSP,
+   ARM::AEK_NONE | ARM::AEK_HWDIVTHUMB |
+   ARM::AEK_DSP,
"7E-M"),
-ARMCPUTestParams("cortex-a32", "armv8-a", 
"crypto-neon-fp-armv8",
+

[llvm] [clang] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU (PR #74822)

2023-12-08 Thread via cfe-commits 

llvmbot wrote:




@llvm/pr-subscribers-clang

Author: Jonathan Thackray (jthackray)


Changes

Cortex-M52 is an Armv8.1 AArch32 CPU.

Technical specifications available at:
  https://developer.arm.com/processors/cortex-m52


---
Full diff: https://github.com/llvm/llvm-project/pull/74822.diff


11 Files Affected:

- (modified) clang/docs/ReleaseNotes.rst (+1) 
- (modified) clang/test/CodeGen/arm-target-features.c (+3) 
- (modified) clang/test/Driver/arm-cortex-cpus-2.c (+3) 
- (modified) clang/test/Misc/target-invalid-cpu-note.c (+1-1) 
- (modified) llvm/docs/ReleaseNotes.rst (+1-1) 
- (modified) llvm/include/llvm/TargetParser/ARMTargetParser.def (+3) 
- (modified) llvm/lib/Target/ARM/ARM.td (+11) 
- (modified) llvm/lib/Target/ARM/ARMSubtarget.cpp (+1) 
- (modified) llvm/lib/Target/ARM/ARMSubtarget.h (+1) 
- (modified) llvm/lib/TargetParser/Host.cpp (+1) 
- (modified) llvm/unittests/TargetParser/TargetParserTest.cpp (+7-1) 


``diff
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 5c044658197139..6f3b6efbfe08c0 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -899,6 +899,7 @@ Arm and AArch64 Support
   * Arm Cortex-A520 (cortex-a520).
   * Arm Cortex-A720 (cortex-a720).
   * Arm Cortex-X4 (cortex-x4).
+  * Arm Cortex-M52 (cortex-m52).
 
 Android Support
 ^^^
diff --git a/clang/test/CodeGen/arm-target-features.c 
b/clang/test/CodeGen/arm-target-features.c
index bd051059fb0cc1..ad4bfd45c408b5 100644
--- a/clang/test/CodeGen/arm-target-features.c
+++ b/clang/test/CodeGen/arm-target-features.c
@@ -113,6 +113,9 @@
 // RUN: %clang_cc1 -triple thumb-linux-gnueabi -target-cpu cortex-m85 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-ARMV81M-CORTEX-M85-LINUX
 // CHECK-ARMV81M-CORTEX-M85-LINUX: 
"target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+pacbti,+ras,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp"
 
+// RUN: %clang_cc1 -triple thumb-linux-gnueabi -target-cpu cortex-m52 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-ARMV81M-CORTEX-M52-LINUX
+// CHECK-ARMV81M-CORTEX-M52-LINUX: 
"target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+pacbti,+ras,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp"
+
 // RUN: %clang_cc1 -triple thumbv9.3a-linux-gnueabihf -emit-llvm -o - %s | 
FileCheck %s --check-prefix=CHECK-ARCH93
 // CHECK-ARCH93: 
"target-features"="+armv9.3-a,+thumb-mode,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v9.1a,+v9.2a,+v9.3a,+v9a"
 
diff --git a/clang/test/Driver/arm-cortex-cpus-2.c 
b/clang/test/Driver/arm-cortex-cpus-2.c
index 5b52488bc498f3..4bf2b3a50412d0 100644
--- a/clang/test/Driver/arm-cortex-cpus-2.c
+++ b/clang/test/Driver/arm-cortex-cpus-2.c
@@ -562,6 +562,9 @@
 // RUN: %clang -target arm -mcpu=cortex-m85 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CORTEX-M85 %s
 // CHECK-CORTEX-M85:  "-cc1"{{.*}} "-triple" "thumbv8.1m.main-{{.*}} 
"-target-cpu" "cortex-m85"
 
+// RUN: %clang -target arm -mcpu=cortex-m52 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CORTEX-M52 %s
+// CHECK-CORTEX-M52:  "-cc1"{{.*}} "-triple" "thumbv8.1m.main-{{.*}} 
"-target-cpu" "cortex-m52"
+
 // RUN: %clang -target arm -mcpu=neoverse-n2 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-NEOVERSE-N2 %s
 // CHECK-NEOVERSE-N2: "-cc1"{{.*}} "-triple" "armv8.5a-{{.*}}" "-target-cpu" 
"neoverse-n2"
 
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index c7146e63add5f2..f921c4605bb976 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -1,7 +1,7 @@
 // Use CHECK-NEXT instead of multiple CHECK-SAME to ensure we will fail if 
there is anything extra in the output.
 // RUN: not %clang_cc1 -triple armv5--- -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix ARM
 // ARM: error: unknown target CPU 'not-a-cpu'
-// ARM-NEXT: note: valid target CPU values are: arm8, arm810, strongarm, 
strongarm110, strongarm1100, strongarm1110, arm7tdmi, arm7tdmi-s, arm710t, 
arm720t, arm9, arm9tdmi, arm920, arm920t, arm922t, arm940t, ep9312, arm10tdmi, 
arm1020t, arm9e, arm946e-s, arm966e-s, arm968e-s, arm10e, arm1020e, arm1022e, 
arm926ej-s, arm1136j-s, arm1136jf-s, mpcore, mpcorenovfp, arm1176jz-s, 
arm1176jzf-s, arm1156t2-s, arm1156t2f-s, cortex-m0, cortex-m0plus, cortex-m1, 
sc000, cortex-a5, cortex-a7, cortex-a8, cortex-a9, cortex-a12, cortex-a15, 
cortex-a17, krait, cortex-r4, cortex-r4f, cortex-r5, cortex-r7, cortex-r8, 
cortex-r52, sc300, cortex-m3, cortex-m4, cortex-m7, cortex-m23, cortex-m33, 
cortex-m35p, cortex-m55, cortex-m85, cortex-a32, cortex-a35, cortex-a53, 
cortex-a55, cortex-a57, cortex-a72, cortex-a73, cortex-a75, cortex-a76, 
cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-x1, 
cortex-x1c, neoverse-n1,

[llvm] [clang] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU (PR #74822)

2023-12-08 Thread Jonathan Thackray via cfe-commits 

https://github.com/jthackray created 
https://github.com/llvm/llvm-project/pull/74822

Cortex-M52 is an Armv8.1 AArch32 CPU.

Technical specifications available at:
  https://developer.arm.com/processors/cortex-m52


>From 5925f180b6a8623ae1f1497f89c1f6ef35517e4a Mon Sep 17 00:00:00 2001
From: Jonathan Thackray 
Date: Thu, 23 Nov 2023 15:54:01 +
Subject: [PATCH] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU

Cortex-M52 is an Armv8.1 AArch32 CPU.

Technical specifications available at:
  https://developer.arm.com/processors/cortex-m52
---
 clang/docs/ReleaseNotes.rst|  1 +
 clang/test/CodeGen/arm-target-features.c   |  3 +++
 clang/test/Driver/arm-cortex-cpus-2.c  |  3 +++
 clang/test/Misc/target-invalid-cpu-note.c  |  2 +-
 llvm/docs/ReleaseNotes.rst |  2 +-
 llvm/include/llvm/TargetParser/ARMTargetParser.def |  3 +++
 llvm/lib/Target/ARM/ARM.td | 11 +++
 llvm/lib/Target/ARM/ARMSubtarget.cpp   |  1 +
 llvm/lib/Target/ARM/ARMSubtarget.h |  1 +
 llvm/lib/TargetParser/Host.cpp |  1 +
 llvm/unittests/TargetParser/TargetParserTest.cpp   |  8 +++-
 11 files changed, 33 insertions(+), 3 deletions(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 5c044658197139..6f3b6efbfe08c0 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -899,6 +899,7 @@ Arm and AArch64 Support
   * Arm Cortex-A520 (cortex-a520).
   * Arm Cortex-A720 (cortex-a720).
   * Arm Cortex-X4 (cortex-x4).
+  * Arm Cortex-M52 (cortex-m52).
 
 Android Support
 ^^^
diff --git a/clang/test/CodeGen/arm-target-features.c 
b/clang/test/CodeGen/arm-target-features.c
index bd051059fb0cc1..ad4bfd45c408b5 100644
--- a/clang/test/CodeGen/arm-target-features.c
+++ b/clang/test/CodeGen/arm-target-features.c
@@ -113,6 +113,9 @@
 // RUN: %clang_cc1 -triple thumb-linux-gnueabi -target-cpu cortex-m85 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-ARMV81M-CORTEX-M85-LINUX
 // CHECK-ARMV81M-CORTEX-M85-LINUX: 
"target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+pacbti,+ras,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp"
 
+// RUN: %clang_cc1 -triple thumb-linux-gnueabi -target-cpu cortex-m52 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-ARMV81M-CORTEX-M52-LINUX
+// CHECK-ARMV81M-CORTEX-M52-LINUX: 
"target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+pacbti,+ras,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp"
+
 // RUN: %clang_cc1 -triple thumbv9.3a-linux-gnueabihf -emit-llvm -o - %s | 
FileCheck %s --check-prefix=CHECK-ARCH93
 // CHECK-ARCH93: 
"target-features"="+armv9.3-a,+thumb-mode,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v9.1a,+v9.2a,+v9.3a,+v9a"
 
diff --git a/clang/test/Driver/arm-cortex-cpus-2.c 
b/clang/test/Driver/arm-cortex-cpus-2.c
index 5b52488bc498f3..4bf2b3a50412d0 100644
--- a/clang/test/Driver/arm-cortex-cpus-2.c
+++ b/clang/test/Driver/arm-cortex-cpus-2.c
@@ -562,6 +562,9 @@
 // RUN: %clang -target arm -mcpu=cortex-m85 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CORTEX-M85 %s
 // CHECK-CORTEX-M85:  "-cc1"{{.*}} "-triple" "thumbv8.1m.main-{{.*}} 
"-target-cpu" "cortex-m85"
 
+// RUN: %clang -target arm -mcpu=cortex-m52 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CORTEX-M52 %s
+// CHECK-CORTEX-M52:  "-cc1"{{.*}} "-triple" "thumbv8.1m.main-{{.*}} 
"-target-cpu" "cortex-m52"
+
 // RUN: %clang -target arm -mcpu=neoverse-n2 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-NEOVERSE-N2 %s
 // CHECK-NEOVERSE-N2: "-cc1"{{.*}} "-triple" "armv8.5a-{{.*}}" "-target-cpu" 
"neoverse-n2"
 
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index c7146e63add5f2..f921c4605bb976 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -1,7 +1,7 @@
 // Use CHECK-NEXT instead of multiple CHECK-SAME to ensure we will fail if 
there is anything extra in the output.
 // RUN: not %clang_cc1 -triple armv5--- -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix ARM
 // ARM: error: unknown target CPU 'not-a-cpu'
-// ARM-NEXT: note: valid target CPU values are: arm8, arm810, strongarm, 
strongarm110, strongarm1100, strongarm1110, arm7tdmi, arm7tdmi-s, arm710t, 
arm720t, arm9, arm9tdmi, arm920, arm920t, arm922t, arm940t, ep9312, arm10tdmi, 
arm1020t, arm9e, arm946e-s, arm966e-s, arm968e-s, arm10e, arm1020e, arm1022e, 
arm926ej-s, arm1136j-s, arm1136jf-s, mpcore, mpcorenovfp, arm1176jz-s, 
arm1176jzf-s, arm1156t2-s, arm1156t2f-s, cortex-m0, cortex-m0plus, cortex-m1, 
sc000, cortex-a5, cortex-a7, cortex-a8, cortex-a9, cortex-a12, cortex-a15, 
cortex-a17, krait, cortex-r4, cortex-r4f, cortex-r5, cortex-r7, cortex-r8,