[llvm] [clang] [PowerPC] Implement fence builtin (PR #76495)

2023-12-28 Thread Qiu Chaofan via cfe-commits 

https://github.com/ecnelises created 
https://github.com/llvm/llvm-project/pull/76495

This builtin will work as barrier for instruction motion (scheduling, etc.)

>From aaa11bc775b9aa3a0398ba2bbca4087e99f04243 Mon Sep 17 00:00:00 2001
From: Qiu Chaofan 
Date: Thu, 28 Dec 2023 16:54:25 +0800
Subject: [PATCH] [PowerPC] Implement fence builtin

---
 clang/include/clang/Basic/BuiltinsPPC.def |  3 +++
 clang/lib/Basic/Targets/PPC.cpp   |  1 +
 llvm/include/llvm/IR/IntrinsicsPowerPC.td |  5 +
 llvm/lib/Target/PowerPC/PPCInstrInfo.cpp  |  7 ++-
 llvm/lib/Target/PowerPC/PPCInstrInfo.td   |  4 
 .../CodeGen/PowerPC/builtins-ppc-xlcompat-msync.ll| 11 +++
 6 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/clang/include/clang/Basic/BuiltinsPPC.def 
b/clang/include/clang/Basic/BuiltinsPPC.def
index a35488ed3dfa56..829c60defe17c6 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -944,6 +944,9 @@ TARGET_BUILTIN(__builtin_pack_vector_int128, 
"V1LLLiULLiULLi", "", "vsx")
 // Set the floating point rounding mode
 BUILTIN(__builtin_setrnd, "di", "")
 
+// Barrier for instruction motion
+BUILTIN(__builtin_ppc_fence, "v", "")
+
 // Get content from current FPSCR
 BUILTIN(__builtin_readflm, "d", "")
 
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index 045c273f03c7a0..41935abfb65d3b 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -212,6 +212,7 @@ static void defineXLCompatMacros(MacroBuilder &Builder) {
   Builder.defineMacro("__darn_32", "__builtin_darn_32");
   Builder.defineMacro("__darn_raw", "__builtin_darn_raw");
   Builder.defineMacro("__dcbf", "__builtin_dcbf");
+  Builder.defineMacro("__fence", "__builtin_ppc_fence");
   Builder.defineMacro("__fmadd", "__builtin_fma");
   Builder.defineMacro("__fmadds", "__builtin_fmaf");
   Builder.defineMacro("__abs", "__builtin_abs");
diff --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td 
b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
index 3ede2a3736bf30..6d1e8eb47405dd 100644
--- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -29,6 +29,11 @@ let TargetPrefix = "ppc" in {  // All intrinsics start with 
"llvm.ppc.".
 [IntrArgMemOnly, NoCapture>, ImmArg>]>;
   def int_ppc_dcbzl : Intrinsic<[], [llvm_ptr_ty], []>;
 
+  // Emit pseudo instruction as fence of instruction motion
+  def int_ppc_fence : ClangBuiltin<"__builtin_ppc_fence">,
+  DefaultAttrsIntrinsic<[], [],
+[IntrNoMerge, IntrHasSideEffects]>;
+
   // Get content from current FPSCR register
   def int_ppc_readflm : ClangBuiltin<"__builtin_readflm">,
 DefaultAttrsIntrinsic<[llvm_double_ty], [],
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp 
b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index aaced58defe603..af55c6cf337120 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -2155,11 +2155,16 @@ bool PPCInstrInfo::isPredicated(const MachineInstr &MI) 
const {
 bool PPCInstrInfo::isSchedulingBoundary(const MachineInstr &MI,
 const MachineBasicBlock *MBB,
 const MachineFunction &MF) const {
+  switch (MI.getOpcode()) {
+  default: break;
   // Set MFFS and MTFSF as scheduling boundary to avoid unexpected code motion
   // across them, since some FP operations may change content of FPSCR.
   // TODO: Model FPSCR in PPC instruction definitions and remove the workaround
-  if (MI.getOpcode() == PPC::MFFS || MI.getOpcode() == PPC::MTFSF)
+  case PPC::MFFS:
+  case PPC::MTFSF:
+  case PPC::FENCE:
 return true;
+  }
   return TargetInstrInfo::isSchedulingBoundary(MI, MBB, MF);
 }
 
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td 
b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index b1601739fd4569..c0344dfbf3a728 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -1328,6 +1328,9 @@ def SETFLM : PPCCustomInserterPseudo<(outs f8rc:$FRT), 
(ins f8rc:$FLM),
 "#SETFLM", [(set f64:$FRT, (int_ppc_setflm f8rc:$FLM))]>;
 }
 
+let isBarrier = 1, hasSideEffects = 1, Defs = [RM] in
+def FENCE : PPCEmitTimePseudo<(outs), (ins), "#FENCE", []>;
+
 let Defs = [LR] in
   def MovePCtoLR : PPCEmitTimePseudo<(outs), (ins), "#MovePCtoLR", []>,
PPC970_Unit_BRU;
@@ -3187,6 +3190,7 @@ def : Pat<(PPCtc_return (i32 texternalsym:$dst), 
imm:$imm),
 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
   (TCRETURNri CTRRC:$dst, imm:$imm)>;
 
+def : Pat<(int_ppc_fence), (FENCE)>;
 def : Pat<(int_ppc_readflm), (MFFS)>;
 def : Pat<(int_ppc_mffsl), (MFFSL)>;
 
diff --git a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-msync.ll 
b/llvm/test/CodeGen/PowerPC/builtins-ppc-xl

[llvm] [clang] [PowerPC] Implement fence builtin (PR #76495)

2023-12-28 Thread via cfe-commits 

github-actions[bot] wrote:




:warning: C/C++ code formatter, clang-format found issues in your code. 
:warning:



You can test this locally with the following command:


``bash
git-clang-format --diff 36fd7291cdd85b282950d3782758353d259e 
aaa11bc775b9aa3a0398ba2bbca4087e99f04243 -- clang/lib/Basic/Targets/PPC.cpp 
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
``





View the diff from clang-format here.


``diff
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp 
b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index af55c6cf33..538e0e6b3d 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -2156,7 +2156,8 @@ bool PPCInstrInfo::isSchedulingBoundary(const 
MachineInstr &MI,
 const MachineBasicBlock *MBB,
 const MachineFunction &MF) const {
   switch (MI.getOpcode()) {
-  default: break;
+  default:
+break;
   // Set MFFS and MTFSF as scheduling boundary to avoid unexpected code motion
   // across them, since some FP operations may change content of FPSCR.
   // TODO: Model FPSCR in PPC instruction definitions and remove the workaround

``




https://github.com/llvm/llvm-project/pull/76495
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[llvm] [clang] [PowerPC] Implement fence builtin (PR #76495)

2023-12-28 Thread Qiu Chaofan via cfe-commits 

https://github.com/ecnelises ready_for_review 
https://github.com/llvm/llvm-project/pull/76495
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[llvm] [clang] [PowerPC] Implement fence builtin (PR #76495)

2023-12-28 Thread Qiu Chaofan via cfe-commits 

https://github.com/ecnelises updated 
https://github.com/llvm/llvm-project/pull/76495

>From aaa11bc775b9aa3a0398ba2bbca4087e99f04243 Mon Sep 17 00:00:00 2001
From: Qiu Chaofan 
Date: Thu, 28 Dec 2023 16:54:25 +0800
Subject: [PATCH 1/2] [PowerPC] Implement fence builtin

---
 clang/include/clang/Basic/BuiltinsPPC.def |  3 +++
 clang/lib/Basic/Targets/PPC.cpp   |  1 +
 llvm/include/llvm/IR/IntrinsicsPowerPC.td |  5 +
 llvm/lib/Target/PowerPC/PPCInstrInfo.cpp  |  7 ++-
 llvm/lib/Target/PowerPC/PPCInstrInfo.td   |  4 
 .../CodeGen/PowerPC/builtins-ppc-xlcompat-msync.ll| 11 +++
 6 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/clang/include/clang/Basic/BuiltinsPPC.def 
b/clang/include/clang/Basic/BuiltinsPPC.def
index a35488ed3dfa56..829c60defe17c6 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -944,6 +944,9 @@ TARGET_BUILTIN(__builtin_pack_vector_int128, 
"V1LLLiULLiULLi", "", "vsx")
 // Set the floating point rounding mode
 BUILTIN(__builtin_setrnd, "di", "")
 
+// Barrier for instruction motion
+BUILTIN(__builtin_ppc_fence, "v", "")
+
 // Get content from current FPSCR
 BUILTIN(__builtin_readflm, "d", "")
 
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index 045c273f03c7a0..41935abfb65d3b 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -212,6 +212,7 @@ static void defineXLCompatMacros(MacroBuilder &Builder) {
   Builder.defineMacro("__darn_32", "__builtin_darn_32");
   Builder.defineMacro("__darn_raw", "__builtin_darn_raw");
   Builder.defineMacro("__dcbf", "__builtin_dcbf");
+  Builder.defineMacro("__fence", "__builtin_ppc_fence");
   Builder.defineMacro("__fmadd", "__builtin_fma");
   Builder.defineMacro("__fmadds", "__builtin_fmaf");
   Builder.defineMacro("__abs", "__builtin_abs");
diff --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td 
b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
index 3ede2a3736bf30..6d1e8eb47405dd 100644
--- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -29,6 +29,11 @@ let TargetPrefix = "ppc" in {  // All intrinsics start with 
"llvm.ppc.".
 [IntrArgMemOnly, NoCapture>, ImmArg>]>;
   def int_ppc_dcbzl : Intrinsic<[], [llvm_ptr_ty], []>;
 
+  // Emit pseudo instruction as fence of instruction motion
+  def int_ppc_fence : ClangBuiltin<"__builtin_ppc_fence">,
+  DefaultAttrsIntrinsic<[], [],
+[IntrNoMerge, IntrHasSideEffects]>;
+
   // Get content from current FPSCR register
   def int_ppc_readflm : ClangBuiltin<"__builtin_readflm">,
 DefaultAttrsIntrinsic<[llvm_double_ty], [],
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp 
b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index aaced58defe603..af55c6cf337120 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -2155,11 +2155,16 @@ bool PPCInstrInfo::isPredicated(const MachineInstr &MI) 
const {
 bool PPCInstrInfo::isSchedulingBoundary(const MachineInstr &MI,
 const MachineBasicBlock *MBB,
 const MachineFunction &MF) const {
+  switch (MI.getOpcode()) {
+  default: break;
   // Set MFFS and MTFSF as scheduling boundary to avoid unexpected code motion
   // across them, since some FP operations may change content of FPSCR.
   // TODO: Model FPSCR in PPC instruction definitions and remove the workaround
-  if (MI.getOpcode() == PPC::MFFS || MI.getOpcode() == PPC::MTFSF)
+  case PPC::MFFS:
+  case PPC::MTFSF:
+  case PPC::FENCE:
 return true;
+  }
   return TargetInstrInfo::isSchedulingBoundary(MI, MBB, MF);
 }
 
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td 
b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index b1601739fd4569..c0344dfbf3a728 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -1328,6 +1328,9 @@ def SETFLM : PPCCustomInserterPseudo<(outs f8rc:$FRT), 
(ins f8rc:$FLM),
 "#SETFLM", [(set f64:$FRT, (int_ppc_setflm f8rc:$FLM))]>;
 }
 
+let isBarrier = 1, hasSideEffects = 1, Defs = [RM] in
+def FENCE : PPCEmitTimePseudo<(outs), (ins), "#FENCE", []>;
+
 let Defs = [LR] in
   def MovePCtoLR : PPCEmitTimePseudo<(outs), (ins), "#MovePCtoLR", []>,
PPC970_Unit_BRU;
@@ -3187,6 +3190,7 @@ def : Pat<(PPCtc_return (i32 texternalsym:$dst), 
imm:$imm),
 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
   (TCRETURNri CTRRC:$dst, imm:$imm)>;
 
+def : Pat<(int_ppc_fence), (FENCE)>;
 def : Pat<(int_ppc_readflm), (MFFS)>;
 def : Pat<(int_ppc_mffsl), (MFFSL)>;
 
diff --git a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-msync.ll 
b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-msync.ll
index 2c9fd2034f887c..555de90c56c364 100644
--- a/llvm/te

[llvm] [clang] [PowerPC] Implement fence builtin (PR #76495)

2023-12-28 Thread Qiu Chaofan via cfe-commits 

https://github.com/ecnelises updated 
https://github.com/llvm/llvm-project/pull/76495

>From aaa11bc775b9aa3a0398ba2bbca4087e99f04243 Mon Sep 17 00:00:00 2001
From: Qiu Chaofan 
Date: Thu, 28 Dec 2023 16:54:25 +0800
Subject: [PATCH 1/3] [PowerPC] Implement fence builtin

---
 clang/include/clang/Basic/BuiltinsPPC.def |  3 +++
 clang/lib/Basic/Targets/PPC.cpp   |  1 +
 llvm/include/llvm/IR/IntrinsicsPowerPC.td |  5 +
 llvm/lib/Target/PowerPC/PPCInstrInfo.cpp  |  7 ++-
 llvm/lib/Target/PowerPC/PPCInstrInfo.td   |  4 
 .../CodeGen/PowerPC/builtins-ppc-xlcompat-msync.ll| 11 +++
 6 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/clang/include/clang/Basic/BuiltinsPPC.def 
b/clang/include/clang/Basic/BuiltinsPPC.def
index a35488ed3dfa56..829c60defe17c6 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -944,6 +944,9 @@ TARGET_BUILTIN(__builtin_pack_vector_int128, 
"V1LLLiULLiULLi", "", "vsx")
 // Set the floating point rounding mode
 BUILTIN(__builtin_setrnd, "di", "")
 
+// Barrier for instruction motion
+BUILTIN(__builtin_ppc_fence, "v", "")
+
 // Get content from current FPSCR
 BUILTIN(__builtin_readflm, "d", "")
 
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index 045c273f03c7a0..41935abfb65d3b 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -212,6 +212,7 @@ static void defineXLCompatMacros(MacroBuilder &Builder) {
   Builder.defineMacro("__darn_32", "__builtin_darn_32");
   Builder.defineMacro("__darn_raw", "__builtin_darn_raw");
   Builder.defineMacro("__dcbf", "__builtin_dcbf");
+  Builder.defineMacro("__fence", "__builtin_ppc_fence");
   Builder.defineMacro("__fmadd", "__builtin_fma");
   Builder.defineMacro("__fmadds", "__builtin_fmaf");
   Builder.defineMacro("__abs", "__builtin_abs");
diff --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td 
b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
index 3ede2a3736bf30..6d1e8eb47405dd 100644
--- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -29,6 +29,11 @@ let TargetPrefix = "ppc" in {  // All intrinsics start with 
"llvm.ppc.".
 [IntrArgMemOnly, NoCapture>, ImmArg>]>;
   def int_ppc_dcbzl : Intrinsic<[], [llvm_ptr_ty], []>;
 
+  // Emit pseudo instruction as fence of instruction motion
+  def int_ppc_fence : ClangBuiltin<"__builtin_ppc_fence">,
+  DefaultAttrsIntrinsic<[], [],
+[IntrNoMerge, IntrHasSideEffects]>;
+
   // Get content from current FPSCR register
   def int_ppc_readflm : ClangBuiltin<"__builtin_readflm">,
 DefaultAttrsIntrinsic<[llvm_double_ty], [],
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp 
b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index aaced58defe603..af55c6cf337120 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -2155,11 +2155,16 @@ bool PPCInstrInfo::isPredicated(const MachineInstr &MI) 
const {
 bool PPCInstrInfo::isSchedulingBoundary(const MachineInstr &MI,
 const MachineBasicBlock *MBB,
 const MachineFunction &MF) const {
+  switch (MI.getOpcode()) {
+  default: break;
   // Set MFFS and MTFSF as scheduling boundary to avoid unexpected code motion
   // across them, since some FP operations may change content of FPSCR.
   // TODO: Model FPSCR in PPC instruction definitions and remove the workaround
-  if (MI.getOpcode() == PPC::MFFS || MI.getOpcode() == PPC::MTFSF)
+  case PPC::MFFS:
+  case PPC::MTFSF:
+  case PPC::FENCE:
 return true;
+  }
   return TargetInstrInfo::isSchedulingBoundary(MI, MBB, MF);
 }
 
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td 
b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index b1601739fd4569..c0344dfbf3a728 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -1328,6 +1328,9 @@ def SETFLM : PPCCustomInserterPseudo<(outs f8rc:$FRT), 
(ins f8rc:$FLM),
 "#SETFLM", [(set f64:$FRT, (int_ppc_setflm f8rc:$FLM))]>;
 }
 
+let isBarrier = 1, hasSideEffects = 1, Defs = [RM] in
+def FENCE : PPCEmitTimePseudo<(outs), (ins), "#FENCE", []>;
+
 let Defs = [LR] in
   def MovePCtoLR : PPCEmitTimePseudo<(outs), (ins), "#MovePCtoLR", []>,
PPC970_Unit_BRU;
@@ -3187,6 +3190,7 @@ def : Pat<(PPCtc_return (i32 texternalsym:$dst), 
imm:$imm),
 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
   (TCRETURNri CTRRC:$dst, imm:$imm)>;
 
+def : Pat<(int_ppc_fence), (FENCE)>;
 def : Pat<(int_ppc_readflm), (MFFS)>;
 def : Pat<(int_ppc_mffsl), (MFFSL)>;
 
diff --git a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-msync.ll 
b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-msync.ll
index 2c9fd2034f887c..555de90c56c364 100644
--- a/llvm/te

[llvm] [clang] [PowerPC] Implement fence builtin (PR #76495)

2024-01-01 Thread Chen Zheng via cfe-commits 


@@ -944,6 +944,9 @@ TARGET_BUILTIN(__builtin_pack_vector_int128, 
"V1LLLiULLiULLi", "", "vsx")
 // Set the floating point rounding mode
 BUILTIN(__builtin_setrnd, "di", "")
 
+// Barrier for instruction motion

chenzheng1030 wrote:

Can we add some comments here to emphasize that `__fence` will stop code motion 
for register based instructions?

https://github.com/llvm/llvm-project/pull/76495
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[llvm] [clang] [PowerPC] Implement fence builtin (PR #76495)

2024-01-01 Thread Chen Zheng via cfe-commits 


@@ -944,6 +944,9 @@ TARGET_BUILTIN(__builtin_pack_vector_int128, 
"V1LLLiULLiULLi", "", "vsx")
 // Set the floating point rounding mode
 BUILTIN(__builtin_setrnd, "di", "")
 
+// Barrier for instruction motion
+BUILTIN(__builtin_ppc_fence, "v", "")

chenzheng1030 wrote:

nit: maybe we can put this builtin around line 100, together with other XL 
Compatibility built-ins.

https://github.com/llvm/llvm-project/pull/76495
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[llvm] [clang] [PowerPC] Implement fence builtin (PR #76495)

2024-01-01 Thread Chen Zheng via cfe-commits 

https://github.com/chenzheng1030 approved this pull request.

LGTM with nits.

https://github.com/llvm/llvm-project/pull/76495
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