llvmbot wrote:
@llvm/pr-subscribers-backend-risc-v
Author: Brandon Wu (4vtomat)
Changes
This patch models LMUL and SEW as inputs in sf_vc_x_se and sf_vc_i_se,
it reduces 42 intrinsics in the lookup table.
---
Patch is 125.78 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/79407.diff
13 Files Affected:
- (modified) clang/include/clang/Basic/riscv_sifive_vector.td (+9-20)
- (modified) clang/lib/Headers/sifive_vector.h (+102)
- (modified) clang/lib/Sema/SemaChecking.cpp (+8-48)
- (modified)
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-x-rv64.c
(+8-4)
- (modified)
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-x.c
(+106-80)
- (modified)
clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/xsfvcp-index-out-of-range.c
(+7-7)
- (modified) llvm/include/llvm/IR/IntrinsicsRISCVXsf.td (+24-20)
- (modified) llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp (+64)
- (modified) llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h (+2)
- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (-88)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td (-14)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-xsfvcp-x.ll (+80-80)
- (modified) llvm/test/CodeGen/RISCV/rvv/xsfvcp-x.ll (+80-80)
``diff
diff --git a/clang/include/clang/Basic/riscv_sifive_vector.td
b/clang/include/clang/Basic/riscv_sifive_vector.td
index ef5114d6105e48a..0761712a40fbafb 100644
--- a/clang/include/clang/Basic/riscv_sifive_vector.td
+++ b/clang/include/clang/Basic/riscv_sifive_vector.td
@@ -46,34 +46,23 @@ multiclass VCIXBuiltinSet range, string prototype,
- list intrinsic_types, bit UseGPR> {
+ list intrinsic_types, bit UseGPR,
+ string suffix = "Uv"> {
foreach r = range in
let RequiredFeatures = !if(!and(UseGPR, !eq(r, "l")),
["Xsfvcp", "RV64"], ["Xsfvcp"]) in
- defm : VCIXBuiltinSet;
+ defm : VCIXBuiltinSet;
}
-multiclass RVVVCIXBuiltinSetWVType range, string prototype,
- list intrinsic_types, bit UseGPR> {
- foreach r = range in
-let RequiredFeatures = !if(!and(UseGPR, !eq(r, "l")),
- ["Xsfvcp", "RV64"], ["Xsfvcp"]) in
- // These intrinsics don't have any vector types in the output and inputs,
- // but we still need to add vetvli for them. So we encode different
- // VTYPE into the intrinsic names, and then will know which vsetvli is
- // correct.
- foreach s = VCIXSuffix.suffix in
-// Since we already encode the Vtype into the name, so just set
-// Log2LMUL to zero. Otherwise the RISCVVEmitter will expand
-// lots of redundant intrinsic but have same names.
-let Log2LMUL = [0] in
- def : VCIXBuiltinSet;
+multiclass RVVVCIXBuiltinSetWOSuffix range, string prototype,
+ list intrinsic_types, bit UseGPR> {
+ let Log2LMUL = [0] in
+ defm NAME : RVVVCIXBuiltinSet;
}
let SupportOverloading = false in {
- defm sf_vc_x_se : RVVVCIXBuiltinSetWVType<["c", "s", "i", "l"],
"0KzKzKzUe", [0, 3], UseGPR=1>;
- defm sf_vc_i_se : RVVVCIXBuiltinSetWVType<["c", "s", "i", "l"],
"0KzKzKzKz", [2, 3], UseGPR=0>;
+ defm sf_vc_x : RVVVCIXBuiltinSetWOSuffix<["i"], "0KzKzKzUeKzKz", [0, 3],
UseGPR=1>;
+ defm sf_vc_i : RVVVCIXBuiltinSetWOSuffix<["i"], "0KzKzKzKzKzKz", [2, 3],
UseGPR=0>;
defm sf_vc_xv: RVVVCIXBuiltinSet<["csi", "l"], "0KzKzUvUe", [0, 2, 3],
UseGPR=1>;
defm sf_vc_iv: RVVVCIXBuiltinSet<["csi", "l"], "0KzKzUvKz", [0, 2, 3],
UseGPR=0>;
defm sf_vc_vv: RVVVCIXBuiltinSet<["csi", "l"], "0KzKzUvUv", [0, 2, 3],
UseGPR=0>;
diff --git a/clang/lib/Headers/sifive_vector.h
b/clang/lib/Headers/sifive_vector.h
index 42d7224db614541..2dea69947754acc 100644
--- a/clang/lib/Headers/sifive_vector.h
+++ b/clang/lib/Headers/sifive_vector.h
@@ -13,4 +13,106 @@
#pragma clang riscv intrinsic sifive_vector
+#define __riscv_sf_vc_x_se_u8mf4(p27_26, p24_20, p11_7, rs1, vl)
\
+ __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, rs1, 8, 6, vl)
+#define __riscv_sf_vc_x_se_u8mf2(p27_26, p24_20, p11_7, rs1, vl)
\
+ __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, rs1, 8, 7, vl)
+#define __riscv_sf_vc_x_se_u8m1(p27_26, p24_20, p11_7, rs1, vl)
\
+ __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, rs1, 8, 0, vl)
+#define __riscv_sf_vc_x_se_u8m2(p27_26, p24_20, p11_7, rs1, vl)
\
+ __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, rs1, 8, 1, vl)
+#define __riscv_sf_vc_x_se_u8m4(p27_26, p24_20, p11_7, rs1, vl)
\
+ __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, rs1, 8, 2, vl)
+#define __riscv_sf_vc_x_se_u8m8(p27_26, p24_20, p11_7, rs1, vl)
\
+ __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, rs1, 8, 3, vl)
+
+#define
