[llvm] [clang] [RISCV] Update the interface of sifive vqmaccqoq (PR #74284)

2023-12-05 Thread Craig Topper via cfe-commits 

https://github.com/topperc approved this pull request.

LGTM

https://github.com/llvm/llvm-project/pull/74284
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[llvm] [clang] [RISCV] Update the interface of sifive vqmaccqoq (PR #74284)

2023-12-11 Thread Brandon Wu via cfe-commits 

https://github.com/4vtomat closed 
https://github.com/llvm/llvm-project/pull/74284
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[llvm] [clang] [RISCV] Update the interface of sifive vqmaccqoq (PR #74284)

2023-12-03 Thread via cfe-commits 

llvmbot wrote:




@llvm/pr-subscribers-clang

Author: Brandon Wu (4vtomat)


Changes

The 
spec(https://sifive.cdn.prismic.io/sifive/60d5a660-3af0-49a3-a904-d2bbb1a21517_int8-matmul-spec.pdf)
 is updated.


---

Patch is 121.79 KiB, truncated to 20.00 KiB below, full version: 
https://github.com/llvm/llvm-project/pull/74284.diff


23 Files Affected:

- (modified) clang/include/clang/Basic/riscv_sifive_vector.td (+17-9) 
- (modified) 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmacc_4x8x4.c
 (+12-12) 
- (modified) 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c
 (+12-12) 
- (modified) 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c
 (+12-12) 
- (modified) 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c
 (+12-12) 
- (modified) 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmacc_4x8x4.c
 (+12-12) 
- (modified) 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccsu_4x8x4.c
 (+12-12) 
- (modified) 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccu_4x8x4.c
 (+12-12) 
- (modified) 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccus_4x8x4.c
 (+12-12) 
- (modified) 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmacc_4x8x4.c
 (+12-12) 
- (modified) 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccsu_4x8x4.c
 (+12-12) 
- (modified) 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccu_4x8x4.c
 (+12-12) 
- (modified) 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccus_4x8x4.c
 (+12-12) 
- (modified) 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmacc_4x8x4.c
 (+12-12) 
- (modified) 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccsu_4x8x4.c
 (+12-12) 
- (modified) 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccu_4x8x4.c
 (+12-12) 
- (modified) 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccus_4x8x4.c
 (+12-12) 
- (modified) clang/test/Sema/rvv-required-features.c (+2-16) 
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td (+38-23) 
- (modified) llvm/test/CodeGen/RISCV/rvv/sf_vqmacc_4x8x4.ll (+28-30) 
- (modified) llvm/test/CodeGen/RISCV/rvv/sf_vqmaccsu_4x8x4.ll (+28-30) 
- (modified) llvm/test/CodeGen/RISCV/rvv/sf_vqmaccu_4x8x4.ll (+28-30) 
- (modified) llvm/test/CodeGen/RISCV/rvv/sf_vqmaccus_4x8x4.ll (+28-30) 


``diff
diff --git a/clang/include/clang/Basic/riscv_sifive_vector.td 
b/clang/include/clang/Basic/riscv_sifive_vector.td
index bb54e26641861..61c2ff52d9f7c 100644
--- a/clang/include/clang/Basic/riscv_sifive_vector.td
+++ b/clang/include/clang/Basic/riscv_sifive_vector.td
@@ -112,7 +112,7 @@ multiclass RVVVFWMACCBuiltinSet> 
suffixes_prototypes> {
 defm NAME : RVVOutOp1Op2BuiltinSet;
 }
 
-multiclass RVVVQMACCBuiltinSet> suffixes_prototypes> {
+multiclass RVVVQMACCDODBuiltinSet> suffixes_prototypes> {
   let OverloadedName = NAME,
   Name = NAME,
   HasMasked = false,
@@ -120,6 +120,14 @@ multiclass RVVVQMACCBuiltinSet> 
suffixes_prototypes> {
 defm NAME : RVVOutOp1Op2BuiltinSet;
 }
 
+multiclass RVVVQMACCQOQBuiltinSet> suffixes_prototypes> {
+   let OverloadedName = NAME,
+   Name = NAME,
+   HasMasked = false,
+   Log2LMUL = [-1, 0, 1, 2] in
+ defm NAME : RVVOutOp1Op2BuiltinSet;
+}
+
 multiclass RVVVFNRCLIPBuiltinSet {
   let Log2LMUL = [-3, -2, -1, 0, 1, 2],
   Name = NAME,
@@ -130,18 +138,18 @@ multiclass RVVVFNRCLIPBuiltinSet;
-defm sf_vqmacc_2x8x2 : RVVVQMACCBuiltinSet<[["", "v", 
"vv(FixedSEW:8)Sv(FixedSEW:8)v"]]>;
-defm sf_vqmaccus_2x8x2 : RVVVQMACCBuiltinSet<[["", "v", 
"vv(FixedSEW:8)SUv(FixedSEW:8)v"]]>;
-defm sf_vqmaccsu_2x8x2 : RVVVQMACCBuiltinSet<[["", "v", 
"vv(FixedSEW:8)Sv(FixedSEW:8)Uv"]]>;
+defm sf_vqmaccu_2x8x2 : RVVVQMACCDODBuiltinSet<[["", "v", 
"vv(FixedSEW:8)SUv(FixedSEW:8)Uv"]]>;
+defm sf_vqmacc_2x8x2 : RVVVQMACCDODBuiltinSet<[["", "v", 
"vv(FixedSEW:8)Sv(FixedSEW:8)v"]]>;
+defm sf_vqmaccus_2x8x2 : RVVVQMACCDODBuiltinSet<[["", "v", 
"vv(FixedSEW:8)SUv(FixedSEW:8)v"]]>;
+defm sf_vqmaccsu_2x8x2 : RVVVQMACCDODBuiltinSet<[["", "v", 
"vv(FixedSEW:8)Sv(FixedSEW:8)Uv"]]>;
   }
 
 let UnMaskedPolicyScheme = HasPolicyOperand in
   let RequiredFeatures = ["Xsfvqmaccqoq"] in {
-defm sf_vqmaccu_4x8x4 : RVVVQMACCBuiltinSet<[["", "v", 
"vv(FixedSEW:8)SUv(FixedSEW:8)Uv"]]>;
-defm sf_vqmacc_4x8x4 : RVVVQMACCBuiltinSet<[["", "v", 
"vv(FixedSEW:8)Sv(FixedSEW:8)v"]]>;
-defm sf_vqmaccus_4x8x4 : RVVVQMACCBuiltinSet<[["", "v", 
"vv(FixedSEW:8)SUv(FixedSEW:8)v"]]>;
-defm sf_vqmaccsu_4x8x4 : RVVVQMACCBuiltin