[llvm] [clang-tools-extra] [RISCV] Support Global Dynamic TLSDESC in the RISC-V backend (PR #66915)

2023-12-23 Thread Craig Topper via cfe-commits


@@ -188,3 +188,8 @@ addi a2, ft0, 24 # CHECK: :[[@LINE]]:10: error: invalid 
operand for instruction
 
 # fence.tso accepts no operands
 fence.tso rw, rw # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+
+.Ltlsdesc_hi0:
+jalr   x5, 0(a1), %tlsdesc_hi(.Ltlsdesc_hi0) # CHECK: :[[@LINE]]:17: error: 
operand must be a symbol with %tlsdesc_call modifier
+jalr   x1, 0(a1), %tlsdesc_call(.Ltlsdesc_hi0) # CHECK: :[[@LINE]]:12: error: 
the output operand must be t0/x5 when using %tlsdesc_call modifier

topperc wrote:

Looks like we are missing MC layer tests that don't generate an error?

https://github.com/llvm/llvm-project/pull/66915
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[llvm] [clang-tools-extra] [RISCV] Support Global Dynamic TLSDESC in the RISC-V backend (PR #66915)

2023-12-18 Thread Paul Kirth via cfe-commits


@@ -6843,6 +6845,24 @@ SDValue 
RISCVTargetLowering::getDynamicTLSAddr(GlobalAddressSDNode *N,
   return LowerCallTo(CLI).first;
 }
 
+SDValue
+RISCVTargetLowering::getGeneralDynamicTLSDescAddr(GlobalAddressSDNode *N,

ilovepi wrote:

done.

https://github.com/llvm/llvm-project/pull/66915
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[llvm] [clang-tools-extra] [RISCV] Support Global Dynamic TLSDESC in the RISC-V backend (PR #66915)

2023-12-18 Thread Paul Kirth via cfe-commits

https://github.com/ilovepi updated 
https://github.com/llvm/llvm-project/pull/66915

>From ce9772dd519a62025cf545ded306bf40c75f2924 Mon Sep 17 00:00:00 2001
From: Paul Kirth 
Date: Tue, 19 Sep 2023 20:53:54 +
Subject: [PATCH 1/7] [RISCV] Support Global Dynamic TLSDESC in the RISC-V
 backend

This patch adds basic TLSDESC support for the global dynamic case in the
RISC-V backend by adding new relocation types for TLSDESC, as prescribed
in https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/373.

We also add a new pseudo instruction to simplify code generation.

Possible improvements for the local dynamic case will be addressed in separate
patches.

The current implementation is only enabled when passing the
-riscv-enable-tlsdesc flag.
---
 .../llvm/BinaryFormat/ELFRelocs/RISCV.def |  4 +
 .../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 97 +--
 .../RISCV/MCTargetDesc/RISCVAsmBackend.cpp|  9 ++
 .../Target/RISCV/MCTargetDesc/RISCVBaseInfo.h |  6 +-
 .../MCTargetDesc/RISCVELFObjectWriter.cpp | 15 +++
 .../RISCV/MCTargetDesc/RISCVFixupKinds.h  | 12 +++
 .../RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp | 46 +
 .../Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp | 18 
 .../Target/RISCV/MCTargetDesc/RISCVMCExpr.h   |  4 +
 llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp | 12 +++
 .../Target/RISCV/RISCVExpandPseudoInsts.cpp   | 53 ++
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp   | 23 -
 llvm/lib/Target/RISCV/RISCVISelLowering.h |  3 +
 llvm/lib/Target/RISCV/RISCVInstrInfo.cpp  |  6 +-
 llvm/lib/Target/RISCV/RISCVInstrInfo.td   | 36 +++
 llvm/lib/Target/RISCV/RISCVTargetMachine.cpp  |  4 +
 llvm/test/CodeGen/RISCV/tls-models.ll | 96 ++
 17 files changed, 432 insertions(+), 12 deletions(-)

diff --git a/llvm/include/llvm/BinaryFormat/ELFRelocs/RISCV.def 
b/llvm/include/llvm/BinaryFormat/ELFRelocs/RISCV.def
index 9a126df0153119..94420395fa0fad 100644
--- a/llvm/include/llvm/BinaryFormat/ELFRelocs/RISCV.def
+++ b/llvm/include/llvm/BinaryFormat/ELFRelocs/RISCV.def
@@ -55,3 +55,7 @@ ELF_RELOC(R_RISCV_SET32, 56)
 ELF_RELOC(R_RISCV_32_PCREL,  57)
 ELF_RELOC(R_RISCV_IRELATIVE, 58)
 ELF_RELOC(R_RISCV_PLT32, 59)
+ELF_RELOC(R_RISCV_TLSDESC_HI20,  62)
+ELF_RELOC(R_RISCV_TLSDESC_LOAD_LO12, 63)
+ELF_RELOC(R_RISCV_TLSDESC_ADD_LO12,  64)
+ELF_RELOC(R_RISCV_TLSDESC_CALL,  65)
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp 
b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 7d8d82e381313b..1303f5e85aeeb6 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -152,6 +152,7 @@ class RISCVAsmParser : public MCTargetAsmParser {
   // Helper to emit pseudo instruction "la.tls.gd" used in global-dynamic TLS
   // addressing.
   void emitLoadTLSGDAddress(MCInst , SMLoc IDLoc, MCStreamer );
+  void emitLoadTLSDescAddress(MCInst , SMLoc IDLoc, MCStreamer );
 
   // Helper to emit pseudo load/store instruction with a symbol.
   void emitLoadStoreSymbol(MCInst , unsigned Opcode, SMLoc IDLoc,
@@ -170,6 +171,12 @@ class RISCVAsmParser : public MCTargetAsmParser {
   // 'add' is an overloaded mnemonic.
   bool checkPseudoAddTPRel(MCInst , OperandVector );
 
+  // Checks that a PseudoTLSDESCCall is using x5/t0 in its output operand.
+  // Enforcing this using a restricted register class for the output
+  // operand of PseudoTLSDESCCall results in a poor diagnostic due to the fact
+  // 'jalr' is an overloaded mnemonic.
+  bool checkPseudoTLSDESCCall(MCInst , OperandVector );
+
   // Check instruction constraints.
   bool validateInstruction(MCInst , OperandVector );
 
@@ -533,6 +540,16 @@ struct RISCVOperand final : public MCParsedAsmOperand {
VK == RISCVMCExpr::VK_RISCV_TPREL_ADD;
   }
 
+  bool isTLSDESCCallSymbol() const {
+int64_t Imm;
+RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+// Must be of 'immediate' type but not a constant.
+if (!isImm() || evaluateConstantImm(getImm(), Imm, VK))
+  return false;
+return RISCVAsmParser::classifySymbolRef(getImm(), VK) &&
+   VK == RISCVMCExpr::VK_RISCV_TLSDESC_CALL;
+  }
+
   bool isCSRSystemRegister() const { return isSystemRegister(); }
 
   bool isVTypeImm(unsigned N) const {
@@ -584,7 +601,10 @@ struct RISCVOperand final : public MCParsedAsmOperand {
 if (!isImm())
   return false;
 bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
-if (VK == RISCVMCExpr::VK_RISCV_LO || VK == RISCVMCExpr::VK_RISCV_PCREL_LO)
+if (VK == RISCVMCExpr::VK_RISCV_LO ||
+VK == RISCVMCExpr::VK_RISCV_PCREL_LO ||
+VK == RISCVMCExpr::VK_RISCV_TLSDESC_LOAD_LO ||
+VK == RISCVMCExpr::VK_RISCV_TLSDESC_ADD_LO)
   return true;
 // Given only Imm, ensuring that the actually specified constant is either
 // a signed or unsigned 64-bit number is unfortunately impossible.
@@ 

[llvm] [clang-tools-extra] [RISCV] Support Global Dynamic TLSDESC in the RISC-V backend (PR #66915)

2023-12-18 Thread Fangrui Song via cfe-commits


@@ -6843,6 +6845,24 @@ SDValue 
RISCVTargetLowering::getDynamicTLSAddr(GlobalAddressSDNode *N,
   return LowerCallTo(CLI).first;
 }
 
+SDValue
+RISCVTargetLowering::getGeneralDynamicTLSDescAddr(GlobalAddressSDNode *N,

MaskRay wrote:

getTLSDescAddr sounds good.

https://github.com/llvm/llvm-project/pull/66915
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[llvm] [clang-tools-extra] [RISCV] Support Global Dynamic TLSDESC in the RISC-V backend (PR #66915)

2023-12-18 Thread Paul Kirth via cfe-commits


@@ -6843,6 +6845,24 @@ SDValue 
RISCVTargetLowering::getDynamicTLSAddr(GlobalAddressSDNode *N,
   return LowerCallTo(CLI).first;
 }
 
+SDValue
+RISCVTargetLowering::getGeneralDynamicTLSDescAddr(GlobalAddressSDNode *N,

ilovepi wrote:

Well, AArch64 handles lowering for llvm's general-dynamic and local-dynamic 
cases differently. I was trying to make it clear here that we're not trying to 
do anything fancy like elide loads of the `__MODULE_BASE__` for multiple 
accesses.  I'm not convinced we want to do that in RISC-V, so it's probably 
fine to rename this.

Maybe `getTLSDescAddr` is good enough? at least until we decide that we want to 
optimize them differently.

https://github.com/llvm/llvm-project/pull/66915
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