[mlir] [llvm] [clang] [AMDGPU] - Add address space for strided buffers (PR #74471)
https://github.com/OutOfCache updated https://github.com/llvm/llvm-project/pull/74471 >From a6e0f1170cc0a9a3c6541d16edd12f2fafbe0da0 Mon Sep 17 00:00:00 2001 From: Jessica Del Date: Tue, 5 Dec 2023 13:45:58 +0100 Subject: [PATCH 1/8] [AMDGPU] - Add address space for strided buffers This is an experimental address space for strided buffers. These buffers can have structs as elements and a stride > 1. These pointers allow the indexed access in units of stride, i.e., they point at `buffer[index * stride]`. Thus, we can use the `idxen` modifier for buffer loads. We assign address space 9 to 192-bit buffer pointers which contain a 128-bit descriptor, a 32-bit offset and a 32-bit index. Essentially, they are fat buffer pointers with an additional 32-bit index. --- llvm/docs/AMDGPUUsage.rst | 48 - llvm/include/llvm/Support/AMDGPUAddrSpace.h | 3 + llvm/lib/Target/AMDGPU/AMDGPU.h | 27 +++ .../lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 7 +- .../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 2 +- .../AMDGPU/AMDGPUTargetTransformInfo.cpp | 3 +- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 13 +++- .../CodeGen/AMDGPU/amdgpu-alias-analysis.ll | 70 +++ .../AMDGPU/vectorize-buffer-fat-pointer.ll| 19 - 9 files changed, 153 insertions(+), 39 deletions(-) diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst index 7fb3d70bbeffe..ff45efac7e848 100644 --- a/llvm/docs/AMDGPUUsage.rst +++ b/llvm/docs/AMDGPUUsage.rst @@ -703,23 +703,24 @@ supported for the ``amdgcn`` target. .. table:: AMDGPU Address Spaces :name: amdgpu-address-spaces-table - = === === === - .. 64-Bit Process Address Space - - --- --- - Address Space NameLLVM IR Address HSA Segment Hardware Address NULL Value - Space NumberNameName Size - = === === === - Generic 0 flatflat 64 0x - Global1 global global 64 0x - Region2 N/A GDS 32 *not implemented for AMDHSA* - Local 3 group LDS 32 0x - Constant 4 constant*same as global* 64 0x - Private 5 private scratch 32 0x - Constant 32-bit 6 *TODO* 0x - Buffer Fat Pointer (experimental) 7 *TODO* - Buffer Resource (experimental)8 *TODO* - Streamout Registers 128 N/A GS_REGS - = === === === + = === === === + .. 64-Bit Process Address Space + - --- --- + Address Space NameLLVM IR Address HSA Segment Hardware Address NULL Value + Space NumberNameName Size + = === === === + Generic 0 flatflat 64 0x + Global1 global global 64 0x + Region2 N/A GDS 32 *not implemented for AMDHSA* + Local 3 group LDS 32 0x + Constant 4 constant*same as global* 64 0x + Private 5 private scratch 32 0x + Constant 32-bit 6 *TODO* 0x + Buffer Fat
[mlir] [llvm] [clang] [AMDGPU] - Add address space for strided buffers (PR #74471)
@@ -864,6 +865,17 @@ supported for the ``amdgcn`` target. (bits `127:96`). The specific interpretation of these fields varies by the target architecture and is detailed in the ISA descriptions. +**Buffer Strided Pointer** + The buffer index pointer is an experimental address space. It is supposed to + model a 128-bit buffer descriptor and a 32-bit offset, like the **Buffer Fat + Pointer**. Additionally, it contains an index into the descriptor, which + allows the direct addressing of structured elements. + + The buffer descriptor must be *raw*: OutOfCache wrote: I changed the wording to avoid confusion. https://github.com/llvm/llvm-project/pull/74471 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[mlir] [llvm] [clang] [AMDGPU] - Add address space for strided buffers (PR #74471)
https://github.com/OutOfCache updated https://github.com/llvm/llvm-project/pull/74471 >From a6e0f1170cc0a9a3c6541d16edd12f2fafbe0da0 Mon Sep 17 00:00:00 2001 From: Jessica Del Date: Tue, 5 Dec 2023 13:45:58 +0100 Subject: [PATCH 1/6] [AMDGPU] - Add address space for strided buffers This is an experimental address space for strided buffers. These buffers can have structs as elements and a stride > 1. These pointers allow the indexed access in units of stride, i.e., they point at `buffer[index * stride]`. Thus, we can use the `idxen` modifier for buffer loads. We assign address space 9 to 192-bit buffer pointers which contain a 128-bit descriptor, a 32-bit offset and a 32-bit index. Essentially, they are fat buffer pointers with an additional 32-bit index. --- llvm/docs/AMDGPUUsage.rst | 48 - llvm/include/llvm/Support/AMDGPUAddrSpace.h | 3 + llvm/lib/Target/AMDGPU/AMDGPU.h | 27 +++ .../lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 7 +- .../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 2 +- .../AMDGPU/AMDGPUTargetTransformInfo.cpp | 3 +- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 13 +++- .../CodeGen/AMDGPU/amdgpu-alias-analysis.ll | 70 +++ .../AMDGPU/vectorize-buffer-fat-pointer.ll| 19 - 9 files changed, 153 insertions(+), 39 deletions(-) diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst index 7fb3d70bbeffeb..ff45efac7e8486 100644 --- a/llvm/docs/AMDGPUUsage.rst +++ b/llvm/docs/AMDGPUUsage.rst @@ -703,23 +703,24 @@ supported for the ``amdgcn`` target. .. table:: AMDGPU Address Spaces :name: amdgpu-address-spaces-table - = === === === - .. 64-Bit Process Address Space - - --- --- - Address Space NameLLVM IR Address HSA Segment Hardware Address NULL Value - Space NumberNameName Size - = === === === - Generic 0 flatflat 64 0x - Global1 global global 64 0x - Region2 N/A GDS 32 *not implemented for AMDHSA* - Local 3 group LDS 32 0x - Constant 4 constant*same as global* 64 0x - Private 5 private scratch 32 0x - Constant 32-bit 6 *TODO* 0x - Buffer Fat Pointer (experimental) 7 *TODO* - Buffer Resource (experimental)8 *TODO* - Streamout Registers 128 N/A GS_REGS - = === === === + = === === === + .. 64-Bit Process Address Space + - --- --- + Address Space NameLLVM IR Address HSA Segment Hardware Address NULL Value + Space NumberNameName Size + = === === === + Generic 0 flatflat 64 0x + Global1 global global 64 0x + Region2 N/A GDS 32 *not implemented for AMDHSA* + Local 3 group LDS 32 0x + Constant 4 constant*same as global* 64 0x + Private 5 private scratch 32 0x + Constant 32-bit 6 *TODO* 0x + Buffer Fat
[mlir] [llvm] [clang] [AMDGPU] - Add address space for strided buffers (PR #74471)
https://github.com/OutOfCache updated https://github.com/llvm/llvm-project/pull/74471 >From 94ed734c0d8864a08e3b77600dda811040270bd9 Mon Sep 17 00:00:00 2001 From: Jessica Del Date: Tue, 5 Dec 2023 13:45:58 +0100 Subject: [PATCH 1/4] [AMDGPU] - Add address space for strided buffers This is an experimental address space for strided buffers. These buffers can have structs as elements and a stride > 1. These pointers allow the indexed access in units of stride, i.e., they point at `buffer[index * stride]`. Thus, we can use the `idxen` modifier for buffer loads. We assign address space 9 to 192-bit buffer pointers which contain a 128-bit descriptor, a 32-bit offset and a 32-bit index. Essentially, they are fat buffer pointers with an additional 32-bit index. --- llvm/docs/AMDGPUUsage.rst | 48 - llvm/lib/Target/AMDGPU/AMDGPU.h | 32 + .../lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 7 +- .../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 2 +- .../AMDGPU/AMDGPUTargetTransformInfo.cpp | 3 +- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 13 +++- .../CodeGen/AMDGPU/amdgpu-alias-analysis.ll | 70 +++ .../AMDGPU/vectorize-buffer-fat-pointer.ll| 19 - 8 files changed, 154 insertions(+), 40 deletions(-) diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst index 7fb3d70bbeffe..ff45efac7e848 100644 --- a/llvm/docs/AMDGPUUsage.rst +++ b/llvm/docs/AMDGPUUsage.rst @@ -703,23 +703,24 @@ supported for the ``amdgcn`` target. .. table:: AMDGPU Address Spaces :name: amdgpu-address-spaces-table - = === === === - .. 64-Bit Process Address Space - - --- --- - Address Space NameLLVM IR Address HSA Segment Hardware Address NULL Value - Space NumberNameName Size - = === === === - Generic 0 flatflat 64 0x - Global1 global global 64 0x - Region2 N/A GDS 32 *not implemented for AMDHSA* - Local 3 group LDS 32 0x - Constant 4 constant*same as global* 64 0x - Private 5 private scratch 32 0x - Constant 32-bit 6 *TODO* 0x - Buffer Fat Pointer (experimental) 7 *TODO* - Buffer Resource (experimental)8 *TODO* - Streamout Registers 128 N/A GS_REGS - = === === === + = === === === + .. 64-Bit Process Address Space + - --- --- + Address Space NameLLVM IR Address HSA Segment Hardware Address NULL Value + Space NumberNameName Size + = === === === + Generic 0 flatflat 64 0x + Global1 global global 64 0x + Region2 N/A GDS 32 *not implemented for AMDHSA* + Local 3 group LDS 32 0x + Constant 4 constant*same as global* 64 0x + Private 5 private scratch 32 0x + Constant 32-bit 6 *TODO* 0x + Buffer Fat Pointer (experimental) 7 *TODO* +
[mlir] [llvm] [clang] [AMDGPU] - Add address space for strided buffers (PR #74471)
https://github.com/OutOfCache updated https://github.com/llvm/llvm-project/pull/74471 >From 94ed734c0d8864a08e3b77600dda811040270bd9 Mon Sep 17 00:00:00 2001 From: Jessica Del Date: Tue, 5 Dec 2023 13:45:58 +0100 Subject: [PATCH 1/2] [AMDGPU] - Add address space for strided buffers This is an experimental address space for strided buffers. These buffers can have structs as elements and a stride > 1. These pointers allow the indexed access in units of stride, i.e., they point at `buffer[index * stride]`. Thus, we can use the `idxen` modifier for buffer loads. We assign address space 9 to 192-bit buffer pointers which contain a 128-bit descriptor, a 32-bit offset and a 32-bit index. Essentially, they are fat buffer pointers with an additional 32-bit index. --- llvm/docs/AMDGPUUsage.rst | 48 - llvm/lib/Target/AMDGPU/AMDGPU.h | 32 + .../lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 7 +- .../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 2 +- .../AMDGPU/AMDGPUTargetTransformInfo.cpp | 3 +- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 13 +++- .../CodeGen/AMDGPU/amdgpu-alias-analysis.ll | 70 +++ .../AMDGPU/vectorize-buffer-fat-pointer.ll| 19 - 8 files changed, 154 insertions(+), 40 deletions(-) diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst index 7fb3d70bbeffe..ff45efac7e848 100644 --- a/llvm/docs/AMDGPUUsage.rst +++ b/llvm/docs/AMDGPUUsage.rst @@ -703,23 +703,24 @@ supported for the ``amdgcn`` target. .. table:: AMDGPU Address Spaces :name: amdgpu-address-spaces-table - = === === === - .. 64-Bit Process Address Space - - --- --- - Address Space NameLLVM IR Address HSA Segment Hardware Address NULL Value - Space NumberNameName Size - = === === === - Generic 0 flatflat 64 0x - Global1 global global 64 0x - Region2 N/A GDS 32 *not implemented for AMDHSA* - Local 3 group LDS 32 0x - Constant 4 constant*same as global* 64 0x - Private 5 private scratch 32 0x - Constant 32-bit 6 *TODO* 0x - Buffer Fat Pointer (experimental) 7 *TODO* - Buffer Resource (experimental)8 *TODO* - Streamout Registers 128 N/A GS_REGS - = === === === + = === === === + .. 64-Bit Process Address Space + - --- --- + Address Space NameLLVM IR Address HSA Segment Hardware Address NULL Value + Space NumberNameName Size + = === === === + Generic 0 flatflat 64 0x + Global1 global global 64 0x + Region2 N/A GDS 32 *not implemented for AMDHSA* + Local 3 group LDS 32 0x + Constant 4 constant*same as global* 64 0x + Private 5 private scratch 32 0x + Constant 32-bit 6 *TODO* 0x + Buffer Fat Pointer (experimental) 7 *TODO* +
