r333157 - [Sparc] Use the leon arch for Leon3's when using an external assembler
Author: dcederman
Date: Wed May 23 23:16:02 2018
New Revision: 333157
URL: http://llvm.org/viewvc/llvm-project?rev=333157&view=rev
Log:
[Sparc] Use the leon arch for Leon3's when using an external assembler
Summary: This allows the use of the casa instruction available in most Leon3's.
Reviewers: jyknight
Reviewed By: jyknight
Subscribers: joerg, fedor.sergeev, jrtc27, cfe-commits
Differential Revision: https://reviews.llvm.org/D47138
Modified:
cfe/trunk/lib/Driver/ToolChains/Arch/Sparc.cpp
cfe/trunk/test/Driver/sparc-as.c
Modified: cfe/trunk/lib/Driver/ToolChains/Arch/Sparc.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/ToolChains/Arch/Sparc.cpp?rev=333157&r1=333156&r2=333157&view=diff
==
--- cfe/trunk/lib/Driver/ToolChains/Arch/Sparc.cpp (original)
+++ cfe/trunk/lib/Driver/ToolChains/Arch/Sparc.cpp Wed May 23 23:16:02 2018
@@ -45,14 +45,29 @@ const char *sparc::getSparcAsmModeForCPU
.Case("niagara2", "-Av8plusb")
.Case("niagara3", "-Av8plusd")
.Case("niagara4", "-Av8plusd")
+.Case("ma2100", "-Aleon")
+.Case("ma2150", "-Aleon")
+.Case("ma2155", "-Aleon")
+.Case("ma2450", "-Aleon")
+.Case("ma2455", "-Aleon")
+.Case("ma2x5x", "-Aleon")
+.Case("ma2080", "-Aleon")
+.Case("ma2085", "-Aleon")
+.Case("ma2480", "-Aleon")
+.Case("ma2485", "-Aleon")
+.Case("ma2x8x", "-Aleon")
+.Case("myriad2", "-Aleon")
+.Case("myriad2.1", "-Aleon")
+.Case("myriad2.2", "-Aleon")
+.Case("myriad2.3", "-Aleon")
.Case("leon2", "-Av8")
.Case("at697e", "-Av8")
.Case("at697f", "-Av8")
-.Case("leon3", "-Av8")
+.Case("leon3", "-Aleon")
.Case("ut699", "-Av8")
-.Case("gr712rc", "-Av8")
-.Case("leon4", "-Av8")
-.Case("gr740", "-Av8")
+.Case("gr712rc", "-Aleon")
+.Case("leon4", "-Aleon")
+.Case("gr740", "-Aleon")
.Default("-Av8");
}
}
Modified: cfe/trunk/test/Driver/sparc-as.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/sparc-as.c?rev=333157&r1=333156&r2=333157&view=diff
==
--- cfe/trunk/test/Driver/sparc-as.c (original)
+++ cfe/trunk/test/Driver/sparc-as.c Wed May 23 23:16:02 2018
@@ -76,6 +76,66 @@
// RUN: -no-integrated-as --sysroot=%S/Inputs/basic_netbsd_tree %s -### 2>&1 \
// RUN: | FileCheck -check-prefix=SPARC-V8PLUSD %s
+// RUN: %clang -mcpu=ma2100 -no-canonical-prefixes -target sparc \
+// RUN: -no-integrated-as --sysroot=%S/Inputs/basic_netbsd_tree %s -### 2>&1 \
+// RUN: | FileCheck -check-prefix=SPARC-LEON %s
+
+// RUN: %clang -mcpu=ma2150 -no-canonical-prefixes -target sparc \
+// RUN: -no-integrated-as --sysroot=%S/Inputs/basic_netbsd_tree %s -### 2>&1 \
+// RUN: | FileCheck -check-prefix=SPARC-LEON %s
+
+// RUN: %clang -mcpu=ma2155 -no-canonical-prefixes -target sparc \
+// RUN: -no-integrated-as --sysroot=%S/Inputs/basic_netbsd_tree %s -### 2>&1 \
+// RUN: | FileCheck -check-prefix=SPARC-LEON %s
+
+// RUN: %clang -mcpu=ma2450 -no-canonical-prefixes -target sparc \
+// RUN: -no-integrated-as --sysroot=%S/Inputs/basic_netbsd_tree %s -### 2>&1 \
+// RUN: | FileCheck -check-prefix=SPARC-LEON %s
+
+// RUN: %clang -mcpu=ma2455 -no-canonical-prefixes -target sparc \
+// RUN: -no-integrated-as --sysroot=%S/Inputs/basic_netbsd_tree %s -### 2>&1 \
+// RUN: | FileCheck -check-prefix=SPARC-LEON %s
+
+// RUN: %clang -mcpu=ma2x5x -no-canonical-prefixes -target sparc \
+// RUN: -no-integrated-as --sysroot=%S/Inputs/basic_netbsd_tree %s -### 2>&1 \
+// RUN: | FileCheck -check-prefix=SPARC-LEON %s
+
+// RUN: %clang -mcpu=ma2080 -no-canonical-prefixes -target sparc \
+// RUN: -no-integrated-as --sysroot=%S/Inputs/basic_netbsd_tree %s -### 2>&1 \
+// RUN: | FileCheck -check-prefix=SPARC-LEON %s
+
+// RUN: %clang -mcpu=ma2085 -no-canonical-prefixes -target sparc \
+// RUN: -no-integrated-as --sysroot=%S/Inputs/basic_netbsd_tree %s -### 2>&1 \
+// RUN: | FileCheck -check-prefix=SPARC-LEON %s
+
+// RUN: %clang -mcpu=ma2480 -no-canonical-prefixes -target sparc \
+// RUN: -no-integrated-as --sysroot=%S/Inputs/basic_netbsd_tree %s -### 2>&1 \
+// RUN: | FileCheck -check-prefix=SPARC-LEON %s
+
+// RUN: %clang -mcpu=ma2485 -no-canonical-prefixes -target sparc \
+// RUN: -no-integrated-as --sysroot=%S/Inputs/basic_netbsd_tree %s -### 2>&1 \
+// RUN: | FileCheck -check-prefix=SPARC-LEON %s
+
+// RUN: %clang -mcpu=ma2x8x -no-canonical-prefixes -target sparc \
+// RUN: -no-integrated-as --sysroot=%S/Inputs/basic_netbsd_tree %s -### 2>&1 \
+// RUN: | FileCheck -check-prefix=SPARC-LEON %s
+
+// RUN: %clang -mcpu=myriad2 -no-canonical-prefixes -target sparc \
+// RUN: -no-integrated-as --sysroot=%S/Inputs/basic_netbsd_tree %s -### 2>&1 \
+// RUN: | FileCheck -check-prefix=SPARC-LEON %s
+
+// RUN:
r333510 - [Sparc] Add floating-point register names
Author: dcederman
Date: Tue May 29 23:02:18 2018
New Revision: 333510
URL: http://llvm.org/viewvc/llvm-project?rev=333510&view=rev
Log:
[Sparc] Add floating-point register names
Reviewers: jyknight
Reviewed By: jyknight
Subscribers: eraman, fedor.sergeev, jrtc27, cfe-commits
Differential Revision: https://reviews.llvm.org/D47137
Added:
cfe/trunk/test/CodeGen/sparcv9-inline-asm.c
Modified:
cfe/trunk/lib/Basic/Targets/Sparc.cpp
cfe/trunk/test/CodeGen/sparcv8-inline-asm.c
Modified: cfe/trunk/lib/Basic/Targets/Sparc.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/Sparc.cpp?rev=333510&r1=333509&r2=333510&view=diff
==
--- cfe/trunk/lib/Basic/Targets/Sparc.cpp (original)
+++ cfe/trunk/lib/Basic/Targets/Sparc.cpp Tue May 29 23:02:18 2018
@@ -20,9 +20,17 @@ using namespace clang;
using namespace clang::targets;
const char *const SparcTargetInfo::GCCRegNames[] = {
+// Integer registers
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9",
"r10",
"r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20",
"r21",
-"r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
+"r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
+
+// Floating-point registers
+"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9",
"f10",
+"f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", "f20",
"f21",
+"f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
"f32",
+"f34", "f36", "f38", "f40", "f42", "f44", "f46", "f48", "f50", "f52",
"f54",
+"f56", "f58", "f60", "f62",
};
ArrayRef SparcTargetInfo::getGCCRegNames() const {
Modified: cfe/trunk/test/CodeGen/sparcv8-inline-asm.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/sparcv8-inline-asm.c?rev=333510&r1=333509&r2=333510&view=diff
==
--- cfe/trunk/test/CodeGen/sparcv8-inline-asm.c (original)
+++ cfe/trunk/test/CodeGen/sparcv8-inline-asm.c Tue May 29 23:02:18 2018
@@ -1,7 +1,7 @@
// RUN: %clang_cc1 -triple sparc-unknown-unknown -emit-llvm %s -o - |
FileCheck %s
// CHECK: define float @fabsf(float %a)
-// CHECK: %{{.*}} = call float asm sideeffect "fabss $1, $0;", "=e,f"(float
%{{.*}}) #1
+// CHECK: %{{.*}} = call float asm sideeffect "fabss $1, $0;", "=e,f"(float
%{{.*}})
float fabsf(float a) {
float res;
__asm __volatile__("fabss %1, %0;"
@@ -9,3 +9,34 @@ float fabsf(float a) {
: /* reg in */ "f"(a));
return res;
}
+
+void test_gcc_registers(void) {
+register unsigned int regO6 asm("o6") = 0;
+register unsigned int regSP asm("sp") = 1;
+register unsigned int reg14 asm("r14") = 2;
+register unsigned int regI6 asm("i6") = 3;
+register unsigned int regFP asm("fp") = 4;
+register unsigned int reg30 asm("r30") = 5;
+
+register float fF20 asm("f20") = 8.0;
+register double dF20 asm("f20") = 11.0;
+register long double qF20 asm("f20") = 14.0;
+
+// Test remapping register names in register ... asm("rN") statments.
+
+// CHECK: call void asm sideeffect "add $0,$1,$2", "{r14},{r14},{r14}"
+asm volatile("add %0,%1,%2" : : "r" (regO6), "r" (regSP), "r" (reg14));
+
+// CHECK: call void asm sideeffect "add $0,$1,$2", "{r30},{r30},{r30}"
+asm volatile("add %0,%1,%2" : : "r" (regI6), "r" (regFP), "r" (reg30));
+
+ // CHECK: call void asm sideeffect "fadds $0,$1,$2", "{f20},{f20},{f20}"
+asm volatile("fadds %0,%1,%2" : : "f" (fF20), "f" (fF20), "f"(fF20));
+
+// CHECK: call void asm sideeffect "faddd $0,$1,$2", "{f20},{f20},{f20}"
+asm volatile("faddd %0,%1,%2" : : "f" (dF20), "f" (dF20), "f"(dF20));
+
+// CHECK: call void asm sideeffect "faddq $0,$1,$2", "{f20},{f20},{f20}"
+asm volatile("faddq %0,%1,%2" : : "f" (qF20), "f" (qF20), "f"(qF20));
+
+}
Added: cfe/trunk/test/CodeGen/sparcv9-inline-asm.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/sparcv9-inline-asm.c?rev=333510&view=auto
==
--- cfe/trunk/test/CodeGen/sparcv9-inline-asm.c (added)
+++ cfe/trunk/test/CodeGen/sparcv9-inline-asm.c Tue May 29 23:02:18 2018
@@ -0,0 +1,32 @@
+// RUN: %clang_cc1 -triple sparcv9-unknown-unknown -emit-llvm %s -o - |
FileCheck %s
+
+void test_gcc_registers(void) {
+register unsigned int regO6 asm("o6") = 0;
+register unsigned int regSP asm("sp") = 1;
+register unsigned int reg14 asm("r14") = 2;
+register unsigned int regI6 asm("i6") = 3;
+register unsigned int regFP asm("fp") = 4;
+register unsigned int reg30 asm("r30") = 5;
+
+register float fF20 asm("f20") = 8.0;
+register double dF40 asm("f40") = 11.0;
+register long double qF40 asm("f40") = 14.0;
+
+// Test remapping register names in register ..
[libunwind] r351044 - [Sparc] Add Sparc V8 support
Author: dcederman
Date: Mon Jan 14 02:15:20 2019
New Revision: 351044
URL: http://llvm.org/viewvc/llvm-project?rev=351044&view=rev
Log:
[Sparc] Add Sparc V8 support
Summary:
Adds the register class implementation for Sparc.
Adds support for DW_CFA_GNU_window_save.
Adds save and restore context functionality.
Adds getArch() function to each Registers_ class to be able to separate
between DW_CFA_AARCH64_negate_ra_state and DW_CFA_GNU_window_save which
are both represented by the same constant.
On Sparc the return address is the address of the call instruction, so
an offset needs to be added when returning to skip the call instruction
and its delay slot. If the function returns a struct it is also necessary
to skip one extra instruction on Sparc V8.
Reviewers: jyknight, mclow.lists, mstorsjo, compnerd
Reviewed By: jyknight, compnerd
Subscribers: jgorbe, mgorny, christof, llvm-commits, fedor.sergeev,
JDevlieghere, ldionne, libcxx-commits
Differential Revision: https://reviews.llvm.org/D55763
Modified:
libunwind/trunk/include/__libunwind_config.h
libunwind/trunk/include/libunwind.h
libunwind/trunk/src/DwarfInstructions.hpp
libunwind/trunk/src/DwarfParser.hpp
libunwind/trunk/src/Registers.hpp
libunwind/trunk/src/UnwindCursor.hpp
libunwind/trunk/src/UnwindRegistersRestore.S
libunwind/trunk/src/UnwindRegistersSave.S
libunwind/trunk/src/assembly.h
libunwind/trunk/src/libunwind.cpp
Modified: libunwind/trunk/include/__libunwind_config.h
URL:
http://llvm.org/viewvc/llvm-project/libunwind/trunk/include/__libunwind_config.h?rev=351044&r1=351043&r2=351044&view=diff
==
--- libunwind/trunk/include/__libunwind_config.h (original)
+++ libunwind/trunk/include/__libunwind_config.h Mon Jan 14 02:15:20 2019
@@ -23,6 +23,7 @@
#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_ARM 287
#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_OR1K 32
#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_MIPS 65
+#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_SPARC 31
#if defined(_LIBUNWIND_IS_NATIVE_ONLY)
# if defined(__i386__)
@@ -113,6 +114,11 @@
#error "Unsupported MIPS ABI and/or environment"
# endif
# define _LIBUNWIND_HIGHEST_DWARF_REGISTER
_LIBUNWIND_HIGHEST_DWARF_REGISTER_MIPS
+# elif defined(__sparc__)
+ #define _LIBUNWIND_TARGET_SPARC 1
+ #define _LIBUNWIND_HIGHEST_DWARF_REGISTER
_LIBUNWIND_HIGHEST_DWARF_REGISTER_SPARC
+ #define _LIBUNWIND_CONTEXT_SIZE 16
+ #define _LIBUNWIND_CURSOR_SIZE 23
# else
# error "Unsupported architecture."
# endif
@@ -126,6 +132,7 @@
# define _LIBUNWIND_TARGET_OR1K 1
# define _LIBUNWIND_TARGET_MIPS_O32 1
# define _LIBUNWIND_TARGET_MIPS_NEWABI 1
+# define _LIBUNWIND_TARGET_SPARC 1
# define _LIBUNWIND_CONTEXT_SIZE 167
# define _LIBUNWIND_CURSOR_SIZE 179
# define _LIBUNWIND_HIGHEST_DWARF_REGISTER 287
Modified: libunwind/trunk/include/libunwind.h
URL:
http://llvm.org/viewvc/llvm-project/libunwind/trunk/include/libunwind.h?rev=351044&r1=351043&r2=351044&view=diff
==
--- libunwind/trunk/include/libunwind.h (original)
+++ libunwind/trunk/include/libunwind.h Mon Jan 14 02:15:20 2019
@@ -823,4 +823,40 @@ enum {
UNW_MIPS_LO = 65,
};
+// SPARC registers
+enum {
+ UNW_SPARC_G0 = 0,
+ UNW_SPARC_G1 = 1,
+ UNW_SPARC_G2 = 2,
+ UNW_SPARC_G3 = 3,
+ UNW_SPARC_G4 = 4,
+ UNW_SPARC_G5 = 5,
+ UNW_SPARC_G6 = 6,
+ UNW_SPARC_G7 = 7,
+ UNW_SPARC_O0 = 8,
+ UNW_SPARC_O1 = 9,
+ UNW_SPARC_O2 = 10,
+ UNW_SPARC_O3 = 11,
+ UNW_SPARC_O4 = 12,
+ UNW_SPARC_O5 = 13,
+ UNW_SPARC_O6 = 14,
+ UNW_SPARC_O7 = 15,
+ UNW_SPARC_L0 = 16,
+ UNW_SPARC_L1 = 17,
+ UNW_SPARC_L2 = 18,
+ UNW_SPARC_L3 = 19,
+ UNW_SPARC_L4 = 20,
+ UNW_SPARC_L5 = 21,
+ UNW_SPARC_L6 = 22,
+ UNW_SPARC_L7 = 23,
+ UNW_SPARC_I0 = 24,
+ UNW_SPARC_I1 = 25,
+ UNW_SPARC_I2 = 26,
+ UNW_SPARC_I3 = 27,
+ UNW_SPARC_I4 = 28,
+ UNW_SPARC_I5 = 29,
+ UNW_SPARC_I6 = 30,
+ UNW_SPARC_I7 = 31,
+};
+
#endif
Modified: libunwind/trunk/src/DwarfInstructions.hpp
URL:
http://llvm.org/viewvc/llvm-project/libunwind/trunk/src/DwarfInstructions.hpp?rev=351044&r1=351043&r2=351044&view=diff
==
--- libunwind/trunk/src/DwarfInstructions.hpp (original)
+++ libunwind/trunk/src/DwarfInstructions.hpp Mon Jan 14 02:15:20 2019
@@ -159,7 +159,7 @@ int DwarfInstructions::stepWithDwa
&cieInfo) == NULL) {
PrologInfo prolog;
if (CFI_Parser::parseFDEInstructions(addressSpace, fdeInfo, cieInfo, pc,
-&prolog)) {
+R::getArch(), &prolog)) {
// get pointer to cfa (architecture specific)
pint_t cfa = getCFA(addressSpace, prolog, registers);
@@ -204,7 +204,8 @@ int DwarfInstructions::stepWithDwa
// return address needs to be authenticated before
[libunwind] r350705 - [Sparc] Add Sparc V8 support
Author: dcederman
Date: Wed Jan 9 04:06:05 2019
New Revision: 350705
URL: http://llvm.org/viewvc/llvm-project?rev=350705&view=rev
Log:
[Sparc] Add Sparc V8 support
Summary:
Adds the register class implementation for Sparc.
Adds support for DW_CFA_GNU_window_save.
Adds save and restore context functionality.
On Sparc the return address is the address of the call instruction,
so an offset needs to be added when returning to skip the call instruction
and its delay slot. If the function returns a struct it is also necessary
to skip one extra instruction.
Reviewers: jyknight, mclow.lists, mstorsjo, compnerd
Reviewed By: compnerd
Subscribers: fedor.sergeev, JDevlieghere, ldionne, libcxx-commits
Differential Revision: https://reviews.llvm.org/D55763
Modified:
libunwind/trunk/include/__libunwind_config.h
libunwind/trunk/include/libunwind.h
libunwind/trunk/src/DwarfInstructions.hpp
libunwind/trunk/src/DwarfParser.hpp
libunwind/trunk/src/Registers.hpp
libunwind/trunk/src/UnwindCursor.hpp
libunwind/trunk/src/UnwindRegistersRestore.S
libunwind/trunk/src/UnwindRegistersSave.S
libunwind/trunk/src/assembly.h
libunwind/trunk/src/libunwind.cpp
Modified: libunwind/trunk/include/__libunwind_config.h
URL:
http://llvm.org/viewvc/llvm-project/libunwind/trunk/include/__libunwind_config.h?rev=350705&r1=350704&r2=350705&view=diff
==
--- libunwind/trunk/include/__libunwind_config.h (original)
+++ libunwind/trunk/include/__libunwind_config.h Wed Jan 9 04:06:05 2019
@@ -23,6 +23,7 @@
#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_ARM 287
#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_OR1K 32
#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_MIPS 65
+#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_SPARC 31
#if defined(_LIBUNWIND_IS_NATIVE_ONLY)
# if defined(__i386__)
@@ -113,6 +114,11 @@
#error "Unsupported MIPS ABI and/or environment"
# endif
# define _LIBUNWIND_HIGHEST_DWARF_REGISTER
_LIBUNWIND_HIGHEST_DWARF_REGISTER_MIPS
+# elif defined(__sparc__)
+ #define _LIBUNWIND_TARGET_SPARC 1
+ #define _LIBUNWIND_HIGHEST_DWARF_REGISTER
_LIBUNWIND_HIGHEST_DWARF_REGISTER_SPARC
+ #define _LIBUNWIND_CONTEXT_SIZE 16
+ #define _LIBUNWIND_CURSOR_SIZE 23
# else
# error "Unsupported architecture."
# endif
@@ -126,6 +132,7 @@
# define _LIBUNWIND_TARGET_OR1K 1
# define _LIBUNWIND_TARGET_MIPS_O32 1
# define _LIBUNWIND_TARGET_MIPS_NEWABI 1
+# define _LIBUNWIND_TARGET_SPARC 1
# define _LIBUNWIND_CONTEXT_SIZE 167
# define _LIBUNWIND_CURSOR_SIZE 179
# define _LIBUNWIND_HIGHEST_DWARF_REGISTER 287
Modified: libunwind/trunk/include/libunwind.h
URL:
http://llvm.org/viewvc/llvm-project/libunwind/trunk/include/libunwind.h?rev=350705&r1=350704&r2=350705&view=diff
==
--- libunwind/trunk/include/libunwind.h (original)
+++ libunwind/trunk/include/libunwind.h Wed Jan 9 04:06:05 2019
@@ -823,4 +823,40 @@ enum {
UNW_MIPS_LO = 65,
};
+// SPARC registers
+enum {
+ UNW_SPARC_G0 = 0,
+ UNW_SPARC_G1 = 1,
+ UNW_SPARC_G2 = 2,
+ UNW_SPARC_G3 = 3,
+ UNW_SPARC_G4 = 4,
+ UNW_SPARC_G5 = 5,
+ UNW_SPARC_G6 = 6,
+ UNW_SPARC_G7 = 7,
+ UNW_SPARC_O0 = 8,
+ UNW_SPARC_O1 = 9,
+ UNW_SPARC_O2 = 10,
+ UNW_SPARC_O3 = 11,
+ UNW_SPARC_O4 = 12,
+ UNW_SPARC_O5 = 13,
+ UNW_SPARC_O6 = 14,
+ UNW_SPARC_O7 = 15,
+ UNW_SPARC_L0 = 16,
+ UNW_SPARC_L1 = 17,
+ UNW_SPARC_L2 = 18,
+ UNW_SPARC_L3 = 19,
+ UNW_SPARC_L4 = 20,
+ UNW_SPARC_L5 = 21,
+ UNW_SPARC_L6 = 22,
+ UNW_SPARC_L7 = 23,
+ UNW_SPARC_I0 = 24,
+ UNW_SPARC_I1 = 25,
+ UNW_SPARC_I2 = 26,
+ UNW_SPARC_I3 = 27,
+ UNW_SPARC_I4 = 28,
+ UNW_SPARC_I5 = 29,
+ UNW_SPARC_I6 = 30,
+ UNW_SPARC_I7 = 31,
+};
+
#endif
Modified: libunwind/trunk/src/DwarfInstructions.hpp
URL:
http://llvm.org/viewvc/llvm-project/libunwind/trunk/src/DwarfInstructions.hpp?rev=350705&r1=350704&r2=350705&view=diff
==
--- libunwind/trunk/src/DwarfInstructions.hpp (original)
+++ libunwind/trunk/src/DwarfInstructions.hpp Wed Jan 9 04:06:05 2019
@@ -223,6 +223,14 @@ int DwarfInstructions::stepWithDwa
}
#endif
+#if defined(_LIBUNWIND_TARGET_SPARC)
+ // Skip call site instruction and delay slot
+ returnAddress += 8;
+ // Skip unimp instruction if function returns a struct
+ if ((addressSpace.get32(returnAddress) & 0xC1C0) == 0)
+returnAddress += 4;
+#endif
+
// Return address is address after call site instruction, so setting IP
to
// that does simualates a return.
newRegisters.setIP(returnAddress);
Modified: libunwind/trunk/src/DwarfParser.hpp
URL:
http://llvm.org/viewvc/llvm-project/libunwind/trunk/src/DwarfParser.hpp?rev=350705&r1=350704&r2=350705&view=diff
==
--- libunwind/trunk/src/DwarfParser.hpp (origin
[clang] [Sparc] Add flags to enable errata workaround pass for GR712RC and UT700 (PR #104742)
https://github.com/doac created https://github.com/llvm/llvm-project/pull/104742
This adds the flags -mfix-gr712rc and -mfix-ut700 which enables the necessary
errata workarounds for the GR712RC and UT700 processors. The functionality
enabled by the flags is the same as the functionality provided by the
corresponding GCC flags.
>From a68dec7b074afdc003c63e721cd384c9c6721610 Mon Sep 17 00:00:00 2001
From: Daniel Cederman
Date: Mon, 19 Aug 2024 08:17:36 +0200
Subject: [PATCH] [Sparc] Add flags to enable errata workaround pass for
GR712RC and UT700
This adds the flags -mfix-gr712rc and -mfix-ut700 which enables the
necessary errata workarounds for the GR712RC and UT700 processors.
The functionality enabled by the flag is the same as the functionality
provided by the corresponding GCC flag.
---
clang/include/clang/Driver/Options.td | 4
clang/lib/Driver/ToolChains/Arch/Sparc.cpp | 13 +
clang/test/Driver/sparc-fix.c | 12
3 files changed, 29 insertions(+)
create mode 100644 clang/test/Driver/sparc-fix.c
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index cfd9e595c55178..0ef3a2dbd69ae3 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -6148,6 +6148,10 @@ def mv8plus : Flag<["-"], "mv8plus">,
Group,
HelpText<"Enable V8+ mode, allowing use of 64-bit V9 instructions in 32-bit
code">;
def mno_v8plus : Flag<["-"], "mno-v8plus">, Group,
HelpText<"Disable V8+ mode">;
+def mfix_gr712rc : Flag<["-"], "mfix-gr712rc">, Group,
+ HelpText<"Enable workarounds for GR712RC errata">;
+def mfix_ut700 : Flag<["-"], "mfix-ut700">, Group,
+ HelpText<"Enable workarounds for UT700 errata">;
foreach i = 1 ... 7 in
def ffixed_g#i : Flag<["-"], "ffixed-g"#i>, Group,
HelpText<"Reserve the G"#i#" register (SPARC only)">;
diff --git a/clang/lib/Driver/ToolChains/Arch/Sparc.cpp
b/clang/lib/Driver/ToolChains/Arch/Sparc.cpp
index 5a1fedbec06adf..f7f0a265fef68b 100644
--- a/clang/lib/Driver/ToolChains/Arch/Sparc.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/Sparc.cpp
@@ -264,4 +264,17 @@ void sparc::getSparcTargetFeatures(const Driver &D, const
ArgList &Args,
if (Args.hasArg(options::OPT_ffixed_i5))
Features.push_back("+reserve-i5");
+
+ if (Args.hasArg(options::OPT_mfix_gr712rc)) {
+Features.push_back("+fix-tn0009");
+Features.push_back("+fix-tn0011");
+Features.push_back("+fix-tn0012");
+Features.push_back("+fix-tn0013");
+ }
+
+ if (Args.hasArg(options::OPT_mfix_ut700)) {
+Features.push_back("+fix-tn0009");
+Features.push_back("+fix-tn0010");
+Features.push_back("+fix-tn0013");
+ }
}
diff --git a/clang/test/Driver/sparc-fix.c b/clang/test/Driver/sparc-fix.c
new file mode 100644
index 00..2b4bc4117adb68
--- /dev/null
+++ b/clang/test/Driver/sparc-fix.c
@@ -0,0 +1,12 @@
+// RUN: %clang -target sparc -mfix-gr712rc -### %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-FIX-GR712RC < %t %s
+// CHECK-FIX-GR712RC: "-target-feature" "+fix-tn0009"
+// CHECK-FIX-GR712RC: "-target-feature" "+fix-tn0011"
+// CHECK-FIX-GR712RC: "-target-feature" "+fix-tn0012"
+// CHECK-FIX-GR712RC: "-target-feature" "+fix-tn0013"
+
+// RUN: %clang -target sparc -mfix-ut700 -### %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-FIX-UT700 < %t %s
+// CHECK-FIX-UT700: "-target-feature" "+fix-tn0009"
+// CHECK-FIX-UT700: "-target-feature" "+fix-tn0010"
+// CHECK-FIX-UT700: "-target-feature" "+fix-tn0013"
___
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cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Sparc] Add flags to enable errata workaround pass for GR712RC and UT700 (PR #104742)
doac wrote: Thank you for your comments! https://github.com/llvm/llvm-project/pull/104742 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Sparc] Add flags to enable errata workaround pass for GR712RC and UT700 (PR #104742)
https://github.com/doac updated https://github.com/llvm/llvm-project/pull/104742
>From a68dec7b074afdc003c63e721cd384c9c6721610 Mon Sep 17 00:00:00 2001
From: Daniel Cederman
Date: Mon, 19 Aug 2024 08:17:36 +0200
Subject: [PATCH 1/3] [Sparc] Add flags to enable errata workaround pass for
GR712RC and UT700
This adds the flags -mfix-gr712rc and -mfix-ut700 which enables the
necessary errata workarounds for the GR712RC and UT700 processors.
The functionality enabled by the flag is the same as the functionality
provided by the corresponding GCC flag.
---
clang/include/clang/Driver/Options.td | 4
clang/lib/Driver/ToolChains/Arch/Sparc.cpp | 13 +
clang/test/Driver/sparc-fix.c | 12
3 files changed, 29 insertions(+)
create mode 100644 clang/test/Driver/sparc-fix.c
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index cfd9e595c55178..0ef3a2dbd69ae3 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -6148,6 +6148,10 @@ def mv8plus : Flag<["-"], "mv8plus">,
Group,
HelpText<"Enable V8+ mode, allowing use of 64-bit V9 instructions in 32-bit
code">;
def mno_v8plus : Flag<["-"], "mno-v8plus">, Group,
HelpText<"Disable V8+ mode">;
+def mfix_gr712rc : Flag<["-"], "mfix-gr712rc">, Group,
+ HelpText<"Enable workarounds for GR712RC errata">;
+def mfix_ut700 : Flag<["-"], "mfix-ut700">, Group,
+ HelpText<"Enable workarounds for UT700 errata">;
foreach i = 1 ... 7 in
def ffixed_g#i : Flag<["-"], "ffixed-g"#i>, Group,
HelpText<"Reserve the G"#i#" register (SPARC only)">;
diff --git a/clang/lib/Driver/ToolChains/Arch/Sparc.cpp
b/clang/lib/Driver/ToolChains/Arch/Sparc.cpp
index 5a1fedbec06adf..f7f0a265fef68b 100644
--- a/clang/lib/Driver/ToolChains/Arch/Sparc.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/Sparc.cpp
@@ -264,4 +264,17 @@ void sparc::getSparcTargetFeatures(const Driver &D, const
ArgList &Args,
if (Args.hasArg(options::OPT_ffixed_i5))
Features.push_back("+reserve-i5");
+
+ if (Args.hasArg(options::OPT_mfix_gr712rc)) {
+Features.push_back("+fix-tn0009");
+Features.push_back("+fix-tn0011");
+Features.push_back("+fix-tn0012");
+Features.push_back("+fix-tn0013");
+ }
+
+ if (Args.hasArg(options::OPT_mfix_ut700)) {
+Features.push_back("+fix-tn0009");
+Features.push_back("+fix-tn0010");
+Features.push_back("+fix-tn0013");
+ }
}
diff --git a/clang/test/Driver/sparc-fix.c b/clang/test/Driver/sparc-fix.c
new file mode 100644
index 00..2b4bc4117adb68
--- /dev/null
+++ b/clang/test/Driver/sparc-fix.c
@@ -0,0 +1,12 @@
+// RUN: %clang -target sparc -mfix-gr712rc -### %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-FIX-GR712RC < %t %s
+// CHECK-FIX-GR712RC: "-target-feature" "+fix-tn0009"
+// CHECK-FIX-GR712RC: "-target-feature" "+fix-tn0011"
+// CHECK-FIX-GR712RC: "-target-feature" "+fix-tn0012"
+// CHECK-FIX-GR712RC: "-target-feature" "+fix-tn0013"
+
+// RUN: %clang -target sparc -mfix-ut700 -### %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-FIX-UT700 < %t %s
+// CHECK-FIX-UT700: "-target-feature" "+fix-tn0009"
+// CHECK-FIX-UT700: "-target-feature" "+fix-tn0010"
+// CHECK-FIX-UT700: "-target-feature" "+fix-tn0013"
>From a4ee7ebd69db218a1084e44fee35832a169f7c7e Mon Sep 17 00:00:00 2001
From: Daniel Cederman
Date: Tue, 20 Aug 2024 09:46:53 +0200
Subject: [PATCH 2/3] [Sparc] Use --target= instead of -target
---
clang/test/Driver/sparc-fix.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/clang/test/Driver/sparc-fix.c b/clang/test/Driver/sparc-fix.c
index 2b4bc4117adb68..f2815c721db9b8 100644
--- a/clang/test/Driver/sparc-fix.c
+++ b/clang/test/Driver/sparc-fix.c
@@ -1,11 +1,11 @@
-// RUN: %clang -target sparc -mfix-gr712rc -### %s 2> %t
+// RUN: %clang --target=sparc -mfix-gr712rc -### %s 2> %t
// RUN: FileCheck --check-prefix=CHECK-FIX-GR712RC < %t %s
// CHECK-FIX-GR712RC: "-target-feature" "+fix-tn0009"
// CHECK-FIX-GR712RC: "-target-feature" "+fix-tn0011"
// CHECK-FIX-GR712RC: "-target-feature" "+fix-tn0012"
// CHECK-FIX-GR712RC: "-target-feature" "+fix-tn0013"
-// RUN: %clang -target sparc -mfix-ut700 -### %s 2> %t
+// RUN: %clang --target=sparc -mfix-ut700 -### %s 2> %t
// RUN: FileCheck --check-prefix=CHECK-FIX-UT700 < %t %s
// CHECK-FIX-UT700: "-target-feature" "+fix-tn0009"
// CHECK-FIX-UT700: "-target-feature" "+fix-tn0010"
>From 2a3d7aa43733908a5e4d498f6b6e1c7f73e5deb7 Mon Sep 17 00:00:00 2001
From: Daniel Cederman
Date: Tue, 20 Aug 2024 09:48:33 +0200
Subject: [PATCH 3/3] [Sparc] Place checks for same target on same line
---
clang/test/Driver/sparc-fix.c | 15 ---
1 file changed, 4 insertions(+), 11 deletions(-)
diff --git a/clang/test/Driver/sparc-fix.c b/clang/test/Driver/sparc-fix.c
index f2815c721db9b8..1f034399ce2245 100644
--- a/clang/test/Driver/sparc-fix.c
+++ b/clang/test/Driver/sparc-fix.c
@@ -1,12 +1,5 @@
-// RUN: %clang --target=sp
[clang] [Sparc] Add flags to enable errata workaround pass for GR712RC and UT700 (PR #104742)
doac wrote: Our UT700 and GR712RC processors are in active production and we have customers that for various reasons wants to use clang instead of gcc. To do that they need to use these workarounds to avoid certain sensitive code sequences (the same workarounds are already available in gcc). We have also developed some performance related patches for the Sparc backend, but it has been difficult to get them upstreamed as, as you say, few people are working on the Sparc backend. So instead we have provided our customers with custom versions of clang/llvm for the different operating systems that we support. In my experience these workarounds have been very easy to port forward, but the downside of not having them in mainline is that they are not included in 3:rd party tools that uses llvm nor in different operating system vendors custom toolchains. https://github.com/llvm/llvm-project/pull/104742 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Sparc] Add flags to enable errata workaround pass for GR712RC and UT700 (PR #104742)
doac wrote: > > We have also developed some performance related patches for the Sparc > > backend, but it has been difficult to get them upstreamed as, as you say, > > few people are working on the Sparc backend. > > This is off-topic but is it possible for you to submit it (or if I can see > those)? I'd like to get them upstreamed, if possible~ Yes, we can definitively try to submit them. We are working on porting them to the latest main, but you can see the 8.0.0 version here: https://github.com/doac/llvm-project/tree/bcc-2.1-llvm-8.0.0 Some of them have already been upstreamed or fixed by others, and others, such as the ones marked by REX, might not be that interesting for you. https://github.com/llvm/llvm-project/pull/104742 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Sparc] Add flags to enable errata workaround pass for GR712RC and UT700 (PR #104742)
https://github.com/doac closed https://github.com/llvm/llvm-project/pull/104742 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
