[PATCH] D25012: [x86][inline-asm] Add support for curly brackets escape using "%" in extended inline asm.

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mharoush created this revision.
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This patch is a compatibility fix for clang, matching GCC support for charter 
escape when using extended in-line assembly (i.e, "%{" ,"%}" --> "{" ,"}" ).
It is meant to enable support for advanced features such as AVX512 
conditional\masked vector instructions/broadcast assembly syntax.

Note: This related test is dependent on the review on 
https://reviews.llvm.org/D25011

Repository:
  rL LLVM

https://reviews.llvm.org/D25012

Files:
  lib/AST/Stmt.cpp
  test/CodeGen/x86_inlineasm_curly_bracket_escape.c

Index: lib/AST/Stmt.cpp
===
--- lib/AST/Stmt.cpp
+++ lib/AST/Stmt.cpp
@@ -533,15 +533,17 @@
   DiagOffs = CurPtr-StrStart-1;
   return diag::err_asm_invalid_escape;
 }
-
+// Handle escaped char and continue looping over the asm string.
 char EscapedChar = *CurPtr++;
-if (EscapedChar == '%') {  // %% -> %
-  // Escaped percentage sign.
-  CurStringPiece += '%';
+switch (EscapedChar) {
+default:
+  break;
+case '%': // %% -> %
+case '{': // %{ -> {
+case '}': // %} -> }
+  CurStringPiece += EscapedChar;
   continue;
-}
-
-if (EscapedChar == '=') {  // %= -> Generate an unique ID.
+case '=': // %= -> Generate a unique ID.
   CurStringPiece += "${:uid}";
   continue;
 }
Index: test/CodeGen/x86_inlineasm_curly_bracket_escape.c
===
--- test/CodeGen/x86_inlineasm_curly_bracket_escape.c
+++ test/CodeGen/x86_inlineasm_curly_bracket_escape.c
@@ -0,0 +1,10 @@
+// RUN: %clang_cc1 %s -target-cpu skylake-avx512 -O0  -S -o - -Wall -Werror | 
FileCheck %s
+// This test checks validity of inline assembly using curly brackets syntax
+// for extended inline asm.
+
+void test_curly_brackets(){
+//CHECK: #APP
+//CHECK: vpaddb %xmm1, %xmm0, %xmm1 {%k1} {z}
+//CHECK: #NO_APP
+  asm ("vpaddb\t %%xmm1,%%xmm0,%%xmm1 %{%%k1%}%{z%}\t":::);
+}


Index: lib/AST/Stmt.cpp
===
--- lib/AST/Stmt.cpp
+++ lib/AST/Stmt.cpp
@@ -533,15 +533,17 @@
   DiagOffs = CurPtr-StrStart-1;
   return diag::err_asm_invalid_escape;
 }
-
+// Handle escaped char and continue looping over the asm string.
 char EscapedChar = *CurPtr++;
-if (EscapedChar == '%') {  // %% -> %
-  // Escaped percentage sign.
-  CurStringPiece += '%';
+switch (EscapedChar) {
+default:
+  break;
+case '%': // %% -> %
+case '{': // %{ -> {
+case '}': // %} -> }
+  CurStringPiece += EscapedChar;
   continue;
-}
-
-if (EscapedChar == '=') {  // %= -> Generate an unique ID.
+case '=': // %= -> Generate a unique ID.
   CurStringPiece += "${:uid}";
   continue;
 }
Index: test/CodeGen/x86_inlineasm_curly_bracket_escape.c
===
--- test/CodeGen/x86_inlineasm_curly_bracket_escape.c
+++ test/CodeGen/x86_inlineasm_curly_bracket_escape.c
@@ -0,0 +1,10 @@
+// RUN: %clang_cc1 %s -target-cpu skylake-avx512 -O0  -S -o - -Wall -Werror | FileCheck %s
+// This test checks validity of inline assembly using curly brackets syntax
+// for extended inline asm.
+
+void test_curly_brackets(){
+//CHECK: #APP
+//CHECK: vpaddb %xmm1, %xmm0, %xmm1 {%k1} {z}
+//CHECK: #NO_APP
+  asm ("vpaddb\t %%xmm1,%%xmm0,%%xmm1 %{%%k1%}%{z%}\t":::);
+}
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[PATCH] D25011: [x86][inline-asm] Introducing (AVX512) k0-k7 registers for inline-asm usage

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mharoush created this revision.
mharoush added reviewers: delena, myatsina, rnk, echristo.
mharoush added a subscriber: cfe-commits.
mharoush set the repository for this revision to rL LLVM.
Herald added a subscriber: mehdi_amini.

This patch enables usage of k registers in inline assembly syntax.

Repository:
  rL LLVM

https://reviews.llvm.org/D25011

Files:
  lib/Basic/Targets.cpp
  test/CodeGen/avx512-inline-asm-kregisters-basics.c

Index: lib/Basic/Targets.cpp
===
--- lib/Basic/Targets.cpp
+++ lib/Basic/Targets.cpp
@@ -2346,6 +2346,7 @@
   "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15",
   "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23",
   "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31",
+  "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7",
 };
 
 const TargetInfo::AddlRegName AddlRegNames[] = {
Index: test/CodeGen/avx512-inline-asm-kregisters-basics.c
===
--- test/CodeGen/avx512-inline-asm-kregisters-basics.c
+++ test/CodeGen/avx512-inline-asm-kregisters-basics.c
@@ -0,0 +1,17 @@
+// RUN: %clang_cc1 %s -target-cpu skylake-avx512 -O0  -S -o - -Wall -Werror | 
FileCheck %s
+// This test checks basic inline assembly recognition of k0-k7 registers for 
avx512.
+
+void test_basic_inline_asm_with_k_regs() {
+//CHECK: #APP
+//CHECK: kandw %k1, %k2, %k3
+//CHECK: #NO_APP
+asm("kandw %k1, %k2, %k3\t");
+//CHECK: #APP
+//CHECK: kandw %k4, %k5, %k6
+//CHECK: #NO_APP
+asm("kandw %k4, %k5, %k6\t");
+//CHECK: #APP
+//CHECK: kandw %k7, %k0, %k1
+//CHECK: #NO_APP
+asm("kandw %k7, %k0, %k1\t");
+}
\ No newline at end of file


Index: lib/Basic/Targets.cpp
===
--- lib/Basic/Targets.cpp
+++ lib/Basic/Targets.cpp
@@ -2346,6 +2346,7 @@
   "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15",
   "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23",
   "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31",
+  "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7",
 };
 
 const TargetInfo::AddlRegName AddlRegNames[] = {
Index: test/CodeGen/avx512-inline-asm-kregisters-basics.c
===
--- test/CodeGen/avx512-inline-asm-kregisters-basics.c
+++ test/CodeGen/avx512-inline-asm-kregisters-basics.c
@@ -0,0 +1,17 @@
+// RUN: %clang_cc1 %s -target-cpu skylake-avx512 -O0  -S -o - -Wall -Werror | FileCheck %s
+// This test checks basic inline assembly recognition of k0-k7 registers for avx512.
+
+void test_basic_inline_asm_with_k_regs() {
+//CHECK: #APP
+//CHECK: kandw %k1, %k2, %k3
+//CHECK: #NO_APP
+asm("kandw %k1, %k2, %k3\t");
+//CHECK: #APP
+//CHECK: kandw %k4, %k5, %k6
+//CHECK: #NO_APP
+asm("kandw %k4, %k5, %k6\t");
+//CHECK: #APP
+//CHECK: kandw %k7, %k0, %k1
+//CHECK: #NO_APP
+asm("kandw %k7, %k0, %k1\t");
+}
\ No newline at end of file
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[PATCH] D25012: [x86][inline-asm] Add support for curly brackets escape using "%" in extended inline asm.

[Matan via cfe-commits]

mharoush updated this revision to Diff 73602.

Repository:
  rL LLVM

https://reviews.llvm.org/D25012

Files:
  lib/AST/Stmt.cpp
  test/CodeGen/x86_inlineasm_curly_bracket_escape.c


Index: lib/AST/Stmt.cpp
===
--- lib/AST/Stmt.cpp
+++ lib/AST/Stmt.cpp
@@ -533,15 +533,17 @@
   DiagOffs = CurPtr-StrStart-1;
   return diag::err_asm_invalid_escape;
 }
-
+// Handle escaped char and continue looping over the asm string.
 char EscapedChar = *CurPtr++;
-if (EscapedChar == '%') {  // %% -> %
-  // Escaped percentage sign.
-  CurStringPiece += '%';
+switch (EscapedChar) {
+default:
+  break;
+case '%': // %% -> %
+case '{': // %{ -> {
+case '}': // %} -> }
+  CurStringPiece += EscapedChar;
   continue;
-}
-
-if (EscapedChar == '=') {  // %= -> Generate an unique ID.
+case '=': // %= -> Generate a unique ID.
   CurStringPiece += "${:uid}";
   continue;
 }
Index: test/CodeGen/x86_inlineasm_curly_bracket_escape.c
===
--- test/CodeGen/x86_inlineasm_curly_bracket_escape.c
+++ test/CodeGen/x86_inlineasm_curly_bracket_escape.c
@@ -0,0 +1,8 @@
+// RUN: %clang_cc1 %s -target-cpu skylake-avx512 -O0  -S -emit-llvm -o - -Wall 
-Werror | FileCheck %s
+// This test checks validity of inline assembly using curly brackets syntax
+// for extended inline asm.
+
+void test_curly_brackets() {
+//CHECK:  %xmm1,%xmm0,%xmm1 {%k1}{z}
+asm("vpaddb\t %%xmm1,%%xmm0,%%xmm1 %{%%k1%}%{z%}\t":::);
+}
\ No newline at end of file


Index: lib/AST/Stmt.cpp
===
--- lib/AST/Stmt.cpp
+++ lib/AST/Stmt.cpp
@@ -533,15 +533,17 @@
   DiagOffs = CurPtr-StrStart-1;
   return diag::err_asm_invalid_escape;
 }
-
+// Handle escaped char and continue looping over the asm string.
 char EscapedChar = *CurPtr++;
-if (EscapedChar == '%') {  // %% -> %
-  // Escaped percentage sign.
-  CurStringPiece += '%';
+switch (EscapedChar) {
+default:
+  break;
+case '%': // %% -> %
+case '{': // %{ -> {
+case '}': // %} -> }
+  CurStringPiece += EscapedChar;
   continue;
-}
-
-if (EscapedChar == '=') {  // %= -> Generate an unique ID.
+case '=': // %= -> Generate a unique ID.
   CurStringPiece += "${:uid}";
   continue;
 }
Index: test/CodeGen/x86_inlineasm_curly_bracket_escape.c
===
--- test/CodeGen/x86_inlineasm_curly_bracket_escape.c
+++ test/CodeGen/x86_inlineasm_curly_bracket_escape.c
@@ -0,0 +1,8 @@
+// RUN: %clang_cc1 %s -target-cpu skylake-avx512 -O0  -S -emit-llvm -o - -Wall -Werror | FileCheck %s
+// This test checks validity of inline assembly using curly brackets syntax
+// for extended inline asm.
+
+void test_curly_brackets() {
+//CHECK:  %xmm1,%xmm0,%xmm1 {%k1}{z}
+asm("vpaddb\t %%xmm1,%%xmm0,%%xmm1 %{%%k1%}%{z%}\t":::);
+}
\ No newline at end of file
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[PATCH] D25011: [x86][inline-asm] Introducing (AVX512) k0-k7 registers for inline-asm usage

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mharoush added a comment.

This patch is a part of a larger support for k constraints, its main purpose is 
to add the option to choose the specific kN register while using basic inline 
assembly, the constraint support for extended inline assembly is being 
supported by another patch D25062    D25063 



Repository:
  rL LLVM

https://reviews.llvm.org/D25011



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[PATCH] D25012: [x86][inline-asm] Add support for curly brackets escape using "%" in extended inline asm.

[Matan via cfe-commits]

mharoush marked an inline comment as done.
mharoush added a comment.

Done


Repository:
  rL LLVM

https://reviews.llvm.org/D25012



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[PATCH] D25062: [x86][inline-asm][AVX512][llvm][PART-2] Introducing "k" and "Yk" constraints for extended inline assembly, enabling use of AVX512 masked vectorized instructions.

[Matan via cfe-commits]

mharoush updated this revision to Diff 74986.
mharoush added a comment.
Herald added a subscriber: mehdi_amini.

fixed Reids comments


Repository:
  rL LLVM

https://reviews.llvm.org/D25062

Files:
  lib/Target/X86/X86ISelLowering.cpp

Index: lib/Target/X86/X86ISelLowering.cpp
===
--- lib/Target/X86/X86ISelLowering.cpp
+++ lib/Target/X86/X86ISelLowering.cpp
@@ -32225,6 +32225,7 @@
 case 'Y':
 case 'l':
   return C_RegisterClass;
+case 'k': // AVX512 masking registers.
 case 'a':
 case 'b':
 case 'c':
@@ -32248,6 +32249,19 @@
   break;
 }
   }
+  else if (Constraint.size() == 2) {
+switch (Constraint[0]) {
+default:
+  break;
+case 'Y':
+  switch (Constraint[1]) {
+  default:
+break;
+  case 'k':
+return C_Register;
+  }
+}
+  }
   return TargetLowering::getConstraintType(Constraint);
 }
 
@@ -32291,16 +32305,27 @@
 if (type->isX86_MMXTy() && Subtarget.hasMMX())
   weight = CW_SpecificReg;
 break;
+  case 'Y':
+// Other "Y" (e.g. "Yk") constraints should be implemented below.
+if (constraint[1] == 'k') {
+  // Support for 'Yk' (similarly to the 'k' variant below).
+  weight = CW_SpecificReg;
+  break;
+}
+  // Else fall through (handle "Y" constraint).
   case 'v':
 if ((type->getPrimitiveSizeInBits() == 512) && Subtarget.hasAVX512())
   weight = CW_Register;
 LLVM_FALLTHROUGH;
   case 'x':
-  case 'Y':
 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget.hasSSE1()) ||
 ((type->getPrimitiveSizeInBits() == 256) && Subtarget.hasFp256()))
   weight = CW_Register;
 break;
+  case 'k':
+// Enable conditional vector operations using %k<#> registers.
+weight = CW_SpecificReg;
+break;
   case 'I':
 if (ConstantInt *C = dyn_cast(info.CallOperandVal)) {
   if (C->getZExtValue() <= 31)
@@ -32577,6 +32602,23 @@
   // TODO: Slight differences here in allocation order and leaving
   // RIP in the class. Do they matter any more here than they do
   // in the normal allocation?
+case 'k':
+  if (Subtarget.hasAVX512()) {
+//  Only supported in AVX512 or later.
+  switch (VT.SimpleTy) {
+  case MVT::i32:
+return std::make_pair(0U, &X86::VK32RegClass);
+  case MVT::i16:
+return std::make_pair(0U, &X86::VK16RegClass);
+  case MVT::i8:
+return std::make_pair(0U, &X86::VK8RegClass);
+  case MVT::i1:
+return std::make_pair(0U, &X86::VK1RegClass);
+  case MVT::i64:
+return std::make_pair(0U, &X86::VK64RegClass);
+  }
+  }
+  break;
 case 'q':   // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
   if (Subtarget.is64Bit()) {
 if (VT == MVT::i32 || VT == MVT::f32)
@@ -32678,6 +32720,28 @@
   }
   break;
 }
+  } else if (Constraint.size() == 2 && Constraint[0] == 'Y') {
+switch (Constraint[1]) {
+default:
+  break;
+case 'k':
+  // This register class doesn't allocate k0 for masked vector operation.
+  if (Subtarget.hasAVX512()) { // Only supported in AVX512.
+  switch (VT.SimpleTy) {
+  case MVT::i32:
+  return std::make_pair(0U, &X86::VK32WMRegClass);
+  case MVT::i16:
+  return std::make_pair(0U, &X86::VK16WMRegClass);
+  case MVT::i8:
+  return std::make_pair(0U, &X86::VK8WMRegClass);
+  case MVT::i1:
+  return std::make_pair(0U, &X86::VK1WMRegClass);
+  case MVT::i64:
+  return std::make_pair(0U, &X86::VK64WMRegClass);
+  } 
+  }
+  break;
+}
   }
 
   // Use the default implementation in TargetLowering to convert the register
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[PATCH] D25062: [x86][inline-asm][AVX512][llvm][PART-2] Introducing "k" and "Yk" constraints for extended inline assembly, enabling use of AVX512 masked vectorized instructions.

[Matan via cfe-commits]

mharoush updated this revision to Diff 75005.
mharoush added a comment.

Added default case, minor ws style.


Repository:
  rL LLVM

https://reviews.llvm.org/D25062

Files:
  lib/Target/X86/X86ISelLowering.cpp

Index: lib/Target/X86/X86ISelLowering.cpp
===
--- lib/Target/X86/X86ISelLowering.cpp
+++ lib/Target/X86/X86ISelLowering.cpp
@@ -32225,6 +32225,7 @@
 case 'Y':
 case 'l':
   return C_RegisterClass;
+case 'k': // AVX512 masking registers.
 case 'a':
 case 'b':
 case 'c':
@@ -32248,6 +32249,19 @@
   break;
 }
   }
+  else if (Constraint.size() == 2) {
+switch (Constraint[0]) {
+default:
+  break;
+case 'Y':
+  switch (Constraint[1]) {
+  default:
+break;
+  case 'k':
+return C_Register;
+  }
+}
+  }
   return TargetLowering::getConstraintType(Constraint);
 }
 
@@ -32291,16 +32305,27 @@
 if (type->isX86_MMXTy() && Subtarget.hasMMX())
   weight = CW_SpecificReg;
 break;
+  case 'Y':
+// Other "Y" (e.g. "Yk") constraints should be implemented below.
+if (constraint[1] == 'k') {
+  // Support for 'Yk' (similarly to the 'k' variant below).
+  weight = CW_SpecificReg;
+  break;
+}
+  // Else fall through (handle "Y" constraint).
   case 'v':
 if ((type->getPrimitiveSizeInBits() == 512) && Subtarget.hasAVX512())
   weight = CW_Register;
 LLVM_FALLTHROUGH;
   case 'x':
-  case 'Y':
 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget.hasSSE1()) ||
 ((type->getPrimitiveSizeInBits() == 256) && Subtarget.hasFp256()))
   weight = CW_Register;
 break;
+  case 'k':
+// Enable conditional vector operations using %k<#> registers.
+weight = CW_SpecificReg;
+break;
   case 'I':
 if (ConstantInt *C = dyn_cast(info.CallOperandVal)) {
   if (C->getZExtValue() <= 31)
@@ -32577,6 +32602,24 @@
   // TODO: Slight differences here in allocation order and leaving
   // RIP in the class. Do they matter any more here than they do
   // in the normal allocation?
+case 'k':
+  if (Subtarget.hasAVX512()) {
+//  Only supported in AVX512 or later.
+switch (VT.SimpleTy) {
+default: break;
+case MVT::i32:
+  return std::make_pair(0U, &X86::VK32RegClass);
+case MVT::i16:
+  return std::make_pair(0U, &X86::VK16RegClass);
+case MVT::i8:
+  return std::make_pair(0U, &X86::VK8RegClass);
+case MVT::i1:
+  return std::make_pair(0U, &X86::VK1RegClass);
+case MVT::i64:
+  return std::make_pair(0U, &X86::VK64RegClass);
+}
+  }
+  break;
 case 'q':   // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
   if (Subtarget.is64Bit()) {
 if (VT == MVT::i32 || VT == MVT::f32)
@@ -32678,6 +32721,29 @@
   }
   break;
 }
+  } else if (Constraint.size() == 2 && Constraint[0] == 'Y') {
+switch (Constraint[1]) {
+default:
+  break;
+case 'k':
+  // This register class doesn't allocate k0 for masked vector operation.
+  if (Subtarget.hasAVX512()) { // Only supported in AVX512.
+switch (VT.SimpleTy) {
+default: break;
+case MVT::i32:
+return std::make_pair(0U, &X86::VK32WMRegClass);
+case MVT::i16:
+return std::make_pair(0U, &X86::VK16WMRegClass);
+case MVT::i8:
+return std::make_pair(0U, &X86::VK8WMRegClass);
+case MVT::i1:
+return std::make_pair(0U, &X86::VK1WMRegClass);
+case MVT::i64:
+return std::make_pair(0U, &X86::VK64WMRegClass);
+} 
+  }
+  break;
+}
   }
 
   // Use the default implementation in TargetLowering to convert the register
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[PATCH] D25012: [x86][inline-asm] Add support for curly brackets escape using "%" in extended inline asm.

[Matan via cfe-commits]

mharoush added a comment.

Done


Repository:
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https://reviews.llvm.org/D25012



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[PATCH] D25063: [x86][inline-asm][AVX512][clang][PART-1] Introducing "k" and "Yk" constraints for extended inline assembly, enabling use of AVX512 masked vectorized instructions.

[Matan via cfe-commits]

mharoush removed rL LLVM as the repository for this revision.
mharoush updated this revision to Diff 75277.
mharoush added a comment.
Herald added a subscriber: mehdi_amini.

I renamed the test file to be more informative, added LLVM_FALLTHROUGH, removed 
check of {z} and changed the test to check LLVM IR.


https://reviews.llvm.org/D25063

Files:
  lib/Basic/Targets.cpp
  test/CodeGen/avx512-kconstraints-att_inline_asm.c

Index: lib/Basic/Targets.cpp
===
--- lib/Basic/Targets.cpp
+++ lib/Basic/Targets.cpp
@@ -3987,6 +3987,7 @@
 case 't': // Any SSE register, when SSE2 is enabled.
 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
 case 'm': // Any MMX register, when inter-unit moves enabled.
+case 'k': // AVX512 arch mask registers: k1-k7.
   Info.setAllowsRegister();
   return true;
 }
@@ -4008,6 +4009,8 @@
   case 'q': // Any register accessible as [r]l: a, b, c, and d.
   case 'y': // Any MMX register.
   case 'x': // Any SSE register.
+  case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0
+// for intermideate k reg operations).
   case 'Q': // Any register accessible as [r]h: a, b, c, and d.
   case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
   case 'l': // "Index" registers: any general register that can be used as an
@@ -4041,6 +4044,8 @@
 unsigned Size) const {
   switch (Constraint[0]) {
   default: break;
+  case 'k':
+  // Registers k0-k7 (AVX512) size limit is 64 bit.
   case 'y':
 return Size <= 64;
   case 'f':
@@ -4061,6 +4066,7 @@
 default: break;
 case 'm':
   // 'Ym' is synonymous with 'y'.
+case 'k':
   return Size <= 64;
 case 'i':
 case 't':
@@ -4092,6 +4098,20 @@
 return std::string("{st}");
   case 'u': // second from top of floating point stack.
 return std::string("{st(1)}"); // second from top of floating point stack.
+  case 'Y':
+switch (Constraint[1]) {
+default:
+  // Break from inner switch and fall through (copy single char),
+  // continue parsing after copying the current constraint into 
+  // the return string.
+  break;
+case 'k':
+  // "^" hints llvm that this is a 2 letter constraint.
+  // "Constraint++" is used to promote the string iterator 
+  // to the next constraint.
+  return std::string("^") + std::string(Constraint++, 2);
+} 
+LLVM_FALLTHROUGH;
   default:
 return std::string(1, *Constraint);
   }
Index: test/CodeGen/avx512-kconstraints-att_inline_asm.c
===
--- test/CodeGen/avx512-kconstraints-att_inline_asm.c
+++ test/CodeGen/avx512-kconstraints-att_inline_asm.c
@@ -0,0 +1,75 @@
+// RUN: %clang_cc1 %s -target-cpu skylake-avx512 -O0  -emit-llvm -S -o - -Wall -Werror | FileCheck %s
+// This test checks validity of att\gcc style inline assmebly for avx512 k and Yk constraints.
+// Also checks mask register allows flexible type (size <= 64 bit)
+
+void mask_Yk_i8(char msk){ 
+//CHECK: #APP 
+//CHECK: vpaddb %xmm1, %xmm0, %xmm1 {%k1}
+//CHECK: #NO_APP 
+	asm ("vpaddb\t %%xmm1, %%xmm0, %%xmm1 %{%0%}\t"
+   ://output
+   : "Yk" (msk));   //inputs
+}
+
+void mask_Yk_i16(short msk){
+//CHECK: #APP
+//CHECK: vpaddb %xmm1, %xmm0, %xmm1 {%k1}
+//CHECK: #NO_APP
+	asm ("vpaddb\t %%xmm1, %%xmm0, %%xmm1 %{%0%}\t"
+   ://output
+   :  "Yk" (msk));  //inputs
+}
+
+void mask_Yk_i32(int msk){
+//CHECK: #APP
+//CHECK: vpaddb %xmm1, %xmm0, %xmm1 {%k1}
+//CHECK: #NO_APP
+asm ("vpaddb\t %%xmm1, %%xmm0, %%xmm1 %{%0%}\t"
+   ://output
+   :  "Yk" (msk)); 	//inputs
+}
+
+void mask_Yk_i64(long long msk){
+//CHECK: #APP 
+//CHECK: vpaddb %xmm1, %xmm0, %xmm1 {%k1}
+//CHECK: #NO_APP 
+	asm ("vpaddb\t %%xmm1, %%xmm0, %%xmm1 %{%0%}\t"
+   ://output
+   :  "Yk" (msk)); 	//inputs
+}
+
+void k_wise_op_i8(char msk_dst,char msk_src1,char msk_src2){
+//CHECK: #APP
+//CHECK: kandw %k1, %k0, %k0
+//CHECK: #NO_APP 
+ asm ("kandw\t%2, %1, %0"
+   : "=k" (msk_dst)
+   : "k" (msk_src1), "k" (msk_src2));
+}
+
+void k_wise_op_i16(short msk_dst, short msk_src1, short msk_src2){
+//CHECK: #APP
+//CHECK: kandw %k1, %k0, %k0
+//CHECK: #NO_APP 
+  asm ("kandw\t%2, %1, %0"
+   : "=k" (msk_dst)
+   : "k" (msk_src1), "k" (msk_src2));
+}
+
+void k_wise_op_i32(int msk_dst, int msk_src1, int msk_src2){
+//CHECK: #APP
+//CHECK: kandw %k1, %k0, %k0
+//CHECK: #NO_APP 
+  asm ("kandw\t%2, %1, %0"
+   : "=k" (msk_dst)
+   : "k" (msk_src1), "k" (msk_src2));
+}
+
+void k_wise_op_i64(long long msk_dst, long long msk_src1, long long msk_src2){
+//CHECK: #APP
+//CHECK: kandw %k1, %k0, %k0
+//CHECK: #NO_APP 
+  asm ("kandw\t%2, %1, %0"
+   : "=k" (msk_dst)
+   : "k" (msk_src1), "k" (msk_src2));
+}
\ No newline at end of file
__

[PATCH] D25062: [x86][inline-asm][AVX512][llvm][PART-2] Introducing "k" and "Yk" constraints for extended inline assembly, enabling use of AVX512 masked vectorized instructions.

[Matan via cfe-commits]

mharoush removed rL LLVM as the repository for this revision.
mharoush updated this revision to Diff 75278.
mharoush added a comment.

Added LLVM_FALLTHROUGH


https://reviews.llvm.org/D25062

Files:
  lib/Target/X86/X86ISelLowering.cpp

Index: lib/Target/X86/X86ISelLowering.cpp
===
--- lib/Target/X86/X86ISelLowering.cpp
+++ lib/Target/X86/X86ISelLowering.cpp
@@ -32225,6 +32225,7 @@
 case 'Y':
 case 'l':
   return C_RegisterClass;
+case 'k': // AVX512 masking registers.
 case 'a':
 case 'b':
 case 'c':
@@ -32248,6 +32249,19 @@
   break;
 }
   }
+  else if (Constraint.size() == 2) {
+switch (Constraint[0]) {
+default:
+  break;
+case 'Y':
+  switch (Constraint[1]) {
+  default:
+break;
+  case 'k':
+return C_Register;
+  }
+}
+  }
   return TargetLowering::getConstraintType(Constraint);
 }
 
@@ -32291,16 +32305,28 @@
 if (type->isX86_MMXTy() && Subtarget.hasMMX())
   weight = CW_SpecificReg;
 break;
+  case 'Y':
+// Other "Y" (e.g. "Yk") constraints should be implemented below.
+if (constraint[1] == 'k') {
+  // Support for 'Yk' (similarly to the 'k' variant below).
+  weight = CW_SpecificReg;
+  break;
+}
+  // Else fall through (handle "Y" constraint).
+LLVM_FALLTHROUGH;
   case 'v':
 if ((type->getPrimitiveSizeInBits() == 512) && Subtarget.hasAVX512())
   weight = CW_Register;
 LLVM_FALLTHROUGH;
   case 'x':
-  case 'Y':
 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget.hasSSE1()) ||
 ((type->getPrimitiveSizeInBits() == 256) && Subtarget.hasFp256()))
   weight = CW_Register;
 break;
+  case 'k':
+// Enable conditional vector operations using %k<#> registers.
+weight = CW_SpecificReg;
+break;
   case 'I':
 if (ConstantInt *C = dyn_cast(info.CallOperandVal)) {
   if (C->getZExtValue() <= 31)
@@ -32577,6 +32603,24 @@
   // TODO: Slight differences here in allocation order and leaving
   // RIP in the class. Do they matter any more here than they do
   // in the normal allocation?
+case 'k':
+  if (Subtarget.hasAVX512()) {
+//  Only supported in AVX512 or later.
+switch (VT.SimpleTy) {
+default: break;
+case MVT::i32:
+  return std::make_pair(0U, &X86::VK32RegClass);
+case MVT::i16:
+  return std::make_pair(0U, &X86::VK16RegClass);
+case MVT::i8:
+  return std::make_pair(0U, &X86::VK8RegClass);
+case MVT::i1:
+  return std::make_pair(0U, &X86::VK1RegClass);
+case MVT::i64:
+  return std::make_pair(0U, &X86::VK64RegClass);
+}
+  }
+  break;
 case 'q':   // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
   if (Subtarget.is64Bit()) {
 if (VT == MVT::i32 || VT == MVT::f32)
@@ -32678,6 +32722,29 @@
   }
   break;
 }
+  } else if (Constraint.size() == 2 && Constraint[0] == 'Y') {
+switch (Constraint[1]) {
+default:
+  break;
+case 'k':
+  // This register class doesn't allocate k0 for masked vector operation.
+  if (Subtarget.hasAVX512()) { // Only supported in AVX512.
+switch (VT.SimpleTy) {
+default: break;
+case MVT::i32:
+  return std::make_pair(0U, &X86::VK32WMRegClass);
+case MVT::i16:
+  return std::make_pair(0U, &X86::VK16WMRegClass);
+case MVT::i8:
+  return std::make_pair(0U, &X86::VK8WMRegClass);
+case MVT::i1:
+  return std::make_pair(0U, &X86::VK1WMRegClass);
+case MVT::i64:
+  return std::make_pair(0U, &X86::VK64WMRegClass);
+} 
+  }
+  break;
+}
   }
 
   // Use the default implementation in TargetLowering to convert the register
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[PATCH] D25011: [x86][inline-asm] Introducing (AVX512) k0-k7 registers for inline-asm usage

[Matan via cfe-commits]

mharoush added a comment.

ping


Repository:
  rL LLVM

https://reviews.llvm.org/D25011



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[PATCH] D25063: [x86][inline-asm][AVX512][clang][PART-1] Introducing "k" and "Yk" constraints for extended inline assembly, enabling use of AVX512 masked vectorized instructions.

[Matan via cfe-commits]

mharoush set the repository for this revision to rL LLVM.
mharoush updated this revision to Diff 75542.
mharoush added a comment.

Only test affected(correct version this time: checking LLVM IR instead of x86 
asm), 
This test depends on D25012  being applied.


Repository:
  rL LLVM

https://reviews.llvm.org/D25063

Files:
  lib/Basic/Targets.cpp
  test/CodeGen/avx512-kconstraints-att_inline_asm.c

Index: lib/Basic/Targets.cpp
===
--- lib/Basic/Targets.cpp
+++ lib/Basic/Targets.cpp
@@ -3987,6 +3987,7 @@
 case 't': // Any SSE register, when SSE2 is enabled.
 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
 case 'm': // Any MMX register, when inter-unit moves enabled.
+case 'k': // AVX512 arch mask registers: k1-k7.
   Info.setAllowsRegister();
   return true;
 }
@@ -4008,6 +4009,8 @@
   case 'q': // Any register accessible as [r]l: a, b, c, and d.
   case 'y': // Any MMX register.
   case 'x': // Any SSE register.
+  case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0
+// for intermideate k reg operations).
   case 'Q': // Any register accessible as [r]h: a, b, c, and d.
   case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
   case 'l': // "Index" registers: any general register that can be used as an
@@ -4041,6 +4044,8 @@
 unsigned Size) const {
   switch (Constraint[0]) {
   default: break;
+  case 'k':
+  // Registers k0-k7 (AVX512) size limit is 64 bit.
   case 'y':
 return Size <= 64;
   case 'f':
@@ -4061,6 +4066,7 @@
 default: break;
 case 'm':
   // 'Ym' is synonymous with 'y'.
+case 'k':
   return Size <= 64;
 case 'i':
 case 't':
@@ -4092,6 +4098,20 @@
 return std::string("{st}");
   case 'u': // second from top of floating point stack.
 return std::string("{st(1)}"); // second from top of floating point stack.
+  case 'Y':
+switch (Constraint[1]) {
+default:
+  // Break from inner switch and fall through (copy single char),
+  // continue parsing after copying the current constraint into 
+  // the return string.
+  break;
+case 'k':
+  // "^" hints llvm that this is a 2 letter constraint.
+  // "Constraint++" is used to promote the string iterator 
+  // to the next constraint.
+  return std::string("^") + std::string(Constraint++, 2);
+} 
+LLVM_FALLTHROUGH;
   default:
 return std::string(1, *Constraint);
   }
Index: test/CodeGen/avx512-kconstraints-att_inline_asm.c
===
--- test/CodeGen/avx512-kconstraints-att_inline_asm.c
+++ test/CodeGen/avx512-kconstraints-att_inline_asm.c
@@ -0,0 +1,59 @@
+// RUN: %clang_cc1 %s -target-cpu skylake-avx512 -O0  -emit-llvm -S -o - -Wall -Werror | FileCheck %s
+// This test checks validity of att\gcc style inline assmebly for avx512 k and Yk constraints.
+// Also checks mask register allows flexible type (size <= 64 bit)
+
+void mask_Yk_i8(char msk){ 
+//CHECK: vpaddb %xmm1, %xmm0, %xmm1 {%k1}
+	asm ("vpaddb\t %%xmm1, %%xmm0, %%xmm1 %{%0%}\t"
+   ://output
+   : "Yk" (msk));   //inputs
+}
+
+void mask_Yk_i16(short msk){
+//CHECK: vpaddb %xmm1, %xmm0, %xmm1 {%k1}
+	asm ("vpaddb\t %%xmm1, %%xmm0, %%xmm1 %{%0%}\t"
+   ://output
+   :  "Yk" (msk));  //inputs
+}
+
+void mask_Yk_i32(int msk){
+//CHECK: vpaddb %xmm1, %xmm0, %xmm1 {%k1}
+asm ("vpaddb\t %%xmm1, %%xmm0, %%xmm1 %{%0%}\t"
+   ://output
+   :  "Yk" (msk)); 	//inputs
+}
+
+void mask_Yk_i64(long long msk){
+//CHECK: vpaddb %xmm1, %xmm0, %xmm1 {%k1}
+	asm ("vpaddb\t %%xmm1, %%xmm0, %%xmm1 %{%0%}\t"
+   ://output
+   :  "Yk" (msk)); 	//inputs
+}
+
+void k_wise_op_i8(char msk_dst,char msk_src1,char msk_src2){
+//CHECK: kandw %k1, %k0, %k0
+ asm ("kandw\t%2, %1, %0"
+   : "=k" (msk_dst)
+   : "k" (msk_src1), "k" (msk_src2));
+}
+
+void k_wise_op_i16(short msk_dst, short msk_src1, short msk_src2){
+//CHECK: kandw %k1, %k0, %k0
+  asm ("kandw\t%2, %1, %0"
+   : "=k" (msk_dst)
+   : "k" (msk_src1), "k" (msk_src2));
+}
+
+void k_wise_op_i32(int msk_dst, int msk_src1, int msk_src2){
+//CHECK: kandw %k1, %k0, %k0
+  asm ("kandw\t%2, %1, %0"
+   : "=k" (msk_dst)
+   : "k" (msk_src1), "k" (msk_src2));
+}
+
+void k_wise_op_i64(long long msk_dst, long long msk_src1, long long msk_src2){
+//CHECK: kandw %k1, %k0, %k0
+  asm ("kandw\t%2, %1, %0"
+   : "=k" (msk_dst)
+   : "k" (msk_src1), "k" (msk_src2));
+}
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[PATCH] D25063: [x86][inline-asm][AVX512][clang][PART-1] Introducing "k" and "Yk" constraints for extended inline assembly, enabling use of AVX512 masked vectorized instructions.

[Matan via cfe-commits]

mharoush added inline comments.



Comment at: test/CodeGen/avx512-kconstraints-att_inline_asm.c:6
+void mask_Yk_i8(char msk){ 
+//CHECK: #APP 
+//CHECK: vpaddb %xmm1, %xmm0, %xmm1 {%k1}

rnk wrote:
> The LLVM IR won't have #APP markers in it. Does this test really pass?
Sorry I uploaded the wrong patch file.


Repository:
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https://reviews.llvm.org/D25063



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