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commit f664e2d3cbeabdf27ace346e22ec4a116eda0f1e Author: Jerzy Kasenberg <jerzy.kasenb...@codecoup.pl> AuthorDate: Wed May 6 08:56:06 2020 +0200 nucleo-l476rg: Fix PLL configuration PLL was configured to produce 64MHz clock, yet PLLM and PLLN produced fVCO = 16 / 1 * 24 = 384MHz which is outside allowed range (64-344). With this change: - PLLx values are specified according to specification - System clock is changed to 80MHz - Flash latency is updated to reflect this higher speed - MSI is configured to run at 48MHz (instead of 16) and can now be used directly as USB clock source. --- hw/bsp/nucleo-l476rg/syscfg.yml | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/bsp/nucleo-l476rg/syscfg.yml b/hw/bsp/nucleo-l476rg/syscfg.yml index de38f02..406ac42 100644 --- a/hw/bsp/nucleo-l476rg/syscfg.yml +++ b/hw/bsp/nucleo-l476rg/syscfg.yml @@ -34,20 +34,20 @@ syscfg.vals: STM32_CLOCK_LSE_BYPASS: 0 STM32_CLOCK_MSI: 1 STM32_CLOCK_MSI_CALIBRATION: 'RCC_MSICALIBRATION_DEFAULT' - STM32_CLOCK_MSI_CLOCK_RANGE: 'RCC_MSIRANGE_8' # 16MHz + STM32_CLOCK_MSI_CLOCK_RANGE: 'RCC_MSIRANGE_11' # 48MHz STM32_CLOCK_HSI: 0 STM32_CLOCK_HSI_CALIBRATION: 'RCC_HSICALIBRATION_DEFAULT' STM32_CLOCK_HSE: 0 STM32_CLOCK_HSE_BYPASS: 0 - STM32_CLOCK_PLL_PLLM: 1 # 16 / 1 = 16MHz - STM32_CLOCK_PLL_PLLN: 24 # 16 * 24 = 384MHz - STM32_CLOCK_PLL_PLLP: 7 # 384 / 7 = 54.85MHz - STM32_CLOCK_PLL_PLLR: 6 # 384 / 6 = 64MHz - STM32_CLOCK_PLL_PLLQ: 8 # 384 / 8 = 48MHz + STM32_CLOCK_PLL_PLLM: 6 # 48 / 6 = 8MHz + STM32_CLOCK_PLL_PLLN: 40 # 48 / 6 * 24 = 320MHz + STM32_CLOCK_PLL_PLLP: 7 # 320 / 7 = 45.71MHz + STM32_CLOCK_PLL_PLLR: 4 # 320 / 4 = 80MHz + STM32_CLOCK_PLL_PLLQ: 4 # 320 / 4 = 80MHz STM32_CLOCK_AHB_DIVIDER: 'RCC_SYSCLK_DIV1' STM32_CLOCK_APB1_DIVIDER: 'RCC_HCLK_DIV1' STM32_CLOCK_APB2_DIVIDER: 'RCC_HCLK_DIV1' - STM32_FLASH_LATENCY: 'FLASH_LATENCY_3' # max 64MHz + STM32_FLASH_LATENCY: 'FLASH_LATENCY_4' # max 80MHz STM32_FLASH_PREFETCH_ENABLE: 0 STM32_INSTRUCTION_CACHE_ENABLE: 1 STM32_DATA_CACHE_ENABLE: 1