[GitHub] mkiiskila commented on a change in pull request #329: Wi-Fire: Implement hal_timer
mkiiskila commented on a change in pull request #329: Wi-Fire: Implement
hal_timer
URL:
https://github.com/apache/incubator-mynewt-core/pull/329#discussion_r121724237
##
File path: hw/mcu/microchip/pic32mz2048efg100/src/hal_timer.c
##
@@ -0,0 +1,548 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include
+#include
+#include
+#include "hal/hal_timer.h"
+#include "mcu/mips_hal.h"
+
+#define PIC32MZ_TIMER_COUNT (8)
+#define PIC32MZ_PRESCALER_COUNT (8)
+
+#define TxCON(T)(base_address[T][0x0 / 0x4])
+#define TxCONCLR(T) (base_address[T][0x4 / 0x4])
+#define TxCONSET(T) (base_address[T][0x8 / 0x4])
+#define TMRx(T) (base_address[T][0x10 / 0x4])
+#define PRx(T) (base_address[T][0x20 / 0x4])
+
+static volatile uint32_t * base_address[PIC32MZ_TIMER_COUNT] = {
+(volatile uint32_t *)_TMR2_BASE_ADDRESS,
+(volatile uint32_t *)_TMR3_BASE_ADDRESS,
+(volatile uint32_t *)_TMR4_BASE_ADDRESS,
+(volatile uint32_t *)_TMR5_BASE_ADDRESS,
+(volatile uint32_t *)_TMR6_BASE_ADDRESS,
+(volatile uint32_t *)_TMR7_BASE_ADDRESS,
+(volatile uint32_t *)_TMR8_BASE_ADDRESS,
+(volatile uint32_t *)_TMR9_BASE_ADDRESS
+};
+
+static uint32_t timer_prescalers[PIC32MZ_PRESCALER_COUNT] =
+{1, 2, 4, 8, 16, 32, 64, 256};
+struct pic32_timer {
+uint32_t index;
+uint64_t interrupt_count;
+uint32_t interrupt_per_tick;
+uint64_t expiry; /* The unit is number of interrupts */
+TAILQ_HEAD(hal_timer_qhead, hal_timer) hal_timer_queue;
+};
+static struct pic32_timer timers[PIC32MZ_TIMER_COUNT];
+
+
+static inline uint32_t
+hal_timer_get_prescaler(int timer_num)
+{
+uint32_t index =
+(TxCON(timer_num) & _T2CON_TCKPS_MASK) >> _T2CON_TCKPS_POSITION;
+return timer_prescalers[index];
+}
+
+static inline uint32_t
+hal_timer_get_peripheral_base_clock(void)
+{
+return MYNEWT_VAL(CLOCK_FREQ) / ((PB3DIV & _PB3DIV_PBDIV_MASK) + 1);
+}
+
+static void
+hal_timer_enable_int(int timer_num)
+{
+switch (timer_num) {
+case 0:
+IPC2CLR = _IPC2_T2IP_MASK | _IPC2_T2IS_MASK;
+IPC2SET = 3 << _IPC2_T2IP_POSITION;
+IFS0CLR = _IFS0_T2IF_MASK;
+IEC0SET = _IEC0_T2IE_MASK;
+break;
+case 1:
+IPC3CLR = _IPC3_T3IP_MASK | _IPC3_T3IS_MASK;
+IPC3SET = 3 << _IPC3_T3IP_POSITION;
+IFS0CLR = _IFS0_T3IF_MASK;
+IEC0SET = _IEC0_T3IE_MASK;
+break;
+case 2:
+IPC4CLR = _IPC4_T4IP_MASK | _IPC4_T4IS_MASK;
+IPC4SET = 3 << _IPC4_T4IP_POSITION;
+IFS0CLR = _IFS0_T4IF_MASK;
+IEC0SET = _IEC0_T4IE_MASK;
+break;
+case 3:
+IPC6CLR = _IPC6_T5IP_MASK | _IPC6_T5IS_MASK;
+IPC6SET = 3 << _IPC6_T5IP_POSITION;
+IFS0CLR = _IFS0_T5IF_MASK;
+IEC0SET = _IEC0_T5IE_MASK;
+break;
+case 4:
+IPC7CLR = _IPC7_T6IP_MASK | _IPC7_T6IS_MASK;
+IPC7SET = 3 << _IPC7_T6IP_POSITION;
+IFS0CLR = _IFS0_T6IF_MASK;
+IEC0SET = _IEC0_T6IE_MASK;
+break;
+case 5:
+IPC8CLR = _IPC8_T7IP_MASK | _IPC8_T7IS_MASK;
+IPC8SET = 3 << _IPC8_T7IP_POSITION;
+IFS1CLR = _IFS1_T7IF_MASK;
+IEC1SET = _IEC1_T7IE_MASK;
+break;
+case 6:
+IPC9CLR = _IPC9_T8IP_MASK | _IPC9_T8IS_MASK;
+IPC9SET = 3 << _IPC9_T8IP_POSITION;
+IFS1CLR = _IFS1_T8IF_MASK;
+IEC1SET = _IEC1_T8IE_MASK;
+break;
+case 7:
+IPC10CLR = _IPC10_T9IP_MASK | _IPC10_T9IS_MASK;
+IPC10SET = 3 << _IPC10_T9IP_POSITION;
+IFS1CLR = _IFS1_T9IF_MASK;
+IEC1SET = _IEC1_T9IE_MASK;
+break;
+}
+}
+
+static void
+hal_timer_disable_int(int timer_num)
+{
+switch (timer_num) {
+case 0:
+IEC0CLR = _IEC0_T2IE_MASK;
+IFS0CLR = _IFS0_T2IF_MASK;
+break;
+case 1:
+IEC0CLR = _IEC0_T3IE_MASK;
+IFS0CLR = _IFS0_T3IF_MASK;
+break;
+case 2:
+IEC0CLR = _IEC0_T4IE_MASK;
+
[GitHub] mkiiskila commented on a change in pull request #329: Wi-Fire: Implement hal_timer
mkiiskila commented on a change in pull request #329: Wi-Fire: Implement
hal_timer
URL:
https://github.com/apache/incubator-mynewt-core/pull/329#discussion_r121561678
##
File path: hw/mcu/microchip/pic32mz2048efg100/src/hal_timer.c
##
@@ -0,0 +1,548 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include
+#include
+#include
+#include "hal/hal_timer.h"
+#include "mcu/mips_hal.h"
+
+#define PIC32MZ_TIMER_COUNT (8)
+#define PIC32MZ_PRESCALER_COUNT (8)
+
+#define TxCON(T)(base_address[T][0x0 / 0x4])
+#define TxCONCLR(T) (base_address[T][0x4 / 0x4])
+#define TxCONSET(T) (base_address[T][0x8 / 0x4])
+#define TMRx(T) (base_address[T][0x10 / 0x4])
+#define PRx(T) (base_address[T][0x20 / 0x4])
+
+static volatile uint32_t * base_address[PIC32MZ_TIMER_COUNT] = {
+(volatile uint32_t *)_TMR2_BASE_ADDRESS,
+(volatile uint32_t *)_TMR3_BASE_ADDRESS,
+(volatile uint32_t *)_TMR4_BASE_ADDRESS,
+(volatile uint32_t *)_TMR5_BASE_ADDRESS,
+(volatile uint32_t *)_TMR6_BASE_ADDRESS,
+(volatile uint32_t *)_TMR7_BASE_ADDRESS,
+(volatile uint32_t *)_TMR8_BASE_ADDRESS,
+(volatile uint32_t *)_TMR9_BASE_ADDRESS
+};
+
+static uint32_t timer_prescalers[PIC32MZ_PRESCALER_COUNT] =
+{1, 2, 4, 8, 16, 32, 64, 256};
+struct pic32_timer {
+uint32_t index;
+uint64_t interrupt_count;
+uint32_t interrupt_per_tick;
+uint64_t expiry; /* The unit is number of interrupts */
+TAILQ_HEAD(hal_timer_qhead, hal_timer) hal_timer_queue;
+};
+static struct pic32_timer timers[PIC32MZ_TIMER_COUNT];
+
+
+static inline uint32_t
+hal_timer_get_prescaler(int timer_num)
+{
+uint32_t index =
+(TxCON(timer_num) & _T2CON_TCKPS_MASK) >> _T2CON_TCKPS_POSITION;
+return timer_prescalers[index];
+}
+
+static inline uint32_t
+hal_timer_get_peripheral_base_clock(void)
+{
+return MYNEWT_VAL(CLOCK_FREQ) / ((PB3DIV & _PB3DIV_PBDIV_MASK) + 1);
+}
+
+static void
+hal_timer_enable_int(int timer_num)
+{
+switch (timer_num) {
+case 0:
+IPC2CLR = _IPC2_T2IP_MASK | _IPC2_T2IS_MASK;
+IPC2SET = 3 << _IPC2_T2IP_POSITION;
+IFS0CLR = _IFS0_T2IF_MASK;
+IEC0SET = _IEC0_T2IE_MASK;
+break;
+case 1:
+IPC3CLR = _IPC3_T3IP_MASK | _IPC3_T3IS_MASK;
+IPC3SET = 3 << _IPC3_T3IP_POSITION;
+IFS0CLR = _IFS0_T3IF_MASK;
+IEC0SET = _IEC0_T3IE_MASK;
+break;
+case 2:
+IPC4CLR = _IPC4_T4IP_MASK | _IPC4_T4IS_MASK;
+IPC4SET = 3 << _IPC4_T4IP_POSITION;
+IFS0CLR = _IFS0_T4IF_MASK;
+IEC0SET = _IEC0_T4IE_MASK;
+break;
+case 3:
+IPC6CLR = _IPC6_T5IP_MASK | _IPC6_T5IS_MASK;
+IPC6SET = 3 << _IPC6_T5IP_POSITION;
+IFS0CLR = _IFS0_T5IF_MASK;
+IEC0SET = _IEC0_T5IE_MASK;
+break;
+case 4:
+IPC7CLR = _IPC7_T6IP_MASK | _IPC7_T6IS_MASK;
+IPC7SET = 3 << _IPC7_T6IP_POSITION;
+IFS0CLR = _IFS0_T6IF_MASK;
+IEC0SET = _IEC0_T6IE_MASK;
+break;
+case 5:
+IPC8CLR = _IPC8_T7IP_MASK | _IPC8_T7IS_MASK;
+IPC8SET = 3 << _IPC8_T7IP_POSITION;
+IFS1CLR = _IFS1_T7IF_MASK;
+IEC1SET = _IEC1_T7IE_MASK;
+break;
+case 6:
+IPC9CLR = _IPC9_T8IP_MASK | _IPC9_T8IS_MASK;
+IPC9SET = 3 << _IPC9_T8IP_POSITION;
+IFS1CLR = _IFS1_T8IF_MASK;
+IEC1SET = _IEC1_T8IE_MASK;
+break;
+case 7:
+IPC10CLR = _IPC10_T9IP_MASK | _IPC10_T9IS_MASK;
+IPC10SET = 3 << _IPC10_T9IP_POSITION;
+IFS1CLR = _IFS1_T9IF_MASK;
+IEC1SET = _IEC1_T9IE_MASK;
+break;
+}
+}
+
+static void
+hal_timer_disable_int(int timer_num)
+{
+switch (timer_num) {
+case 0:
+IEC0CLR = _IEC0_T2IE_MASK;
+IFS0CLR = _IFS0_T2IF_MASK;
+break;
+case 1:
+IEC0CLR = _IEC0_T3IE_MASK;
+IFS0CLR = _IFS0_T3IF_MASK;
+break;
+case 2:
+IEC0CLR = _IEC0_T4IE_MASK;
+
[GitHub] mkiiskila commented on a change in pull request #329: Wi-Fire: Implement hal_timer
mkiiskila commented on a change in pull request #329: Wi-Fire: Implement
hal_timer
URL:
https://github.com/apache/incubator-mynewt-core/pull/329#discussion_r121563383
##
File path: hw/mcu/microchip/pic32mz2048efg100/src/hal_timer.c
##
@@ -0,0 +1,548 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include
+#include
+#include
+#include "hal/hal_timer.h"
+#include "mcu/mips_hal.h"
+
+#define PIC32MZ_TIMER_COUNT (8)
+#define PIC32MZ_PRESCALER_COUNT (8)
+
+#define TxCON(T)(base_address[T][0x0 / 0x4])
+#define TxCONCLR(T) (base_address[T][0x4 / 0x4])
+#define TxCONSET(T) (base_address[T][0x8 / 0x4])
+#define TMRx(T) (base_address[T][0x10 / 0x4])
+#define PRx(T) (base_address[T][0x20 / 0x4])
+
+static volatile uint32_t * base_address[PIC32MZ_TIMER_COUNT] = {
+(volatile uint32_t *)_TMR2_BASE_ADDRESS,
+(volatile uint32_t *)_TMR3_BASE_ADDRESS,
+(volatile uint32_t *)_TMR4_BASE_ADDRESS,
+(volatile uint32_t *)_TMR5_BASE_ADDRESS,
+(volatile uint32_t *)_TMR6_BASE_ADDRESS,
+(volatile uint32_t *)_TMR7_BASE_ADDRESS,
+(volatile uint32_t *)_TMR8_BASE_ADDRESS,
+(volatile uint32_t *)_TMR9_BASE_ADDRESS
+};
+
+static uint32_t timer_prescalers[PIC32MZ_PRESCALER_COUNT] =
+{1, 2, 4, 8, 16, 32, 64, 256};
+struct pic32_timer {
+uint32_t index;
+uint64_t interrupt_count;
+uint32_t interrupt_per_tick;
+uint64_t expiry; /* The unit is number of interrupts */
+TAILQ_HEAD(hal_timer_qhead, hal_timer) hal_timer_queue;
+};
+static struct pic32_timer timers[PIC32MZ_TIMER_COUNT];
+
+
+static inline uint32_t
+hal_timer_get_prescaler(int timer_num)
+{
+uint32_t index =
+(TxCON(timer_num) & _T2CON_TCKPS_MASK) >> _T2CON_TCKPS_POSITION;
+return timer_prescalers[index];
+}
+
+static inline uint32_t
+hal_timer_get_peripheral_base_clock(void)
+{
+return MYNEWT_VAL(CLOCK_FREQ) / ((PB3DIV & _PB3DIV_PBDIV_MASK) + 1);
+}
+
+static void
+hal_timer_enable_int(int timer_num)
+{
+switch (timer_num) {
+case 0:
+IPC2CLR = _IPC2_T2IP_MASK | _IPC2_T2IS_MASK;
+IPC2SET = 3 << _IPC2_T2IP_POSITION;
+IFS0CLR = _IFS0_T2IF_MASK;
+IEC0SET = _IEC0_T2IE_MASK;
+break;
+case 1:
+IPC3CLR = _IPC3_T3IP_MASK | _IPC3_T3IS_MASK;
+IPC3SET = 3 << _IPC3_T3IP_POSITION;
+IFS0CLR = _IFS0_T3IF_MASK;
+IEC0SET = _IEC0_T3IE_MASK;
+break;
+case 2:
+IPC4CLR = _IPC4_T4IP_MASK | _IPC4_T4IS_MASK;
+IPC4SET = 3 << _IPC4_T4IP_POSITION;
+IFS0CLR = _IFS0_T4IF_MASK;
+IEC0SET = _IEC0_T4IE_MASK;
+break;
+case 3:
+IPC6CLR = _IPC6_T5IP_MASK | _IPC6_T5IS_MASK;
+IPC6SET = 3 << _IPC6_T5IP_POSITION;
+IFS0CLR = _IFS0_T5IF_MASK;
+IEC0SET = _IEC0_T5IE_MASK;
+break;
+case 4:
+IPC7CLR = _IPC7_T6IP_MASK | _IPC7_T6IS_MASK;
+IPC7SET = 3 << _IPC7_T6IP_POSITION;
+IFS0CLR = _IFS0_T6IF_MASK;
+IEC0SET = _IEC0_T6IE_MASK;
+break;
+case 5:
+IPC8CLR = _IPC8_T7IP_MASK | _IPC8_T7IS_MASK;
+IPC8SET = 3 << _IPC8_T7IP_POSITION;
+IFS1CLR = _IFS1_T7IF_MASK;
+IEC1SET = _IEC1_T7IE_MASK;
+break;
+case 6:
+IPC9CLR = _IPC9_T8IP_MASK | _IPC9_T8IS_MASK;
+IPC9SET = 3 << _IPC9_T8IP_POSITION;
+IFS1CLR = _IFS1_T8IF_MASK;
+IEC1SET = _IEC1_T8IE_MASK;
+break;
+case 7:
+IPC10CLR = _IPC10_T9IP_MASK | _IPC10_T9IS_MASK;
+IPC10SET = 3 << _IPC10_T9IP_POSITION;
+IFS1CLR = _IFS1_T9IF_MASK;
+IEC1SET = _IEC1_T9IE_MASK;
+break;
+}
+}
+
+static void
+hal_timer_disable_int(int timer_num)
+{
+switch (timer_num) {
+case 0:
+IEC0CLR = _IEC0_T2IE_MASK;
+IFS0CLR = _IFS0_T2IF_MASK;
+break;
+case 1:
+IEC0CLR = _IEC0_T3IE_MASK;
+IFS0CLR = _IFS0_T3IF_MASK;
+break;
+case 2:
+IEC0CLR = _IEC0_T4IE_MASK;
+
