Re: [coreboot] Coreboot fails to initialize on ASUS A8V-E SE
Myles Watson escribió:
>
>> -Original Message-
>> From: Knut Kujat [mailto:kn...@gap.upv.es]
>> Sent: Saturday, December 05, 2009 5:57 AM
>> To: Myles Watson
>> Cc: 'Jonathan Rogers'; coreboot@coreboot.org
>> Subject: Re: [coreboot] Coreboot fails to initialize on ASUS A8V-E SE
>>
>> Hi,
>>
>> I'm trying to build coreboot for the exact same board and getting to
>> the same point as Jonathan Rogers. I also tried with the patch and same
>> result it hangs at "now booting... fallback". I inserted some prints
>> and get till
>>
>> else if (do_normal_boot()) {
>>
>> printf_info("debug6");
>>
>> goto normal_image;
>>
> Great.
>
>
>> any suggestions?
>>
>
> There is no normal_image with Kconfig yet. The quick way to test would be
> to change all normal_image to fallback_image, or any other way to make sure
> it never jumps to normal_image.
>
Hello,
worked fine now I'm getting a little further ;) :
coreboot-2.3 Fri Dec 4 20:15:37 CET 2009
starting...
now booting...
real_main
core0 started:
now booting... Core0 started
started ap apicid:
SBLink=00
NC node|link=00
K8T890 found at LDT 00 Agreed on width: 01 CPU programmed to HT freq: 06
VIA HT caps: 0075
ht reset -
soft reset
coreboot-2. normal_image replaced with fallback_imageWelcome to the
real_main!
coreboot-2.3 Fri Dec 4 20:15:37 CET 2009 starting...
now booting... real_main
core0 started:
now booting... Core0 started
started ap apicid:
SBLink=00
NC node|link=00
K8T890 found at LDT 00 Agreed on width: 01 CPU programmed to HT freq: 06
VIA HT caps: 0075
Current fid_cur: 0x10, fid_max: 0x10
Requested fid_new: 0x10
Debug: after init_fidvid_bsp
Debug: after allow_all_aps_stop
Debug: after fill_mem_ctrl
Debug: after enable_smbus
Debug: after memreset_setup
Ram1.00
Ram2.00
Device error
Device error
No memory for this cpu
Ram3
No memory
but now it seems that coreboot doesn't find any ram. I already tried
with patched Kconfig and without same result.
thx,
Knut Kujat
> Thanks,
> Myles
>
>
>
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Re: [coreboot] Coreboot fails to initialize on ASUS A8V-E SE
> > worked fine now I'm getting a little further ;) : > Good. > coreboot-2.3 Fri Dec 4 20:15:37 CET 2009 > starting... > > now booting... > real_main > > core0 started: > now booting... Core0 started > started ap apicid: > SBLink=00 > NC node|link=00 > K8T890 found at LDT 00 Agreed on width: 01 CPU programmed to HT freq: 06 > VIA HT caps: 0075 > ht reset - > soft reset > > > coreboot-2. normal_image replaced with fallback_imageWelcome to the > real_main! > > coreboot-2.3 Fri Dec 4 20:15:37 CET 2009 starting... > now booting... real_main > core0 started: > now booting... Core0 started > started ap apicid: > SBLink=00 > NC node|link=00 > K8T890 found at LDT 00 Agreed on width: 01 CPU programmed to HT freq: 06 > VIA HT caps: 0075 > Current fid_cur: 0x10, fid_max: 0x10 > Requested fid_new: 0x10 > Debug: after init_fidvid_bsp > Debug: after allow_all_aps_stop > Debug: after fill_mem_ctrl > Debug: after enable_smbus > Debug: after memreset_setup > Ram1.00 > Ram2.00 > Device error > Device error > No memory for this cpu > Ram3 > No memory > > but now it seems that coreboot doesn't find any ram. I already tried with > patched Kconfig and without same result. > I haven't played with RAM initialization much. The "Device error" message is coming from the smbus, so I would try to see how that is configured and put more debugging statements in there. I see that enable_smbus ran, so I don't know what's missing. Hopefully someone who knows more will chime in. Is there a cmos option that could be causing trouble? I'd check that too since the board was choosing to do a normal boot. Thanks, Myles -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Coreboot fails to initialize on ASUS A8V-E SE
Myles Watson escribió: > > > worked fine now I'm getting a little further ;) : > > Good. > > > coreboot-2.3 Fri Dec 4 20:15:37 CET 2009 > starting... > > > now booting... > real_main > > > core0 started: > now booting... Core0 started > started ap apicid: > SBLink=00 > NC node|link=00 > K8T890 found at LDT 00 Agreed on width: 01 CPU programmed to HT > freq: 06 VIA HT caps: 0075 > ht reset - > soft reset > > > coreboot-2. normal_image replaced with fallback_imageWelcome to > the real_main! > > coreboot-2.3 Fri Dec 4 20:15:37 CET 2009 starting... > now booting... real_main > core0 started: > now booting... Core0 started > started ap apicid: > SBLink=00 > NC node|link=00 > K8T890 found at LDT 00 Agreed on width: 01 CPU programmed to HT > freq: 06 VIA HT caps: 0075 > Current fid_cur: 0x10, fid_max: 0x10 > Requested fid_new: 0x10 > Debug: after init_fidvid_bsp > Debug: after allow_all_aps_stop > Debug: after fill_mem_ctrl > Debug: after enable_smbus > Debug: after memreset_setup > Ram1.00 > Ram2.00 > Device error > Device error > No memory for this cpu > Ram3 > No memory > > but now it seems that coreboot doesn't find any ram. I already > tried with patched Kconfig and without same result. > > > I haven't played with RAM initialization much. The "Device error" > message is coming from the smbus, so I would try to see how that is > configured and put more debugging statements in there. I see that > enable_smbus ran, so I don't know what's missing. Hopefully someone > who knows more will chime in. > > Is there a cmos option that could be causing trouble? I'd check that > too since the board was choosing to do a normal boot. > > Thanks, > Myles Hi, thanks for your help so far. I cleared the CMOS before restart but nothing. Ram1.00 setting up CPU00 northbridge registers done. Ram2.00 Debug: in smbus_read_byte Debug: after smbus_reset Debug: after SMBUS_DELAY (first) Debug: after smbus_wait-until_ready (first) Debug: after SMBUS_DELAY (second) Device error Debug: smbus_wait-until_ready (second) Debug: out smbus_read_byte Debug: in smbus_read_byte Debug: after smbus_reset Debug: after SMBUS_DELAY (first) Debug: after smbus_wait-until_ready (first) Debug: after SMBUS_DELAY (second) Debug: smbus_wait-until_ready (second) Debug: out smbus_read_byte Debug: in smbus_read_byte Debug: after smbus_reset Debug: after SMBUS_DELAY (first) Debug: after smbus_wait-until_ready (first) Debug: after SMBUS_DELAY (second) Device error Debug: smbus_wait-until_ready (second) Debug: out smbus_read_byte Debug: in smbus_read_byte Debug: after smbus_reset Debug: after SMBUS_DELAY (first) Debug: after smbus_wait-until_ready (first) Debug: after SMBUS_DELAY (second) Debug: smbus_wait-until_ready (second) Debug: out smbus_read_byte No memory for this cpu Ram3 No memory This board has 4 sockets but only 2 are populated with 1GB dimms each. Could the other empty two sockets be the device error, which is generated by the smbus_wait_until_ready function? But why would it say that there is no memory at all? Yet another question, I can see PRINT_DEBUG in vt8237r_early_smbus.c but i can't see them on the serial although I have the highest message level. Why? thx, Knut Kujat -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Coreboot fails to initialize on ASUS A8V-E SE
> This board has 4 sockets but only 2 are populated with 1GB dimms each. Could > the other empty two sockets be the device error, which is generated by the > smbus_wait_until_ready function? But why would it say that there is no > memory at all? I don't know. > Yet another question, I can see PRINT_DEBUG in vt8237r_early_smbus.c but i > can't see them on the serial although I have the highest message level. Why? I think you're on the right track. from vt8237r.h: #if DEBUG_SMBUS == 1 #define PRINT_DEBUG(x) print_debug(x) #define PRINT_DEBUG_HEX16(x)print_debug_hex16(x) #else #define PRINT_DEBUG(x) #define PRINT_DEBUG_HEX16(x) #endif I'm guessing that DEBUG_SMBUS is not 1. Change it to #if 1 and recompile. Thanks, Myles -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Coreboot fails to initialize on ASUS A8V-E SE
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Hi, Try experimenting with the position of used memory slots. Maybe you just need to put DIMMS into right places ;) I think I used the slot closest to CPU then one empty and then the second DIM and then the closest to edge empty. Rudolf -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.10 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAksdkdYACgkQ3J9wPJqZRNVaygCfQDhss8CY0ZsWvtr9/yjxUnW4 elAAniuDIxlJq33LDiPB35M297F3mkSA =+f/r -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] VIA EDEN ESP (C3) + Apollo CLE266(VT8623) + VT8237R + W83627HG
I am working on setting up CoreBoot Compulab's CM-iVCF
computer-on-module. It's essentially like an EPIA-MS board
(http://www.ewayco.com/20-low-cost-embedded-epia-mini-itx-etc-boards/epia-ms-mini-itx-low-cost-via-embedded-boards.html)
but with a WinBond super-IO. I'm aware this is rather old board, but the
chipset combination has been popular in various embedded projects, and
it looks like porting CoreBoot on EPIA-MS has come up on this list from
time to time. Has anybody got this combination working with CoreBoot,
still working on it, or have general tips on it?
Presently, my main problem seems to be that the
northbridge/via/vt8623/raminit.h does not define a mem_controller struct
required by the southbridge code, so the north- and southbridge code
don't seem to be clearly delimited. My code does compile if I use the
northbridge/via/cn400/raminit.h definition instead, but not surprisingly
there's no output on the console. The website seems to have few pointers
on debugging.
Chip markings on the board I'm working with:
CPU: Eden ESP 10K (133X7.5)1.05V SET BWT6E-0610
Northbridge: CLE266 0610CE
Southbridge: VT8237R 0551CD
WinBond Super-IO: W83627HG-AW
DDR memory: Hynix 515A HY5DU121622BT-J
In addition there's at least W311H clock-generator and W255H DDR2 clock
buffer.
Here's the main() I'm using, which is a combination the EPIA-M (vt8623 +
vt8235 + vt1211) and EPIA-N (cn400 + vt8237r + w83697hf) code:
static void main(unsigned long bist)
{
unsigned long x;
device_t dev;
/* Enable multifunction for northbridge. */
// Not using cn400 northbridge
//pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
w83697hf_set_clksel_48(SERIAL_DEV);
w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
print_spew("In auto.c:main()\r\n");
enable_smbus();
smbus_fixup(&ctrl);
/* Halt if there was a built-in self test failure. */
report_bist_failure(bist);
print_debug("Enabling mainboard devices\r\n");
enable_mainboard_devices();
print_debug("Enable F-ROM Shadow RAM\r\n");
enable_shadow_ram();
/* setup cpu */
// This doesn't appear in EPIA-M, probably northbridge specific
//print_debug("Setup CPU Interface\r\n");
//c3_cpu_setup(ctrl.d0f2);
//ddr_ram_setup();
ddr_ram_setup((const struct mem_controller *)0);
if (bist == 0) {
print_debug("doing early_mtrr\r\n");
early_mtrr_init();
}
//ram_check(0, 640 * 1024);
print_spew("Leaving auto.c:main()\r\n");
}
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Re: [coreboot] VIA EDEN ESP (C3) + Apollo CLE266(VT8623) + VT8237R + W83627HG
On 12/8/09 12:58 AM, Andrej Skirn wrote: > Presently, my main problem seems to be that the > northbridge/via/vt8623/raminit.h does not define a mem_controller > struct required by the southbridge code, so the north- and southbridge > code don't seem to be clearly delimited. try completely commenting out smbus_fixup... Stefan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
