Re: [coreboot] Coreboot fails to initialize on ASUS A8V-E SE

[Knut Kujat]

Myles Watson escribió:
>
> I tried pushing the stuck to 2000 4000 and even 2 but nothing
> it still stucks at the same place: setting up some printk I found
> out that it hangs :
>
> void pci_write_config16(device_t dev, unsigned where, uint16_t val)
> {
> struct bus *pbus = get_pbus(dev);
> ops_pci_bus(pbus)->write16(pbus, dev->bus->secondary,
> dev->path.pci.devfn, where, val);  << HERE!!
> }
>
> I think your problem is earlier.  This just happens to be where it
> catches up with you.
aha, ok!
>  
>
>
> btw, what do you mean by memory problem because as I said before I
> already switched my dimms whithout any results.
>
> I meant that it's possible that RAM is not initialized correctly. 
> Sometimes cache will get you a long ways.
>  
>
> I attached the whole boot sequence.
>
> Thanks.  The device enumeration looks wrong.  There are a lot of
> devices that are found, and  there are a lot of sequences like this:
>
> Capability: type 0x10 @ 0x58
> Capability: type 0x01 @ 0x50
> Capability: type 0x10 @ 0x58
> Capability: type 0x01 @ 0x50
> Capability: type 0x10 @ 0x58
> Capability: type 0x01 @ 0x50
>
> Could you send an lspci -tvnn of your board?
Of course, please find it attached.
>
> I really appreciate your help, thx!
>
> No problem.
> Myles
>
THX,
Knut Kujat
-[:00]-+-00.0  VIA Technologies, Inc. K8T890 Host Bridge [1106:0238]
   +-00.1  VIA Technologies, Inc. K8T890 Host Bridge [1106:1238]
   +-00.2  VIA Technologies, Inc. K8T890 Host Bridge [1106:2238]
   +-00.3  VIA Technologies, Inc. K8T890 Host Bridge [1106:3238]
   +-00.4  VIA Technologies, Inc. K8T890 Host Bridge [1106:4238]
   +-00.5  VIA Technologies, Inc. K8T890 I/O APIC Interrupt Controller 
[1106:5238]
   +-00.7  VIA Technologies, Inc. K8T890 Host Bridge [1106:7238]
   +-01.0-[:01]--
   +-02.0-[:02]--+-00.0  ATI Technologies Inc RV370 [Sapphire X550 
Silent] [1002:5b63]
   | \-00.1  ATI Technologies Inc RV370 secondary 
[Sapphire X550 Silent] [1002:5b73]
   +-03.0-[:03]--
   +-03.1-[:04]--
   +-03.2-[:05]00.0  Marvell Technology Group Ltd. 88E8053 
PCI-E Gigabit Ethernet Controller [11ab:4362]
   +-03.3-[:06]--
   +-0c.0  3Com Corporation 3c905B 100BaseTX [Cyclone] [10b7:9055]
   +-0f.0  VIA Technologies, Inc. VIA VT6420 SATA RAID Controller 
[1106:3149]
   +-0f.1  VIA Technologies, Inc. VT82C586A/B/VT82C686/A/B/VT823x/A/C 
PIPC Bus Master IDE [1106:0571]
   +-10.0  VIA Technologies, Inc. VT82x UHCI USB 1.1 Controller 
[1106:3038]
   +-10.1  VIA Technologies, Inc. VT82x UHCI USB 1.1 Controller 
[1106:3038]
   +-10.2  VIA Technologies, Inc. VT82x UHCI USB 1.1 Controller 
[1106:3038]
   +-10.3  VIA Technologies, Inc. VT82x UHCI USB 1.1 Controller 
[1106:3038]
   +-10.4  VIA Technologies, Inc. USB 2.0 [1106:3104]
   +-11.0  VIA Technologies, Inc. VT8237 ISA bridge 
[KT600/K8T800/K8T890 South] [1106:3227]
   +-11.5  VIA Technologies, Inc. VT8233/A/8235/8237 AC97 Audio 
Controller [1106:3059]
   +-11.6  VIA Technologies, Inc. AC'97 Modem Controller [1106:3068]
   +-18.0  Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] 
HyperTransport Technology Configuration [1022:1100]
   +-18.1  Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address 
Map [1022:1101]
   +-18.2  Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM 
Controller [1022:1102]
   \-18.3  Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] 
Miscellaneous Control [1022:1103]
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Re: [coreboot] Coreboot fails to initialize on ASUS A8V-E SE

[Rudolf Marek]

Hi,

Sorry I did not find time to test on mine board (if it still boots). Your PCI 
stuff looks normal. Can you try with just one DDR module?


Rudolf

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Re: [coreboot] Coreboot fails to initialize on ASUS A8V-E SE

[Knut Kujat]

Rudolf Marek escribió:
> Hi,
>
> Sorry I did not find time to test on mine board (if it still boots).
> Your PCI stuff looks normal. Can you try with just one DDR module?
>
> Rudolf
Hello,

I already tried switching DDR modules in different positions and of
course with only one to test if one of them is broken. But no changes! :(

Thanks,
Knut Kujat

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Re: [coreboot] Coreboot fails to initialize on ASUS A8V-E SE

[Rudolf Marek]

Hi,

Can you test with revision 3593?

I think you will need to do - buildtarget stuff ;)

Rudolf

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Re: [coreboot] Coreboot fails to initialize on ASUS A8V-E SE

[Knut Kujat]

Rudolf Marek escribió:
> Hi,
>
> Can you test with revision 3593?
OK, I'll try it !
>
> I think you will need to do - buildtarget stuff ;)
>
> Rudolf
Thx

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Re: [coreboot] [RFC] CMOS options

[Andrew Goodbody]

Luc Verhaegen wrote:
We have 892 bytes to our disposal in cmos. We can reserve 128 for 
board/cmos versioning, and reserve even 256 for the bootloader, and 
still have 512bytes left for coreboot options, which is tons when bits 
are used properly and when strings are not used.


Most boards I have used have a maximum space of 256 bytes that includes 
the RTC. Where does the extra come from?


Andrew

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Re: [coreboot] Coreboot fails to initialize on ASUS A8V-E SE

[Knut Kujat]

Rudolf Marek escribió:
> Hi,
>
> Can you test with revision 3593?
>
> I think you will need to do - buildtarget stuff ;)
>
> Rudolf
>
Hi,

It fails compiling and don't know exactly why:

gcc -m32  -nostdlib -nostartfiles -static -o coreboot -T ldscript.ld crt0.o
nm -n coreboot | sort > coreboot.map
objcopy --gap-fill 0xff -O binary coreboot coreboot.strip
gcc -o buildrom
/home/knuku/Documents/OldCor/coreboot/coreboot-v2/util/buildrom/buildrom.c
cp /home/knuku/bios.bin.elf payload
./buildrom coreboot.strip coreboot.rom payload 0x2 0x4
coreboot.strip: Value too large for defined data type
make[1]: *** [coreboot.rom] Error 2
make[1]: se sale del directorio
`/home/knuku/Documents/OldCor/coreboot/coreboot-v2/targets/asus/a8v-e_se/asus_a8v-e_se/normal'
make: *** [normal/coreboot.rom] Error 1

I did:

./buildtarget asus/a8v-e_se
cd asus/a8v-e_se
(set the right path to the payload in Config.lb)
cd asus_a8v-e_se
make

I tried with the same payload I did with the newer revisions filo.elf
and then I tried a already compiled seabios elf.

thx,
Knut Kujat




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Re: [coreboot] Using coreboot

[Knut Kujat]

Michael Lustfield escribió:
> I guess I missed part of this.. Here's lspci run as root.
>
> The system is a Sony Vaio VGN-FZ240E. I hope this help more.
>
Wow, a Vaio. Would like to know how do you manage a BIOS recovery once
you flashed the chip with a not working .rom? Do you actually have to
put it into pieces to reach the socket or the soldered chip?


thx,
Knut Kujat

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Re: [coreboot] Coreboot fails to initialize on ASUS A8V-E SE

[Knut Kujat]

Knut Kujat escribió:
> Rudolf Marek escribió:
>   
>> Hi,
>>
>> Can you test with revision 3593?
>>
>> I think you will need to do - buildtarget stuff ;)
>>
>> Rudolf
>>
>> 
> Hi,
>
> It fails compiling and don't know exactly why:
>
> gcc -m32  -nostdlib -nostartfiles -static -o coreboot -T ldscript.ld crt0.o
> nm -n coreboot | sort > coreboot.map
> objcopy --gap-fill 0xff -O binary coreboot coreboot.strip
> gcc -o buildrom
> /home/knuku/Documents/OldCor/coreboot/coreboot-v2/util/buildrom/buildrom.c
> cp /home/knuku/bios.bin.elf payload
> ./buildrom coreboot.strip coreboot.rom payload 0x2 0x4
> coreboot.strip: Value too large for defined data type
> make[1]: *** [coreboot.rom] Error 2
> make[1]: se sale del directorio
> `/home/knuku/Documents/OldCor/coreboot/coreboot-v2/targets/asus/a8v-e_se/asus_a8v-e_se/normal'
> make: *** [normal/coreboot.rom] Error 1
>
> I did:
>
> ./buildtarget asus/a8v-e_se
> cd asus/a8v-e_se
> (set the right path to the payload in Config.lb)
> cd asus_a8v-e_se
> make
>
> I tried with the same payload I did with the newer revisions filo.elf
> and then I tried a already compiled seabios elf.
>
> thx,
> Knut Kujat
>
>
>
>
>   
Hi,

I made it compile and it worked I get till filo payload after that it
stucks because:
Error 18: Selected cylinder exceeds maximum supported by BIOS

but I thing thats a minor problem the most important thing is that the
old revision worked.

thx,
Knut Kujat
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Re: [coreboot] Coreboot fails to initialize on ASUS A8V-E SE

[Rudolf Marek]

Hi,

Good news!

Please can you try the newer once?  Also, I would recommend to use seabios and 
./buildtarget build method for this board because I think kconfig was not tested.


I would suggest to go up to revision like 4096 ;) or go like binary search to 
find out where it broke. So if 4096 works go to 4500 etc else go to 3600... etc


You could try to run Seabios as payload. I will try to test the board next week.

Will be back Sunday night. Folks are often on IRC but you need to be more 
patient.

Rudolf

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Re: [coreboot] Coreboot fails to initialize on ASUS A8V-E SE

[Knut Kujat]

Rudolf Marek escribió:
> Hi,
>
> Good news!
>
> Please can you try the newer once?  Also, I would recommend to use
> seabios and ./buildtarget build method for this board because I think
> kconfig was not tested.
>
> I would suggest to go up to revision like 4096 ;) or go like binary
> search to find out where it broke. So if 4096 works go to 4500 etc
> else go to 3600... etc
OK, will try it!
>
> You could try to run Seabios as payload. I will try to test the board
> next week.
>
> Will be back Sunday night. Folks are often on IRC but you need to be
> more patient.
Yes I know! not my strength ;) 
>
> Rudolf
>

Thx,
Knut Kujat

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[coreboot] #151: v3 Geode cs5536 UART2 wrongly configured

[coreboot]

#151: v3 Geode cs5536 UART2 wrongly configured
---+
   Reporter:  edwin_beas...@…  |  Owner:  somebody
   Type:  defect   | Status:  new 
   Priority:  major|  Milestone:  Going mainstream
  Component:  coreboot |Version:  v3  
   Keywords:  serial com2 geode cs5536 |   Dependencies:  
Patchstatus:  patch needs review   |  
---+
 The UART2 on the AMD cs5536 is incorrectly configured in two places in v3
 code and also in v2.
 GPIO lines 4 and 3 are swapped and also incorrectly put in IR mode receive
 (compound fault).
 This patch corrects the v3 late configuration and the v3 and v2 early
 (stage1/cache as ram) mis-configuration of UART2 to addres 0x3f8 not the
 standard 0x2f8 for COM2.

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[coreboot] #152: v3 Geode cs5536 UART2 wrongly configured

[coreboot]

#152: v3 Geode cs5536 UART2 wrongly configured
---+
   Reporter:  edwin_beas...@…  |  Owner:  somebody
   Type:  defect   | Status:  new 
   Priority:  major|  Milestone:  Going mainstream
  Component:  coreboot |Version:  v3  
   Keywords:  serial com2 geode cs5536 |   Dependencies:  
Patchstatus:  patch needs review   |  
---+
 The UART2 on the AMD cs5536 is incorrectly configured in two places in v3
 code and also in v2.
 GPIO lines 4 and 3 are swapped and also incorrectly put in IR mode receive
 (compound fault).
 This patch corrects the v3 late configuration and the v3 and v2 early
 (stage1/cache as ram) mis-configuration of UART2 to addres 0x3f8 not the
 standard 0x2f8 for COM2.

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coreboot 

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Re: [coreboot] Coreboot fails to initialize on ASUS A8V-E SE

[Myles Watson]

> I made it compile and it worked I get till filo payload after that it
> stucks because:
> Error 18: Selected cylinder exceeds maximum supported by BIOS
>
> but I thing thats a minor problem the most important thing is that the old
> revision worked.
>

I'd like to see it work for you with Kconfig.  Could you send me a working
log for me to compare with the last one you sent me?

Thanks,
Myles
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Re: [coreboot] Coreboot for AMD 780G

[Darmawan Salihun]

that's pretty quick. Looking forward to it. Thanks :-)

On 12/9/09, Bao, Zheng  wrote:
> Now the code is being reviewed by the law department to make sure there
> isn't anything breaking the rules.
>
> Zheng
>
> -Original Message-
> From: coreboot-bounces+zheng.bao=amd@coreboot.org
> [mailto:coreboot-bounces+zheng.bao=amd@coreboot.org] On Behalf Of
> Goderic
> Sent: Wednesday, December 09, 2009 6:14 AM
> To: coreboot@coreboot.org
> Subject: [coreboot] Coreboot for AMD 780G
>
> Hello,
>
> This summer AMD released the documentation for SB700/SB710/SB750 and
> RS780.
> I was very excited about that, I have and AMD 780G board and I'd realy
> like to use coreboot. But I didn't hear anymore about it so I wonder
> how the work on is going.
>
> Thanks,
>
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>
>
>
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Re: [coreboot] [RFC] CMOS options

[ron minnich]

On Wed, Dec 9, 2009 at 2:57 AM, Andrew Goodbody
 wrote:
> Luc Verhaegen wrote:
>>
>> We have 892 bytes to our disposal in cmos. We can reserve 128 for
>> board/cmos versioning, and reserve even 256 for the bootloader, and still
>> have 512bytes left for coreboot options, which is tons when bits are used
>> properly and when strings are not used.
>
> Most boards I have used have a maximum space of 256 bytes that includes the
> RTC. Where does the extra come from?

On much of my hardware, the most I can assume is 128 bytes -
subtracting many bytes that are weirdly hardware controlled (such as
date).

Some of our hardware has 256 bytes.

The io ports only support an 8-bit address I thought?

That said, if newer parts really do have so much data, that is great news.

ron

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Re: [coreboot] Launchpad Import

[Carl-Daniel Hailfinger]

On 10.12.2009 23:00, Michael Lustfield wrote:
> I created a team/project in Launcpad so this branch can be imported
> into a bazaar branch.
>
> The project exists on there and is waiting to be imported. This will
> mirror your svn repository and offer to let others pull via bzr.
>
> I don't know that you can legally say this can't be done because it's
> licensed under GNU GPLv2 but I'd prefer knowing you are ok with this or
> remove it instead.

Sorry, I have trouble parsing that sentence. Could you please reword it?
The coreboot name itself is trademarked, but the source code is
available under the GPL v2.


> Personally, I like using LP because it also tends to get a project
> wider known. I don't know if this project needs wider publicity though.

While coreboot definitely appreciates wider publicity, some of us
believe that Launchpad will be an overall net loss. I'm not a project
leader, so my opinion is just an opinion. Given the fact that quite a
few projects had bad experiences with Launchpad, namely that it
fragments the community and encourages forking, I'm asking you to remove
this project from Launchpad. Feel free to wait for an response from our
project leaders if you disagree.


> So there's 3 options:
> 1) You hate it and request that I remove it (which I will do)
> 2) You don't care either way and feel like ignoring it
> 3) You like it but would prefer to be admin of team that owns it (I'll
>hand it over)

Of course we enourage everyone to keep a copy of coreboot on his/her
harddisk, regardless of the source control technology they use. Some
people run local (non-public) git-svn mirrors, and others work with
Mercurial. Feel free to keep your own bazaar mirror on your hard disk as
long as it doesn't retrieve the full tree with history from svn on every
update (that would cause excessive traffic costs for the private
individual who is donating the infrastructure for coreboot).


Regards,
Carl-Daniel
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