[coreboot] [commit] r5000 - in trunk/src: arch/i386 cpu/amd/model_10xxx cpu/amd/model_fxx cpu/amd/sc520 mainboard/emulation/qemu-x86 mainboard/supermicro/h8dmr_fam10 mainboard/tyan/s2912_fam10 southbr
Author: oxygene Date: 2010-01-06 10:14:08 +0100 (Wed, 06 Jan 2010) New Revision: 5000 Modified: trunk/src/arch/i386/Makefile.tinybootblock.inc trunk/src/cpu/amd/model_10xxx/Kconfig trunk/src/cpu/amd/model_fxx/Kconfig trunk/src/cpu/amd/sc520/Kconfig trunk/src/mainboard/emulation/qemu-x86/Kconfig trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig trunk/src/mainboard/supermicro/h8dmr_fam10/Makefile.inc trunk/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb trunk/src/mainboard/tyan/s2912_fam10/Kconfig trunk/src/mainboard/tyan/s2912_fam10/Makefile.inc trunk/src/southbridge/nvidia/mcp55/Makefile.inc trunk/src/southbridge/via/k8t890/Makefile.inc Log: Kconfig builds all boards now. This patch also aligns the configuration of a couple of boards more closely to what newconfig does. Also, the romstrap inc/lds files are declared in the Makefiles of the southbridges they belong to, instead of some global file. AMD CPUs have their own timer functions, so disable UDELAY_IO for them and set HAVE_INIT_TIMER as appropriate, same for emulation/qemu-x86. Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de Acked-by: Myles Watson myle...@gmail.com Modified: trunk/src/arch/i386/Makefile.tinybootblock.inc === --- trunk/src/arch/i386/Makefile.tinybootblock.inc 2010-01-05 17:35:44 UTC (rev 4999) +++ trunk/src/arch/i386/Makefile.tinybootblock.inc 2010-01-06 09:14:08 UTC (rev 5000) @@ -24,20 +24,15 @@ bootblock_lds += $(src)/cpu/x86/16bit/entry16.lds bootblock_lds += $(src)/cpu/x86/16bit/reset16.lds bootblock_lds += $(src)/arch/i386/lib/id.lds -ifeq ($(CONFIG_SOUTHBRIDGE_VIA_K8T890),y) -bootblock_lds += $(src)/southbridge/via/k8t890/romstrap.lds -endif +bootblock_lds += $(chipset_bootblock_lds) bootblock_inc := $(src)/arch/i386/init/bootblock_prologue.c bootblock_inc += $(src)/cpu/x86/16bit/entry16.inc bootblock_inc += $(src)/cpu/x86/16bit/reset16.inc bootblock_inc += $(src)/cpu/x86/32bit/entry32.inc bootblock_inc += $(src)/arch/i386/lib/id.inc +bootblock_inc += $(chipset_bootblock_inc) -ifeq ($(CONFIG_SOUTHBRIDGE_VIA_K8T890),y) -bootblock_inc += $(src)/southbridge/via/k8t890/romstrap.inc -endif - ifeq ($(CONFIG_SSE),y) bootblock_inc += $(src)/cpu/x86/sse_enable.inc endif Modified: trunk/src/cpu/amd/model_10xxx/Kconfig === --- trunk/src/cpu/amd/model_10xxx/Kconfig 2010-01-05 17:35:44 UTC (rev 4999) +++ trunk/src/cpu/amd/model_10xxx/Kconfig 2010-01-06 09:14:08 UTC (rev 5000) @@ -4,6 +4,7 @@ select USE_PRINTK_IN_CAR select USE_DCACHE_RAM select SSE + select HAVE_INIT_TIMER config CPU_ADDR_BITS int @@ -25,3 +26,7 @@ default 0x04000 depends on CPU_AMD_MODEL_10XXX +config UDELAY_IO + bool + default n + depends on CPU_AMD_MODEL_10XXX Modified: trunk/src/cpu/amd/model_fxx/Kconfig === --- trunk/src/cpu/amd/model_fxx/Kconfig 2010-01-05 17:35:44 UTC (rev 4999) +++ trunk/src/cpu/amd/model_fxx/Kconfig 2010-01-06 09:14:08 UTC (rev 5000) @@ -4,6 +4,7 @@ select USE_PRINTK_IN_CAR select USE_DCACHE_RAM select SSE + select HAVE_INIT_TIMER config CPU_ADDR_BITS int @@ -25,3 +26,8 @@ default 0x01000 depends on CPU_AMD_MODEL_FXX + +config UDELAY_IO + bool + default n + depends on CPU_AMD_MODEL_FXX Modified: trunk/src/cpu/amd/sc520/Kconfig === --- trunk/src/cpu/amd/sc520/Kconfig 2010-01-05 17:35:44 UTC (rev 4999) +++ trunk/src/cpu/amd/sc520/Kconfig 2010-01-06 09:14:08 UTC (rev 5000) @@ -1,3 +1,8 @@ config CPU_AMD_SC520 bool +config UDELAY_IO + bool + default n + depends on CPU_AMD_SC520 + Modified: trunk/src/mainboard/emulation/qemu-x86/Kconfig === --- trunk/src/mainboard/emulation/qemu-x86/Kconfig 2010-01-05 17:35:44 UTC (rev 4999) +++ trunk/src/mainboard/emulation/qemu-x86/Kconfig 2010-01-06 09:14:08 UTC (rev 5000) @@ -27,3 +27,8 @@ bool default n depends on BOARD_EMULATION_QEMU_X86 + +config UDELAY_IO + bool + default n + depends on BOARD_EMULATION_QEMU_X86 Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig === --- trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig 2010-01-05 17:35:44 UTC (rev 4999) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig 2010-01-06 09:14:08 UTC (rev 5000) @@ -15,6 +15,8 @@ select LIFT_BSP_APIC_ID select AMDMCT select BOARD_ROMSIZE_KB_1024 + select TINY_BOOTBLOCK + select ENABLE_APIC_EXT_ID config MAINBOARD_DIR string @@ -23,27 +25,42 @@ config
Re: [coreboot] [commit] r5000 - in trunk/src: arch/i386 cpu/amd/model_10xxx cpu/amd/model_fxx cpu/amd/sc520 mainboard/emulation/qemu-x86 mainboard/supermicro/h8dmr_fam10 mainboard/tyan/s2912_fam10 sou
On 06.01.2010 10:14, s...@coreboot.org wrote: Author: oxygene Date: 2010-01-06 10:14:08 +0100 (Wed, 06 Jan 2010) New Revision: 5000 Log: Kconfig builds all boards now. Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de Acked-by: Myles Watson myle...@gmail.com Congratulations on revision 5000 to all coreboot developers! We have reached a truly impressive milestone and I'm very happy about this. Regards, Carl-Daniel -- Developer quote of the year: We are juggling too many chainsaws and flaming arrows and tigers. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Help in Finding PCI IRQ Number
HiGood Afternoon i bought usb mass storage card from one company . the interface of my usb mass storage card with motheboard is PCI. the Design is smthing like this.. pci-Pci Bridge ---pci/USB2 bridge -- usb2/NAND controller-NAND CHIPS. the hardware manual of this card tells PCI Interrupt (INTB) is passed to PCI Slot. Now i wrote the pci Device Driver http://www.linuxforums.org/forum/linux-kernel/157955-help-finding-pci-i rq-number.html to know the vendor id, device id ,int line, int pin etc... i got the vendor id ,device id but on INT LINE i am getting 0XFF; i am not able to undestand tht why i am not getting the exact IRQ for this card... is this is correct way what i am doing if not please suggest me how to get the correct IRQ no thanks in advance Regards sandeep Gulati | HAL-Edgewood sandeep.gul...@haledgewood.com +919620291990 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Dell Optiplex GX150 Bios
My old Dell Optiplex GX150 Mini-Tower has Dell A11 Bios. The maximum RAM the system will support is 512MB-The system won't boot if more that 512MB is added to the two RAM slots (Memory Error). During a chat with the Dell online community I was told that the computer's hardware won't support more than 512MB of RAM. I did some research on the individual motherboard components and have come to believe that the Dell A11 Bios are limiting the RAM but, I'm not sure. I would like to Flash different Bios that allow for adding more RAM and give me greater control over the CPU. Coreboot does not list my motherboard but does list the individual chips except for my specific Northbridge which is an Intel 815 chipset. My board SCI28-R13 contains: northbridge Intel 82815, Southbridge Intel 82801 BA/BAM, Super I/O NSC PC87364, and the CPU is an Intel Pentium III 686. Will coreboot work with my computer? Will I be able to add more RAM if I flash coreboot? And if so, can someone hold my hand and walk me through the process so I don't turn my Dell into a boat anchor? -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [PATCH]AMDHT misbehaves on recent compilers
Hi,
src/northbridge/amdht/ht_wrapper.c miscompiles on recent compilers
(gcc-4.4.1 in crossgcc for example). The compiler is correct in what it
does, our code isn't.
The issue is that with recent compilers swaplist is generated on the
stack, and then a pointer to that structure on stack is passed around.
The data is nearly immediately destroyed by subsequent calls.
The const modifier only makes the compiler ensure that no write
operations are made to the data, but says nothing about the life cycle.
To force the compiler to keep the array in read-only memory, it must be
global const or static const.
Thanks go to Myles for isolating the problem.
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
Index: src/northbridge/amd/amdht/ht_wrapper.c
===
--- src/northbridge/amd/amdht/ht_wrapper.c (revision 4999)
+++ src/northbridge/amd/amdht/ht_wrapper.c (working copy)
@@ -116,7 +116,7 @@
*/
BOOL AMD_CB_ManualBUIDSwapList (u8 node, u16 link, u8 **List)
{
- const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE,
CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
+ static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE,
CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
/* If the BUID was adjusted in early_ht we need to do the manual
override */
if ((CONFIG_HT_CHAIN_UNITID_BASE != 0)
(CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
printk_debug(AMD_CB_ManualBUIDSwapList()\n);
--
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Re: [coreboot] [commit] r5000 - in trunk/src: arch/i386 cpu/amd/model_10xxx cpu/amd/model_fxx cpu/amd/sc520 mainboard/emulation/qemu-x86 mainboard/supermicro/h8dmr_fam10 mainboard/tyan/s2912_fam10 sou
I can't think of a better use for rev 5000 than the move to Kconfig. Thanks all :-) ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH]AMDHT misbehaves on recent compilers
arg, that kind of error is almost embarassing :-) Acked-by: Ronald G. Minnich rminn...@gmail.com ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r5001 - trunk/src/northbridge/amd/amdht
Author: oxygene
Date: 2010-01-06 11:07:31 +0100 (Wed, 06 Jan 2010)
New Revision: 5001
Modified:
trunk/src/northbridge/amd/amdht/ht_wrapper.c
Log:
Fix amdht on newer compilers.
We were lucky with friendly compilers. Now they're assuming too much.
Identified-by: Myles Watson myle...@gmail.com
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
Acked-by: Ronald G. Minnich rminn...@gmail.com
Modified: trunk/src/northbridge/amd/amdht/ht_wrapper.c
===
--- trunk/src/northbridge/amd/amdht/ht_wrapper.c2010-01-06 09:14:08 UTC
(rev 5000)
+++ trunk/src/northbridge/amd/amdht/ht_wrapper.c2010-01-06 10:07:31 UTC
(rev 5001)
@@ -116,7 +116,7 @@
*/
BOOL AMD_CB_ManualBUIDSwapList (u8 node, u16 link, u8 **List)
{
- const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE,
CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
+ static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE,
CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
/* If the BUID was adjusted in early_ht we need to do the manual
override */
if ((CONFIG_HT_CHAIN_UNITID_BASE != 0)
(CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
printk_debug(AMD_CB_ManualBUIDSwapList()\n);
--
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[coreboot] When should we retire newconfig?
Hi, With r5000 all boards build with kconfig. The last step of the buildconfig project is to eliminate the old system so we're down to one method of building an image. What issues remain before we can remove newconfig from the tree? My list currently contains: * Kconfig must match newconfig for all boards, as appropriate. The automatic KBuild report on the list (which can be regenerated locally by running util/kbuildall/kbuildall) gives some indication on how much work is left in that area. * More testing I'm not sure how many boards and chipsets were successfully run with a kconfig image recently. * Fallback/normal switch While the hard part in code is done for the switch (via tinybootblock), there are some issues left. kbuild always builds just one image, not two as would be necessary to build fallback/normal in a single pass. Question is, do we want that? In my opinion, it's more sensible to have a way to add to and update an existing coreboot image, and expect users who rely on fallback/normal to build twice (into the same image), with an appropriate configuration for each run. Either way, this requires support in the build system (either to update, or to build twice in one go), and some alternative tinybootblock routine. * Documentation I'll try to work out some documentation for the new config system and code flow (esp. tinybootblock). Apart from that, with kconfig, many of the build tutorials on the wiki will be outdated. Patrick -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Ask for install advices
Hi, all, I am new in coreboot. Now for fasting boot, I want to install coreboot to a PC104 computer. I wonder whether it is supported by the coreboot. The following is some information of the martherboard, 1. Vendor: NORCO 2. Mainboard:EMB-3680 3. Northbridge: AMD Geode LX 800 4. Southbridge: AMD Geode CS5536 5. Super I/O: Winbond W83627HG 6. CPU: AMD Geode LX-800-500MHz 7. Home page: http://www.norco.cn/ArticleShow.asp?ArticleID=31BigClassName=Embedded%20Industrial%20MotherboardSmallClassName=3.5%20Inch%20Motherboard And run lspci, it displays, 00:01.0 Host bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] Host Bridge (rev 33) 00:01.1 VGA compatible controller: Advanced Micro Devices [AMD] Geode LX Video 00:0c.0 Bridge: Integrated Technology Express, Inc. ITF/G PCI to ISA Bridge with SMB [Golden Gate] (rev 03) 00:0e.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ (rev 10) 00:0f.0 ISA bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA (rev 03) 00:0f.2 IDE interface: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE (rev 01) 00:0f.3 Multimedia audio controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] Audio (rev 01) 00:0f.4 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC (rev 02) 00:0f.5 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC (rev 02) 00:11.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ (rev 10) From the supported boards list of coreboot website, this PC104 computer is the most similar to IEI IEI PCISA-LX-800-R10 in coreboot v2, except the supper I/O is W83627EHG. Based on the above mentioned points, can I follow the tutorial of IEI IEI PCISA-LX-800-R10 to install the coreboot v2 to PC104 computer? And any hint? Thank you for any input? 2010-01-06 Gavin -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Dell Optiplex GX150 Bios
On Wed, Jan 6, 2010 at 4:32 AM, CHRIS PITZER dogst...@q.com wrote: My old Dell Optiplex GX150 Mini-Tower has Dell A11 Bios. The maximum RAM the system will support is 512MB-The system won't boot if more that 512MB is added to the two RAM slots (Memory Error). During a chat with the Dell online community I was told that the computer's hardware won't support more than 512MB of RAM. I did some research on the individual motherboard components and have come to believe that the Dell A11 Bios are limiting the RAM but, I'm not sure. I would like to Flash different Bios that allow for adding more RAM and give me greater control over the CPU. Coreboot does not list my motherboard but does list the individual chips except for my specific Northbridge which is an Intel 815 chipset. My board SCI28-R13 contains: northbridge Intel 82815, Southbridge Intel 82801 BA/BAM, Super I/O NSC PC87364, and the CPU is an Intel Pentium III 686. Will coreboot work with my computer? Will I be able to add more RAM if I flash coreboot? And if so, can someone hold my hand and walk me through the process so I don't turn my Dell into a boat anchor? -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot Hello! As it happens I am quite familiar with that model. Sadly Dell TS is quite correct. But it isn't their BIOS who is at fault, it is the chipset who is. It is an Intel 810 one. While the respective Super IO is well known to us, the chipset for the other features may not be. This might end up being an entirely new port, and depending on how much information is available regarding the chipset you would be able to do so. I suggest that you provide us with a complete display of these features. The website contains complete instructions on doing so, as does the archives for the list. But the rest of the list will respond accordingly. - Gregg C Levine gregg.drw...@gmail.com This signature fought the Time Wars again and again. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] a bit more user friendly cbfstool print
Hello I know that all experienced corebooters knew well that null mean empty space but that was't obvious for me when i tried first time compile coreboot. Patch in attachment. Signed-off by: Maciej Pijanka maciej.pija...@gmail.com -- Maciej Pijanka reg. Linux user #133161 Index: util/cbfstool/common.c === --- util/cbfstool/common.c (revision 5001) +++ util/cbfstool/common.c (working copy) @@ -165,6 +165,13 @@ struct cbfs_file *thisfile = (struct cbfs_file *)phys_to_virt(current); uint32_t length = ntohl(thisfile-len); + const char *fname = (const char *)(phys_to_virt(current) + sizeof(struct cbfs_file)); + if (strlen(fname) == 0) + printf(%-30s 0x%-8x %-12s %d\n, (empty), + current - phys_start, strfiletype(ntohl(thisfile-type)), + length); + + else printf(%-30s 0x%-8x %-12s %d\n, (const char *)(phys_to_virt(current) + sizeof(struct cbfs_file)), -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r5002 - trunk
Author: myles Date: 2010-01-06 17:59:18 +0100 (Wed, 06 Jan 2010) New Revision: 5002 Modified: trunk/Makefile Log: Check for installed compilers (remove .xcompile) at make clean, not distclean. Signed-off-by: Myles Watson myle...@gmail.com Acked-by: Myles Watson myle...@gmail.com Modified: trunk/Makefile === --- trunk/Makefile 2010-01-06 10:07:31 UTC (rev 5001) +++ trunk/Makefile 2010-01-06 16:59:18 UTC (rev 5002) @@ -292,7 +292,7 @@ rm -rf $(DOXYGEN_OUTPUT_DIR) clean: doxygen-clean - rm -f $(allobjs) $(obj)/coreboot* + rm -f $(allobjs) $(obj)/coreboot* .xcompile rm -rf $(obj)/bootblock* $(obj)/romstage* $(obj)/location.* rm -f $(obj)/option_table.* $(obj)/crt0_includes.h $(obj)/ldscript rm -f $(obj)/mainboard/$(MAINBOARDDIR)/static.c $(obj)/mainboard/$(MAINBOARDDIR)/config.py $(obj)/mainboard/$(MAINBOARDDIR)/static.dot @@ -301,7 +301,7 @@ $(MAKE) -C util/sconfig clean distclean: clean - rm -rf $(obj) .xcompile + rm -rf $(obj) rm -f .config .config.old ..config.tmp .kconfig.d .tmpconfig* update: -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r5003 - trunk/src/northbridge/amd/amdfam10
Author: myles Date: 2010-01-06 18:05:37 +0100 (Wed, 06 Jan 2010) New Revision: 5003 Modified: trunk/src/northbridge/amd/amdfam10/Makefile.inc Log: Move fam10 temp files from build/ to build/northbridge/amd/amdfam10/ Trivial. Signed-off-by: Myles Watson myle...@gmail.com Acked-by: Myles Watson myle...@gmail.com Modified: trunk/src/northbridge/amd/amdfam10/Makefile.inc === --- trunk/src/northbridge/amd/amdfam10/Makefile.inc 2010-01-06 16:59:18 UTC (rev 5002) +++ trunk/src/northbridge/amd/amdfam10/Makefile.inc 2010-01-06 17:05:37 UTC (rev 5003) @@ -13,33 +13,33 @@ ifdef POST_EVALUATION $(obj)/northbridge/amd/amdfam10/ssdt.c: $(src)/northbridge/amd/amdfam10/ssdt.dsl - iasl -p $(obj)/ssdt -tc $ - perl -pi -e 's/AmlCode/AmlCode_ssdt/g' $(obj)/ssdt.hex - mv $(obj)/ssdt.hex $@ + iasl -p $(obj)/northbridge/amd/amdfam10/ssdt -tc $ + perl -pi -e 's/AmlCode/AmlCode_ssdt/g' $(obj)/northbridge/amd/amdfam10/ssdt.hex + mv $(obj)/northbridge/amd/amdfam10/ssdt.hex $@ $(obj)/northbridge/amd/amdfam10/sspr1.c: $(src)/northbridge/amd/amdfam10/sspr1.dsl - iasl -p $(obj)/sspr1 -tc $ - perl -pi -e 's/AmlCode/AmlCode_sspr1/g' $(obj)/sspr1.hex - mv $(obj)/sspr1.hex $@ + iasl -p $(obj)/northbridge/amd/amdfam10/sspr1 -tc $ + perl -pi -e 's/AmlCode/AmlCode_sspr1/g' $(obj)/northbridge/amd/amdfam10/sspr1.hex + mv $(obj)/northbridge/amd/amdfam10/sspr1.hex $@ $(obj)/northbridge/amd/amdfam10/sspr2.c: $(src)/northbridge/amd/amdfam10/sspr2.dsl - iasl -p $(obj)/sspr2 -tc $ - perl -pi -e 's/AmlCode/AmlCode_sspr2/g' $(obj)/sspr2.hex - mv $(obj)/sspr2.hex $@ + iasl -p $(obj)/northbridge/amd/amdfam10/sspr2 -tc $ + perl -pi -e 's/AmlCode/AmlCode_sspr2/g' $(obj)/northbridge/amd/amdfam10/sspr2.hex + mv $(obj)/northbridge/amd/amdfam10/sspr2.hex $@ $(obj)/northbridge/amd/amdfam10/sspr3.c: $(src)/northbridge/amd/amdfam10/sspr3.dsl - iasl -p $(obj)/sspr3 -tc $ - perl -pi -e 's/AmlCode/AmlCode_sspr3/g' $(obj)/sspr3.hex - mv $(obj)/sspr3.hex $@ + iasl -p $(obj)/northbridge/amd/amdfam10/sspr3 -tc $ + perl -pi -e 's/AmlCode/AmlCode_sspr3/g' $(obj)/northbridge/amd/amdfam10/sspr3.hex + mv $(obj)/northbridge/amd/amdfam10/sspr3.hex $@ $(obj)/northbridge/amd/amdfam10/sspr4.c: $(src)/northbridge/amd/amdfam10/sspr4.dsl - iasl -p $(obj)/sspr4 -tc $ - perl -pi -e 's/AmlCode/AmlCode_sspr4/g' $(obj)/sspr4.hex - mv $(obj)/sspr4.hex $@ + iasl -p $(obj)/northbridge/amd/amdfam10/sspr4 -tc $ + perl -pi -e 's/AmlCode/AmlCode_sspr4/g' $(obj)/northbridge/amd/amdfam10/sspr4.hex + mv $(obj)/northbridge/amd/amdfam10/sspr4.hex $@ $(obj)/northbridge/amd/amdfam10/sspr5.c: $(src)/northbridge/amd/amdfam10/sspr5.dsl - iasl -p $(obj)/sspr5 -tc $ - perl -pi -e 's/AmlCode/AmlCode_sspr5/g' $(obj)/sspr5.hex - mv $(obj)/sspr5.hex $@ + iasl -p $(obj)/northbridge/amd/amdfam10/sspr5 -tc $ + perl -pi -e 's/AmlCode/AmlCode_sspr5/g' $(obj)/northbridge/amd/amdfam10/sspr5.hex + mv $(obj)/northbridge/amd/amdfam10/sspr5.hex $@ endif -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] a bit more user friendly cbfstool print
Am 06.01.2010 17:20, schrieb Maciej Pijanka: Hello I know that all experienced corebooters knew well that null mean empty space but that was't obvious for me when i tried first time compile coreboot. Patch in attachment. Signed-off by: Maciej Pijanka maciej.pija...@gmail.com + if (strlen(fname) == 0) + printf(%-30s 0x%-8x %-12s %d\n, (empty), + current - phys_start, strfiletype(ntohl(thisfile-type)), + length); + + else printf(%-30s 0x%-8x %-12s %d\n, (const char *)(phys_to_virt(current) + sizeof(struct cbfs_file)), I don't quite like the duplication that's going on here.. how about if (strlen(fname) == 0) fname = (empty); printf(..., fname, ...); instead? That way, when we feel the need to change that string, we only have to change it once. Patrick -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] a bit more user friendly cbfstool print
On Wed, 06 Jan 2010, Patrick Georgi wrote: Am 06.01.2010 17:20, schrieb Maciej Pijanka: Hello I know that all experienced corebooters knew well that null mean empty space but that was't obvious for me when i tried first time compile coreboot. Patch in attachment. Signed-off by: Maciej Pijanka maciej.pija...@gmail.com + if (strlen(fname) == 0) + printf(%-30s 0x%-8x %-12s %d\n, (empty), +current - phys_start, strfiletype(ntohl(thisfile-type)), +length); + + else printf(%-30s 0x%-8x %-12s %d\n, (const char *)(phys_to_virt(current) + sizeof(struct cbfs_file)), I don't quite like the duplication that's going on here.. how about if (strlen(fname) == 0) fname = (empty); printf(..., fname, ...); instead? That way, when we feel the need to change that string, we only have to change it once. right sounds much better, see changed version. -- Maciej Pijanka reg. Linux user #133161 Index: util/cbfstool/common.c === --- util/cbfstool/common.c (revision 5001) +++ util/cbfstool/common.c (working copy) @@ -165,9 +165,11 @@ struct cbfs_file *thisfile = (struct cbfs_file *)phys_to_virt(current); uint32_t length = ntohl(thisfile-len); - printf(%-30s 0x%-8x %-12s %d\n, - (const char *)(phys_to_virt(current) + - sizeof(struct cbfs_file)), + char *fname = (char *)(phys_to_virt(current) + sizeof(struct cbfs_file)); + if (strlen(fname) == 0) + fname = (empty); + + printf(%-30s 0x%-8x %-12s %d\n, fname, current - phys_start, strfiletype(ntohl(thisfile-type)), length); current = -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Ask for install advices on NORCO EMB-3680 AMD Geode LX 800
Dear Gavin, Am Mittwoch, den 06.01.2010, 19:59 +0800 schrieb Gavin: I am new in coreboot. Now for fasting boot, I want to install coreboot to a PC104 computer. I wonder whether it is supported by the coreboot. The following is some information of the martherboard, 1. Vendor: NORCO 2. Mainboard:EMB-3680 3. Northbridge: AMD Geode LX 800 4. Southbridge: AMD Geode CS5536 5. Super I/O: Winbond W83627HG 6. CPU: AMD Geode LX-800-500MHz 7. Home page: http://www.norco.cn/ArticleShow.asp?ArticleID=31BigClassName=Embedded %20Industrial%20MotherboardSmallClassName=3.5%20Inch%20Motherboard And run lspci, it displays, 00:01.0 Host bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] Host Bridge (rev 33) 00:01.1 VGA compatible controller: Advanced Micro Devices [AMD] Geode LX Video 00:0c.0 Bridge: Integrated Technology Express, Inc. ITF/G PCI to ISA Bridge with SMB [Golden Gate] (rev 03) 00:0e.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ (rev 10) 00:0f.0 ISA bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA (rev 03) 00:0f.2 IDE interface: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE (rev 01) 00:0f.3 Multimedia audio controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] Audio (rev 01) 00:0f.4 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC (rev 02) 00:0f.5 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC (rev 02) 00:11.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ (rev 10) From the supported boards list of coreboot website, this PC104 computer is the most similar to IEI IEI PCISA-LX-800-R10 in coreboot v2, except the supper I/O is W83627EHG. Based on the above mentioned points, can I follow the tutorial of IEI IEI PCISA-LX-800-R10 to install the coreboot v2 to PC104 computer? And any hint? Thank you for any input? 1. Does flashrom [1] support your board/system? 2. Do you have a backup plan? For example, can you take out your flash chip? Do you have replacement chips to easily recover? There is some information on this in the Wiki. 3. I do not know about it, but I think if 1. and 2. are resolved you could just build an image and try to boot it and look how far you get. You should have a serial cable to log the output. 4. If I remember correctly it is suggested to run coreboot v3 on Geode systems until the features have been ported back to trunk. Thanks and please correct me, if I wrote nonsense, Paul [1] http://www.flashrom.org/ signature.asc Description: Dies ist ein digital signierter Nachrichtenteil -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH]AMDHT misbehaves on recent compilers
arg, that kind of error is almost embarassing :-) This seems like something that could have easily been caught by static analysis, but I can't find a compiler warning that would have caught it. Could scan-build have caught it (I looked and didn't find it in the output)? Other tools? Thanks, Myles -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH]AMDHT misbehaves on recent compilers
On 1/6/10 10:31 PM, Myles Watson wrote:
arg, that kind of error is almost embarassing :-)
This seems like something that could have easily been caught by static
analysis, but I can't find a compiler warning that would have caught it.
Could scan-build have caught it (I looked and didn't find it in the output)?
Other tools?
scan-build does not catch it (as of r92410)
Here's a simple test case if someone wants to try other tools:
#include stdio.h
const char *func_foo(void)
{
const char *foo=foobar\n;
return foo;
}
int main(void)
{
const char *foo;
foo = func_foo();
printf(%s\n, foo);
return 0;
}
sparse says:
test.c:2:12: warning: symbol 'func_foo' was not declared. Should it be
static?
which could indicate it catches the error, not sure.
Stefan
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Re: [coreboot] [commit] r5000
s...@coreboot.org wrote: Date: 2010-01-06 10:14:08 +0100 (Wed, 06 Jan 2010) Kconfig builds all boards now. Great way to start the new year! :) //Peter -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH]AMDHT misbehaves on recent compilers
On Thu, Jan 07, 2010 at 02:06:18AM +0100, Stefan Reinauer wrote:
Here's a simple test case if someone wants to try other tools:
#include stdio.h
const char *func_foo(void)
{
const char *foo=foobar\n;
I don't think the above is a problem (the pointer foo resides on the
stack, but the string contents do not). The following is a problem:
const char foo[]=foobar\n;
(both the pointer and the array contents are on the stack), and indeed
this does generate a warning from gcc.
Also, had AMD_CB_ManualBUIDSwapList() returned a pointer to swaplist
instead of returning it via a parameter then it too would have
generated a warning.
-Kevin
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Re: [coreboot] [PATCH]more kconfig
On Tue, Jan 05, 2010 at 09:37:21PM +0100, Patrick Georgi wrote: Hi, attached patch makes all boards build with kconfig (incl. fam10). None boot-tested. Nice! I was going to test boot my epia-cn with a kconfig build, but I noticed that auto.c got compiled with gcc instead of romcc. -Kevin -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
