Re: [coreboot] [PATCH] Update LinuxBIOS/coreboot support in memtest86+ 4.0
Knut Kujat escribió: > I haven't tried with a unpatched version of memtest86+ 4.0 and it works > typo!! I meant I HAVE tried memtest86+ 4.0 with a non patched version and vendor BIOS and it worked. > with vendor BIOS. Now with the patched version it halts with coreboot > without error messages (the output you see below is what I see until I > press reset button) and with vendor BIOS its reboots at the same point > (after 2 sec). > > bye and thx, > Knut Kujat. > > Stefan Reinauer escribió: > >> Knut, >> >> are the values the same as with the vendor bios? Do you get any errors >> at all, or does it just hang? >> >> Stefan >> >> On 1/26/10 5:48 PM, Knut Kujat wrote: >> >> >>> I tried it with and without the little patch below ( and of course with >>> the "big" patch) and it freezes after 2 seconds: >>> >>> Memtest86+ v4.00 | Pass 0% >>> AMD K10 (65nm) @ 2000 MHz | Test 3% # >>> L1 Cache: 64K 30303 MB/s | Test #0 [Address test, walking ones] >>> L2 Cache: 512K 10050 MB/s | Testing: 4096M - 6144M 16G >>> L3 Cache: 2048K 5649 MB/s | Pattern: >>> Memory : 16G 1122 MB/s >>> |- >>> Chipset : AMD K10 IMC (ECC : Detect / Correct - Chipkill : Off) >>> Settings: RAM : 333 MHz (DDR667) / CAS : 5-5-5-15 / DDR2 (64 bits) >>> >>> WallTime Cached RsvdMem MemMap Cache ECC Test Pass Errors >>> ECC Errs >>> - -- --- - --- -- >>> >>>0:00:0216G 0Kcoreboot on >>> off Std 0 0 >>> >>> - >>> >>> If you need some more output of whatever just ask me. >>> >>> bye and thx, >>> Knut Kujat >>> >>> >>> >> >> > > > -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] intel 854 chipset support / IP1150
On Mon, 18 Jan 2010 15:26:40 +0100, wrote: > Hi, > > What is the current status/plan for intel 854 chipset based devises? The > reason is, that I have one Tatung STB5000, which looks like IP1150 "copy" > except the CPU is intel 1,4GHz and no CF, but bios chip (SST 47LF008A) is > used. It would be very nice to be able, to build multimedia box based on > linux. > Hello Juraj, Yes, coreboot support for the i854, Thomson IP1150, and Tatung 5000 is coming. Work in progress is going on behind the scenes. Patients is a virtue my friend. I could use some help if your interested... -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] (no subject)
This patch adds e- and f-segment as an available RAM area on the AMD lx-northbridge platforms and fixes FILO compatibility - Allows SeaBios to become resident correctly - Prevents Linux kernel resource problems when booted with FILO and VGA MSR's written - Allows use of the Geode VGA patches Signed-off-by: Edwin Beasant -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Patch: Update Geode LX code to avoid FILO/Kernel problems
This patch adds e- and f-segment as an available RAM area on the AMD lx-northbridge platforms and fixes FILO compatibility - Allows SeaBios to become resident correctly - Prevents Linux kernel resource problems when booted with FILO and VGA MSR's written - Allows use of the Geode VGA patches Signed-off-by: Edwin Beasant geode-lx-fix-filo-linux.patch Description: geode-lx-fix-filo-linux.patch -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Patch: Update Geode LX code to avoid FILO/Kernel problems
- ram_resource(dev, idx++, 768, 1024); // c-f are usable - ram_resource(dev, idx++, 1024, tomk - 1024);// Systop - 1 MB -> KB + //ram_resource(dev, idx++, 768, 1024); // c-f are usable + ram_resource(dev, idx++, 768, tomk - 768); // Systop - 1 MB -> KB Commented out code has proven to be confusing in the past. Any reason for leaving the commented-out line in there? I see it possibly leading to confusion. Could we go from 768 to comething like: 0xc * 65536 or something? Make it really clear that it's the C segment? Rather than commented-out code, maybe a descriptive comment so people who come later can know what you did? The resource code can be inscrutable ... thanks ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Patch: Update Geode LX code to avoid FILO/Kernel problems
Am 27.01.2010 18:26, schrieb ron minnich:
> Could we go from 768 to comething like:
> 0xc * 65536 or something? Make it really clear that it's the C segment?
>
> Rather than commented-out code, maybe a descriptive comment so people
> who come later can know what you did? The resource code can be
> inscrutable ...
>
> thanks
>
> ron
>
Like this? (wrapped and ugly, sorry about that)
Index: src/northbridge/amd/lx/northbridge.c
===
--- src/northbridge/amd/lx/northbridge.c(revision 5057)
+++ src/northbridge/amd/lx/northbridge.c(working copy)
@@ -411,11 +411,11 @@
mc_dev = dev->link[0].children;
if (mc_dev) {
tomk = get_systop() / 1024;
- /* Report the memory regions */
+ /* Report the memory regions
+ All memory up to systop except 0xa-0xb */
idx = 10;
ram_resource(dev, idx++, 0, 640);
- ram_resource(dev, idx++, 768, 1024); // c-f are
usable
- ram_resource(dev, idx++, 1024, tomk - 1024);//
Systop - 1 MB -> KB
+ ram_resource(dev, idx++, 768, tomk - 768); //
Systop - 0xc -> KB
#if CONFIG_WRITE_HIGH_TABLES==1
/* Leave some space for ACPI, PIRQ and MP tables */
--
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Re: [coreboot] Patch: Update Geode LX code to avoid FILO/Kernel problems
That looks great ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] PATCH: Enable Geode GLUI routing for VGA support + TIMER2 calibration
This patch adds the MSR writes that are needed to provide VGA legacy routing for the Geode LX . - Added appropriate Kconfig defines to provide 8mb of VGA ram allocation - Added the Kconfig defines to cover TSC calibration from TIMER2 and UDELAY setup - Two small warning removals about excessive prototyping. Tested against AMD DB800 with both FILO and SeaBios as payloads, and against Debian Testing Installer and Suse SLES 10.1 installed boot. Signed-off-by: Edwin Beasant coreboot-trunk-geode-lx-vga-routing.patch Description: coreboot-trunk-geode-lx-vga-routing.patch -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] PATCH: Enable Geode GLUI routing for VGA support + TIMER2 calibration
Acked-by: Ronald G. Minnich -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r5058 - trunk/src/northbridge/amd/lx
Author: oxygene
Date: 2010-01-27 19:19:33 +0100 (Wed, 27 Jan 2010)
New Revision: 5058
Modified:
trunk/src/northbridge/amd/lx/northbridge.c
Log:
Change memory map of geode lx: 768kb-systop is a
single range.
This change allows both seabios and filo to boot
linux successfully (which was confused before)
Signed-off-by: Edwin Beasant
Signed-off-by: Patrick Georgi
Acked-by: Patrick Georgi
Modified: trunk/src/northbridge/amd/lx/northbridge.c
===
--- trunk/src/northbridge/amd/lx/northbridge.c 2010-01-26 15:34:15 UTC (rev
5057)
+++ trunk/src/northbridge/amd/lx/northbridge.c 2010-01-27 18:19:33 UTC (rev
5058)
@@ -411,11 +411,11 @@
mc_dev = dev->link[0].children;
if (mc_dev) {
tomk = get_systop() / 1024;
- /* Report the memory regions */
+ /* Report the memory regions
+ All memory up to systop except 0xa-0xb */
idx = 10;
ram_resource(dev, idx++, 0, 640);
- ram_resource(dev, idx++, 768, 1024); // c-f are usable
- ram_resource(dev, idx++, 1024, tomk - 1024);// Systop - 1
MB -> KB
+ ram_resource(dev, idx++, 768, tomk - 768); // Systop -
0xc -> KB
#if CONFIG_WRITE_HIGH_TABLES==1
/* Leave some space for ACPI, PIRQ and MP tables */
--
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[coreboot] [commit] r5059 - in trunk/src: northbridge/amd/lx southbridge/amd/cs5536
Author: oxygene
Date: 2010-01-27 20:20:29 +0100 (Wed, 27 Jan 2010)
New Revision: 5059
Modified:
trunk/src/northbridge/amd/lx/Kconfig
trunk/src/northbridge/amd/lx/grphinit.c
trunk/src/northbridge/amd/lx/northbridgeinit.c
trunk/src/southbridge/amd/cs5536/Kconfig
Log:
Add the MSR writes that are needed to provide VGA legacy routing for the Geode
LX
Add appropriate Kconfig defines to provide 8mb of VGA ram allocation
Add the Kconfig defines to cover TSC calibration from TIMER2 and UDELAY setup
Two small warning removals about excessive prototyping.
Signed-off-by: Edwin Beasant
Acked-by: Ronald G. Minnich
Modified: trunk/src/northbridge/amd/lx/Kconfig
===
--- trunk/src/northbridge/amd/lx/Kconfig2010-01-27 18:19:33 UTC (rev
5058)
+++ trunk/src/northbridge/amd/lx/Kconfig2010-01-27 19:20:29 UTC (rev
5059)
@@ -1,4 +1,8 @@
config NORTHBRIDGE_AMD_LX
bool
select HAVE_HIGH_TABLES
-
+
+config VIDEO_MB
+ int
+ default 8
+ depends on NORTHBRIDGE_AMD_LX
Modified: trunk/src/northbridge/amd/lx/grphinit.c
===
--- trunk/src/northbridge/amd/lx/grphinit.c 2010-01-27 18:19:33 UTC (rev
5058)
+++ trunk/src/northbridge/amd/lx/grphinit.c 2010-01-27 19:20:29 UTC (rev
5059)
@@ -22,7 +22,46 @@
#include
#include
#include
+#include
+#include
+#include
+void geodelx_vga_msr_init(void);
+void graphics_init(void);
+
+struct msrinit {
+ u32 msrnum;
+ msr_t msr;
+};
+
+static const struct msrinit geodelx_vga_msr[] = {
+ /* Enable the GLIU Memory routing to the hardware
+ * PDID1 : Port 4, GLIU0
+ * PBASE : 0x000A0
+ * PMASK : 0xFFFE0
+ */
+ {.msrnum = MSR_GLIU0_BASE4, {.lo = 0x0a0fffe0, .hi = 0x8000}},
+ /* Enable the GLIU IO Routing
+ * IDID : Port 4, GLIU0
+ * IBASE : 0x003c0
+ * IMASK : 0x0
+ */
+ {.msrnum = GLIU0_IOD_BM_0, {.lo = 0x3c00, .hi = 0x8000}},
+ /* Enable the GLIU IO Routing
+ * IDID : Port 4, GLIU0
+ * IBASE : 0x003d0
+ * IMASK : 0x0
+ */
+ {.msrnum = GLIU0_IOD_BM_1, {.lo = 0x3d00, .hi = 0x8000}},
+};
+
+void geodelx_vga_msr_init(void)
+{
+ int i;
+ for (i = 0; i < ARRAY_SIZE(geodelx_vga_msr); i++)
+ wrmsr(geodelx_vga_msr[i].msrnum, geodelx_vga_msr[i].msr);
+}
+
/*
* This function mirrors the Graphics_Init routine in GeodeROM.
*/
@@ -32,7 +71,9 @@
/* SoftVG initialization */
printk_debug("Graphics init...\n");
-
+
+ geodelx_vga_msr_init();
+
/* Call SoftVG with the main configuration parameters. */
/* NOTE: SoftVG expects the memory size to be given in 2MB blocks */
Modified: trunk/src/northbridge/amd/lx/northbridgeinit.c
===
--- trunk/src/northbridge/amd/lx/northbridgeinit.c 2010-01-27 18:19:33 UTC
(rev 5058)
+++ trunk/src/northbridge/amd/lx/northbridgeinit.c 2010-01-27 19:20:29 UTC
(rev 5059)
@@ -99,7 +99,6 @@
{0x0, {0x0, 0x0}}, /* END */
};
-extern int sizeram(void);
static void writeglmsr(struct gliutable *gl)
{
@@ -122,7 +121,6 @@
}
}
-extern int sizeram(void);
static void SysmemInit(struct gliutable *gl)
{
msr_t msr;
@@ -749,7 +747,6 @@
/* ***/
void northbridge_init_early(void)
{
- msr_t msr;
int i;
printk_debug("Enter %s\n", __func__);
Modified: trunk/src/southbridge/amd/cs5536/Kconfig
===
--- trunk/src/southbridge/amd/cs5536/Kconfig2010-01-27 18:19:33 UTC (rev
5058)
+++ trunk/src/southbridge/amd/cs5536/Kconfig2010-01-27 19:20:29 UTC (rev
5059)
@@ -20,3 +20,12 @@
config SOUTHBRIDGE_AMD_CS5536
bool
+select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
+
+config UDELAY_TSC
+ bool
+ default y
+ depends on SOUTHBRIDGE_AMD_CS5536
+
+
+
--
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Re: [coreboot] PATCH: Enable Geode GLUI routing for VGA support + TIMER2 calibration
Am 27.01.2010 19:34, schrieb ron minnich: > Acked-by: Ronald G. Minnich Committed with some styleguide fixes, r5059 Thanks, Patrick -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r5060 - trunk/src/southbridge/amd/cs5536
Author: oxygene Date: 2010-01-27 20:55:01 +0100 (Wed, 27 Jan 2010) New Revision: 5060 Modified: trunk/src/southbridge/amd/cs5536/Kconfig Log: reformat Kconfig file, too. Signed-off-by: Patrick Georgi Acked-by: Patrick Georgi Modified: trunk/src/southbridge/amd/cs5536/Kconfig === --- trunk/src/southbridge/amd/cs5536/Kconfig2010-01-27 19:20:29 UTC (rev 5059) +++ trunk/src/southbridge/amd/cs5536/Kconfig2010-01-27 19:55:01 UTC (rev 5060) @@ -19,9 +19,8 @@ config SOUTHBRIDGE_AMD_CS5536 bool + select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 - config UDELAY_TSC bool default y -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [PATCH]getopt support in crossgcc
Hi,
attached patch adds the getopt tool to crossgcc. In case it doesn't
exist in the system (eg. mingw), it's compiled and added to the path.
The getopt implementation is taken from dragonflybsd, thus cleanly
sublicensable to GPL, given that it's 3-clause BSD licensed.
Besides, it's never linked to any other code in our tree.
I wouldn't mind to have some GNU implementation, but I just didn't find
one in my short search.
Signed-off-by: Patrick Georgi
Property changes on: util\crossgcc
___
Added: svn:ignore
+ getopt
getopt.exe
tarballs
xgcc
Index: util/crossgcc/getopt.c
===
--- util/crossgcc/getopt.c (revision 0)
+++ util/crossgcc/getopt.c (revision 0)
@@ -0,0 +1,32 @@
+/* $FreeBSD: src/usr.bin/getopt/getopt.c,v 1.4.2.2 2001/07/30 10:16:38 dd Exp
$ */
+/* $DragonFly: src/usr.bin/getopt/getopt.c,v 1.4 2004/10/23 13:33:36 eirikn
Exp $ */
+
+#include
+#include
+#include
+
+int
+main(int argc, char **argv)
+{
+ int c;
+ int status = 0;
+
+ optind = 2; /* Past the program name and the option letters. */
+ while ((c = getopt(argc, argv, argv[1])) != -1)
+ switch (c) {
+ case '?':
+ status = 1; /* getopt routine gave message */
+ break;
+ default:
+ if (optarg != NULL)
+ printf(" -%c %s", c, optarg);
+ else
+ printf(" -%c", c);
+ break;
+ }
+ printf(" --");
+ for (; optind < argc; optind++)
+ printf(" %s", argv[optind]);
+ printf("\n");
+ return(status);
+}
Index: util/crossgcc/buildgcc
===
--- util/crossgcc/buildgcc (revision 5060)
+++ util/crossgcc/buildgcc (working copy)
@@ -132,6 +132,10 @@
printf "${blue}Welcome to the ${red}coresystems${blue} cross toolchain builder
v$CROSSGCC_VERSION ($CROSSGCC_DATE)${NC}\n\n"
+# Look if we have getopt. If not, build it.
+export PATH=$PATH:.
+getopt - > /dev/null 2>/dev/null || gcc -o getopt getopt.c
+
# parse parameters.. try to find out whether we're running GNU getopt
getoptbrand="`getopt -V`"
if [ "${getoptbrand:0:6}" == "getopt" ]; then
@@ -205,7 +209,7 @@
for patch in patches/${!dir}_*.patch; do
test -r $patch || continue
printf " o `basename $patch`\n"
- patch -s -N -p0 < `echo $patch`
+ $PATCH -s -N -p0 < `echo $patch`
done
)
done
--
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[coreboot] [PATCH]improve support for parallel make in kconfig
Hi, attached patch helps with parallel make (make -j) on Kconfig builds on my system. Basically, $(obj)/build.h is made an explicit dependency of all the various object files, so make doesn't try to build any of these with build.h not around. Also, build.h is atomically generated by writing to some other file, then renaming. I don't say that this "fixes" parallel make, as there might be more issues. Signed-off-by: Patrick Georgi Index: Makefile === --- Makefile(Revision 5060) +++ Makefile(Arbeitskopie) @@ -140,7 +140,7 @@ define c_dsl_template -$(obj)/$(1)%.c: src/$(1)%.dsl +$(obj)/$(1)%.c: src/$(1)%.dsl $(obj)/build.h @printf "IASL $$(subst $$(shell pwd)/,,$$(@))\n" iasl -p $$(basename $$@) -tc $$< perl -pi -e 's/AmlCode/AmlCode_$$(notdir $$(basename $$@))/g' $$(basename $$@).hex @@ -148,31 +148,31 @@ endef define objs_c_template -$(obj)/$(1)%.o: src/$(1)%.c +$(obj)/$(1)%.o: src/$(1)%.c $(obj)/build.h @printf "CC $$(subst $$(obj)/,,$$(@))\n" $(CC) -m32 $$(CFLAGS) -c -o $$@ $$< endef define objs_S_template -$(obj)/$(1)%.o: src/$(1)%.S +$(obj)/$(1)%.o: src/$(1)%.S $(obj)/build.h @printf "CC $$(subst $$(obj)/,,$$(@))\n" $(CC) -m32 -DASSEMBLY $$(CFLAGS) -c -o $$@ $$< endef define initobjs_c_template -$(obj)/$(1)%.o: src/$(1)%.c +$(obj)/$(1)%.o: src/$(1)%.c $(obj)/build.h @printf "CC $$(subst $$(obj)/,,$$(@))\n" $(CC) -m32 $$(CFLAGS) -c -o $$@ $$< endef define initobjs_S_template -$(obj)/$(1)%.o: src/$(1)%.S +$(obj)/$(1)%.o: src/$(1)%.S $(obj)/build.h @printf "CC $$(subst $$(obj)/,,$$(@))\n" $(CC) -m32 -DASSEMBLY $$(CFLAGS) -c -o $$@ $$< endef define drivers_c_template -$(obj)/$(1)%.o: src/$(1)%.c +$(obj)/$(1)%.o: src/$(1)%.c $(obj)/build.h @printf "CC $$(subst $$(obj)/,,$$(@))\n" $(CC) -m32 $$(CFLAGS) -c -o $$@ $$< endef @@ -257,20 +257,24 @@ mkdir -p $(obj)/util/kconfig/lxdialog test -n "$(alldirs)" && mkdir -p $(alldirs) || true -prepare2: +prepare2: $(obj)/build.h + +$(obj)/build.h: @printf "GENbuild.h\n" - printf "#define COREBOOT_VERSION \"$(KERNELVERSION)\"\n" > $(obj)/build.h - printf "#define COREBOOT_EXTRA_VERSION \"$(COREBOOT_EXTRA_VERSION)\"\n" >> $(obj)/build.h - printf "#define COREBOOT_BUILD \"`LANG= date`\"\n" >> $(obj)/build.h - printf "\n" >> $(obj)/build.h - printf "#define COREBOOT_COMPILER \"$(shell LANG= $(CC) --version | head -n1)\"\n" >> $(obj)/build.h - printf "#define COREBOOT_ASSEMBLER \"$(shell LANG= $(AS) --version | head -n1)\"\n" >> $(obj)/build.h - printf "#define COREBOOT_LINKER \"$(shell LANG= $(LD) --version | head -n1)\"\n" >> $(obj)/build.h - printf "#define COREBOOT_COMPILE_TIME \"`LANG= date +%T`\"\n" >> $(obj)/build.h - printf "#define COREBOOT_COMPILE_BY \"$(shell PATH=$$PATH:/usr/ucb whoami)\"\n" >> $(obj)/build.h - printf "#define COREBOOT_COMPILE_HOST \"$(shell hostname)\"\n" >> $(obj)/build.h - printf "#define COREBOOT_COMPILE_DOMAIN \"$(shell test `uname -s` = "Linux" && dnsdomainname || domainname)\"\n" >> $(obj)/build.h - printf "#include \"config.h\"\n" >> $(obj)/build.h + rm -f $(obj)/build.h + printf "#define COREBOOT_VERSION \"$(KERNELVERSION)\"\n" > $(obj)/build.ht + printf "#define COREBOOT_EXTRA_VERSION \"$(COREBOOT_EXTRA_VERSION)\"\n" >> $(obj)/build.ht + printf "#define COREBOOT_BUILD \"`LANG= date`\"\n" >> $(obj)/build.ht + printf "\n" >> $(obj)/build.ht + printf "#define COREBOOT_COMPILER \"$(shell LANG= $(CC) --version | head -n1)\"\n" >> $(obj)/build.ht + printf "#define COREBOOT_ASSEMBLER \"$(shell LANG= $(AS) --version | head -n1)\"\n" >> $(obj)/build.ht + printf "#define COREBOOT_LINKER \"$(shell LANG= $(LD) --version | head -n1)\"\n" >> $(obj)/build.ht + printf "#define COREBOOT_COMPILE_TIME \"`LANG= date +%T`\"\n" >> $(obj)/build.ht + printf "#define COREBOOT_COMPILE_BY \"$(subst \,@,$(shell PATH=$$PATH:/usr/ucb whoami))\"\n" >> $(obj)/build.ht + printf "#define COREBOOT_COMPILE_HOST \"$(shell hostname)\"\n" >> $(obj)/build.ht + printf "#define COREBOOT_COMPILE_DOMAIN \"$(shell test `uname -s` = "Linux" && dnsdomainname || domainname)\"\n" >> $(obj)/build.ht + printf "#include \"config.h\"\n" >> $(obj)/build.ht + mv $(obj)/build.ht $(obj)/build.h doxy: doxygen doxygen: -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH]improve support for parallel make in kconfig
Acked-by: Ronald G. Minnich -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH]getopt support in crossgcc
Acked-by: Ronald G. Minnich -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH]improve support for parallel make in kconfig
Patrick Georgi wrote: > Also, build.h is atomically generated by writing to some other > file, then renaming. > + printf "#define COREBOOT_VERSION \"$(KERNELVERSION)\"\n" > > $(obj)/build.ht > + printf "#define COREBOOT_EXTRA_VERSION \"$(COREBOOT_EXTRA_VERSION)\"\n" > >> $(obj)/build.ht > + printf "#define COREBOOT_BUILD \"`LANG= date`\"\n" >> $(obj)/build.ht > + printf "\n" >> $(obj)/build.ht > + printf "#define COREBOOT_COMPILER \"$(shell LANG= $(CC) --version | > head -n1)\"\n" >> $(obj)/build.ht > + printf "#define COREBOOT_ASSEMBLER \"$(shell LANG= $(AS) --version | > head -n1)\"\n" >> $(obj)/build.ht > + printf "#define COREBOOT_LINKER \"$(shell LANG= $(LD) --version | head > -n1)\"\n" >> $(obj)/build.ht > + printf "#define COREBOOT_COMPILE_TIME \"`LANG= date +%T`\"\n" >> > $(obj)/build.ht > + printf "#define COREBOOT_COMPILE_BY \"$(subst \,@,$(shell > PATH=$$PATH:/usr/ucb whoami))\"\n" >> $(obj)/build.ht > + printf "#define COREBOOT_COMPILE_HOST \"$(shell hostname)\"\n" >> > $(obj)/build.ht > + printf "#define COREBOOT_COMPILE_DOMAIN \"$(shell test `uname -s` = > "Linux" && dnsdomainname || domainname)\"\n" >> $(obj)/build.ht > + printf "#include \"config.h\"\n" >> $(obj)/build.ht > + mv $(obj)/build.ht $(obj)/build.h Is build.h strictly neccessary for the build? If yes, why? //Peter -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
