Re: [coreboot] [PATCH] CAR on Intel P6 Series - Support for model_6bx
Dear Joseph,
Am Donnerstag, den 08.04.2010, 02:09 -0400 schrieb Joseph Smith:
1. This patch adds CAR for Intel P6 series processors.
2. Add support for Micro-FCBGA 479 Celeron and PIII's
3. Add support for model_6bx and microcode updates
4. Add support for CAR and Tinybootblock on RCA RM4100 and Thomson IP1000
sorry for my dump question. Does supporting CAR have any practical
improvements besides going with coreboot features(?). For example did
boot time improve?
Build and boot tested (bootlog attached).
It says »Boot failed.« at the end. But that is due to the payload, is
not it?
Anyway, I just spotted one indentation error. Someone knowledgeable has
to do the review. Sorry!
[…]
Index: src/cpu/intel/model_6bx/cache_as_ram_disable.c
===
--- src/cpu/intel/model_6bx/cache_as_ram_disable.c (revision 0)
+++ src/cpu/intel/model_6bx/cache_as_ram_disable.c (revision 0)
@@ -0,0 +1,89 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include cpu/x86/car/copy_and_run.c
+
+/* called from assembler code */
+void stage1_main(unsigned long bist);
+
+/* from romstage.c */
+void real_main(unsigned long bist);
+
+void stage1_main(unsigned long bist)
+{
+ unsigned int cpu_reset = 0;
+
+ real_main(bist);
+
+ /* No servicable parts below this line .. */
+#ifdef CAR_DEBUG
+/* Check value of esp to verify if we have enough rom for
stack in Cache as RAM */
+ unsigned v_esp;
+ __asm__ volatile (
+ movl %%esp, %0\n
+ : =a (v_esp)
+ );
+ printk(BIOS_SPEW, v_esp=%08x\n, v_esp);
+#endif
+
+printk(BIOS_SPEW, cpu_reset = %08x\n, cpu_reset);
+ printk(BIOS_SPEW, No cache as ram now - );
This indentation looks different. I do not know if it is just my MUA.
[…]
Thanks for your work,
Paul
[1] http://www.coreboot.org/images/6/6c/LBCar.pdf
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[coreboot] build service results for r5373
Dear coreboot readers! This is the automatic build system of coreboot. The developer oxygene checked in revision 5373 to the coreboot repository. This caused the following changes: Change Log: Replace sconfig with a C implementation. (smaller, faster, standard parser generator, no more python) Provide precompiled parser, so bison and flex are optional dependencies. Adapt Makefile and abuild (which uses some sconfig file as a magic path) to match. Drop python as dependency from README, and add bison and flex as optional dependencies Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de Acked-by: Stefan Reinauer ste...@coresystems.de Acked-by: Ronald G. Minnich rminn...@gmail.com Build Log: Compilation of asi:mb_5blgp has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5373device=mb_5blgpvendor=asinum=2 Compilation of digitallogic:adl855pc has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5373device=adl855pcvendor=digitallogicnum=2 Compilation of kontron:kt690 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5373device=kt690vendor=kontronnum=2 Compilation of tyan:s2850 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5373device=s2850vendor=tyannum=2 Compilation of tyan:s2881 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5373device=s2881vendor=tyannum=2 If something broke during this checkin please be a pain in oxygene's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r5374 - in trunk: src/mainboard/digitallogic/adl855pc util/sconfig
Author: oxygene Date: Thu Apr 8 14:00:35 2010 New Revision: 5374 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5374 Log: Remove duplicate registers in digitallogic/adl855pc's device tree Create directories before trying to copy files into them Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de Acked-by: Patrick Georgi patrick.geo...@coresystems.de Modified: trunk/src/mainboard/digitallogic/adl855pc/devicetree.cb trunk/util/sconfig/Makefile.inc Modified: trunk/src/mainboard/digitallogic/adl855pc/devicetree.cb == --- trunk/src/mainboard/digitallogic/adl855pc/devicetree.cb Thu Apr 8 13:37:43 2010(r5373) +++ trunk/src/mainboard/digitallogic/adl855pc/devicetree.cb Thu Apr 8 14:00:35 2010(r5374) @@ -13,8 +13,6 @@ # pci 12.0 on end register enable_usb = 0 register enable_native_ide = 0 - register enable_usb = 0 - register enable_native_ide = 0 chip superio/winbond/w83627hf # link 1 device pnp 2e.0 on # Floppy io 0x60 = 0x3f0 Modified: trunk/util/sconfig/Makefile.inc == --- trunk/util/sconfig/Makefile.inc Thu Apr 8 13:37:43 2010(r5373) +++ trunk/util/sconfig/Makefile.inc Thu Apr 8 14:00:35 2010(r5374) @@ -23,6 +23,7 @@ $(obj)/util/sconfig/lex.yy.o: $(obj)/util/sconfig/sconfig.tab.h $(obj)/util/sconfig/%: $(top)/util/sconfig/%_shipped + mkdir -p $(dir $@) cp $ $@ $(obj)/util/sconfig/sconfig: $(obj)/util/sconfig $(addprefix $(obj)/util/sconfig/,$(sconfigobj)) -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] CAR on Intel P6 Series - Support for model_6bx
On 04/08/2010 02:36 AM, Paul Menzel wrote:
Dear Joseph,
Am Donnerstag, den 08.04.2010, 02:09 -0400 schrieb Joseph Smith:
1. This patch adds CAR for Intel P6 series processors.
2. Add support for Micro-FCBGA 479 Celeron and PIII's
3. Add support for model_6bx and microcode updates
4. Add support for CAR and Tinybootblock on RCA RM4100 and Thomson IP1000
sorry for my dump question. Does supporting CAR have any practical
improvements besides going with coreboot features(?). For example did
boot time improve?
Yes it seems to boot alot faster :-)
Build and boot tested (bootlog attached).
It says »Boot failed.« at the end. But that is due to the payload, is
not it?
Yes that log was without a payload.
Anyway, I just spotted one indentation error. Someone knowledgeable has
to do the review. Sorry!
[…]
Index: src/cpu/intel/model_6bx/cache_as_ram_disable.c
===
--- src/cpu/intel/model_6bx/cache_as_ram_disable.c (revision 0)
+++ src/cpu/intel/model_6bx/cache_as_ram_disable.c (revision 0)
@@ -0,0 +1,89 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include cpu/x86/car/copy_and_run.c
+
+/* called from assembler code */
+void stage1_main(unsigned long bist);
+
+/* from romstage.c */
+void real_main(unsigned long bist);
+
+void stage1_main(unsigned long bist)
+{
+ unsigned int cpu_reset = 0;
+
+ real_main(bist);
+
+ /* No servicable parts below this line .. */
+#ifdef CAR_DEBUG
+/* Check value of esp to verify if we have enough rom for
stack in Cache as RAM */
+ unsigned v_esp;
+ __asm__ volatile (
+ movl %%esp, %0\n
+ : =a (v_esp)
+ );
+ printk(BIOS_SPEW, v_esp=%08x\n, v_esp);
+#endif
+
+printk(BIOS_SPEW, cpu_reset = %08x\n, cpu_reset);
+ printk(BIOS_SPEW, No cache as ram now - );
This indentation looks different. I do not know if it is just my MUA.
ah thanks.
--
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org
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[coreboot] build service results for r5374
Dear coreboot readers! This is the automatic build system of coreboot. The developer oxygene checked in revision 5374 to the coreboot repository. This caused the following changes: Change Log: Remove duplicate registers in digitallogic/adl855pc's device tree Create directories before trying to copy files into them Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de Acked-by: Patrick Georgi patrick.geo...@coresystems.de Build Log: Compilation of asi:mb_5blgp has been fixed Compilation of digitallogic:adl855pc has been fixed Compilation of kontron:kt690 has been fixed Compilation of tyan:s2850 has been fixed Compilation of tyan:s2881 has been fixed If something broke during this checkin please be a pain in oxygene's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r5375 - trunk/util/sconfig
Author: oxygene
Date: Thu Apr 8 14:46:18 2010
New Revision: 5375
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5375
Log:
sconfig: Mangle - to _ for struct names, too.
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
Acked-by: Patrick Georgi patrick.geo...@coresystems.de
Modified:
trunk/util/sconfig/sconfig.tab.c_shipped
trunk/util/sconfig/sconfig.y
Modified: trunk/util/sconfig/sconfig.tab.c_shipped
==
--- trunk/util/sconfig/sconfig.tab.c_shippedThu Apr 8 14:00:35 2010
(r5374)
+++ trunk/util/sconfig/sconfig.tab.c_shippedThu Apr 8 14:46:18 2010
(r5375)
@@ -562,7 +562,7 @@
static const yytype_uint16 yyrline[] =
{
0, 132, 132, 152, 152, 154, 154, 154, 156, 156,
- 156, 158, 158, 214, 214, 293, 311
+ 156, 158, 158, 215, 215, 294, 312
};
#endif
@@ -1511,6 +1511,7 @@
char *c;
for (c = (yyval.device)-name_underscore; *c; c++) {
if (*c == '/') *c = '_';
+ if (*c == '-') *c = '_';
}
(yyval.device)-type = chip;
(yyval.device)-chip = (yyval.device);
@@ -1536,7 +1537,7 @@
case 12:
/* Line 1455 of yacc.c */
-#line 186 /home/Patrick/work/coreboot/util/sconfig/sconfig.y
+#line 187 /home/Patrick/work/coreboot/util/sconfig/sconfig.y
{
cur_parent = (yyvsp[(3) - (5)].device)-parent;
@@ -1569,7 +1570,7 @@
case 13:
/* Line 1455 of yacc.c */
-#line 214 /home/Patrick/work/coreboot/util/sconfig/sconfig.y
+#line 215 /home/Patrick/work/coreboot/util/sconfig/sconfig.y
{
(yyval.device) = new_dev();
(yyval.device)-bustype = (yyvsp[(2) - (4)].number);
@@ -1625,7 +1626,7 @@
case 14:
/* Line 1455 of yacc.c */
-#line 264 /home/Patrick/work/coreboot/util/sconfig/sconfig.y
+#line 265 /home/Patrick/work/coreboot/util/sconfig/sconfig.y
{
cur_parent = (yyvsp[(5) - (7)].device)-parent;
cur_bus = (yyvsp[(5) - (7)].device)-bus;
@@ -1659,7 +1660,7 @@
case 15:
/* Line 1455 of yacc.c */
-#line 294 /home/Patrick/work/coreboot/util/sconfig/sconfig.y
+#line 295 /home/Patrick/work/coreboot/util/sconfig/sconfig.y
{
struct resource *r = malloc(sizeof(struct resource));
memset (r, 0, sizeof(struct resource));
@@ -1680,7 +1681,7 @@
case 16:
/* Line 1455 of yacc.c */
-#line 312 /home/Patrick/work/coreboot/util/sconfig/sconfig.y
+#line 313 /home/Patrick/work/coreboot/util/sconfig/sconfig.y
{
struct reg *r = malloc(sizeof(struct reg));
memset (r, 0, sizeof(struct reg));
@@ -1711,7 +1712,7 @@
/* Line 1455 of yacc.c */
-#line 1715 /home/Patrick/work/coreboot/util/sconfig/sconfig.tab.c_shipped
+#line 1716 /home/Patrick/work/coreboot/util/sconfig/sconfig.tab.c_shipped
default: break;
}
YY_SYMBOL_PRINT (- $$ =, yyr1[yyn], yyval, yyloc);
@@ -1923,7 +1924,7 @@
/* Line 1675 of yacc.c */
-#line 339 /home/Patrick/work/coreboot/util/sconfig/sconfig.y
+#line 340 /home/Patrick/work/coreboot/util/sconfig/sconfig.y
void pass0(FILE *fil, struct device *ptr) {
if ((ptr-type == device) (ptr-id != 0) (!ptr-used))
Modified: trunk/util/sconfig/sconfig.y
==
--- trunk/util/sconfig/sconfig.yThu Apr 8 14:00:35 2010(r5374)
+++ trunk/util/sconfig/sconfig.yThu Apr 8 14:46:18 2010(r5375)
@@ -163,6 +163,7 @@
char *c;
for (c = $device$-name_underscore; *c; c++) {
if (*c == '/') *c = '_';
+ if (*c == '-') *c = '_';
}
$device$-type = chip;
$device$-chip = $device$;
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[coreboot] [commit] r5376 - trunk/src/mainboard/emulation/qemu-x86
Author: oxygene
Date: Thu Apr 8 14:47:35 2010
New Revision: 5376
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5376
Log:
cpu/emulation/qemu-x86 doesn't exist anymore, as this
is folded into mainboard/emulation/qemu-x86. Adapt code.
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
Acked-by: Stefan Reinauer ste...@coresystems.de
Modified:
trunk/src/mainboard/emulation/qemu-x86/chip.h
trunk/src/mainboard/emulation/qemu-x86/devicetree.cb
trunk/src/mainboard/emulation/qemu-x86/northbridge.c
Modified: trunk/src/mainboard/emulation/qemu-x86/chip.h
==
--- trunk/src/mainboard/emulation/qemu-x86/chip.h Thu Apr 8 14:46:18
2010(r5375)
+++ trunk/src/mainboard/emulation/qemu-x86/chip.h Thu Apr 8 14:47:35
2010(r5376)
@@ -3,9 +3,9 @@
struct mainboard_config {
};
-struct cpu_emulation_qemu_x86_config
+struct mainboard_emulation_qemu_x86_config
{
};
-extern struct chip_operations cpu_emulation_qemu_x86_ops;
+extern struct chip_operations mainboard_emulation_qemu_x86_ops;
Modified: trunk/src/mainboard/emulation/qemu-x86/devicetree.cb
==
--- trunk/src/mainboard/emulation/qemu-x86/devicetree.cbThu Apr 8
14:46:18 2010(r5375)
+++ trunk/src/mainboard/emulation/qemu-x86/devicetree.cbThu Apr 8
14:47:35 2010(r5376)
@@ -1,4 +1,4 @@
-chip cpu/emulation/qemu-x86
+chip mainboard/emulation/qemu-x86
device pci_domain 0 on
device pci 0.0 on end
Modified: trunk/src/mainboard/emulation/qemu-x86/northbridge.c
==
--- trunk/src/mainboard/emulation/qemu-x86/northbridge.cThu Apr 8
14:46:18 2010(r5375)
+++ trunk/src/mainboard/emulation/qemu-x86/northbridge.cThu Apr 8
14:47:35 2010(r5376)
@@ -152,7 +152,7 @@
}
}
-struct chip_operations cpu_emulation_qemu_x86_ops = {
+struct chip_operations mainboard_emulation_qemu_x86_ops = {
CHIP_NAME(QEMU Northbridge)
.enable_dev = enable_dev,
};
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[coreboot] [commit] r5377 - trunk/util/sconfig
Author: oxygene
Date: Thu Apr 8 14:59:41 2010
New Revision: 5377
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5377
Log:
Remove #line statements in processed parser source,
to avoid clutter in revision history.
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
Acked-by: Patrick Georgi patrick.geo...@coresystems.de
Modified:
trunk/util/sconfig/Makefile.inc
trunk/util/sconfig/lex.yy.c_shipped
trunk/util/sconfig/sconfig.tab.c_shipped
trunk/util/sconfig/sconfig.tab.h_shipped
Modified: trunk/util/sconfig/Makefile.inc
==
--- trunk/util/sconfig/Makefile.inc Thu Apr 8 14:47:35 2010(r5376)
+++ trunk/util/sconfig/Makefile.inc Thu Apr 8 14:59:41 2010(r5377)
@@ -11,12 +11,12 @@
ifdef SCONFIG_GENPARSER
$(top)/util/sconfig/lex.yy.c_shipped: $(top)/util/sconfig/sconfig.l
- flex -o $@ $
+ flex -L -o $@ $
# the .c rule also creates .h
$(top)/util/sconfig/sconfig.tab.h_shipped:
$(top)/util/sconfig/sconfig.tab.c_shipped
$(top)/util/sconfig/sconfig.tab.c_shipped: $(top)/util/sconfig/sconfig.y
- bison --defines=$(top)/util/sconfig/sconfig.tab.h_shipped -o $@ $
+ bison -l --defines=$(top)/util/sconfig/sconfig.tab.h_shipped -o $@ $
endif
Modified: trunk/util/sconfig/lex.yy.c_shipped
==
--- trunk/util/sconfig/lex.yy.c_shipped Thu Apr 8 14:47:35 2010(r5376)
+++ trunk/util/sconfig/lex.yy.c_shipped Thu Apr 8 14:59:41 2010(r5377)
@@ -1,6 +1,5 @@
-#line 2 /home/Patrick/work/coreboot/util/sconfig/lex.yy.c_shipped
-#line 4 /home/Patrick/work/coreboot/util/sconfig/lex.yy.c_shipped
+#line 3 /home/Patrick/work/coreboot/util/sconfig/lex.yy.c_shipped
#define YY_INT_ALIGNED short int
@@ -508,8 +507,6 @@
#define YY_MORE_ADJ 0
#define YY_RESTORE_YY_MORE_OFFSET
char *yytext;
-#line 1 /home/Patrick/work/coreboot/util/sconfig/sconfig.l
-#line 2 /home/Patrick/work/coreboot/util/sconfig/sconfig.l
/*
* sconfig, coreboot device tree compiler
*
@@ -533,7 +530,6 @@
#include sconfig.tab.h
int linenum = 0;
-#line 537 /home/Patrick/work/coreboot/util/sconfig/lex.yy.c_shipped
#define INITIAL 0
@@ -715,10 +711,6 @@
register char *yy_cp, *yy_bp;
register int yy_act;
-#line 27 /home/Patrick/work/coreboot/util/sconfig/sconfig.l
-
-#line 721 /home/Patrick/work/coreboot/util/sconfig/lex.yy.c_shipped
-
if ( !(yy_init) )
{
(yy_init) = 1;
@@ -802,133 +794,107 @@
case 1:
YY_RULE_SETUP
-#line 28 /home/Patrick/work/coreboot/util/sconfig/sconfig.l
{}
YY_BREAK
case 2:
/* rule 2 can match eol */
YY_RULE_SETUP
-#line 29 /home/Patrick/work/coreboot/util/sconfig/sconfig.l
{linenum++;}
YY_BREAK
case 3:
/* rule 3 can match eol */
YY_RULE_SETUP
-#line 30 /home/Patrick/work/coreboot/util/sconfig/sconfig.l
{linenum++;}
YY_BREAK
case 4:
YY_RULE_SETUP
-#line 31 /home/Patrick/work/coreboot/util/sconfig/sconfig.l
{return(CHIP);}
YY_BREAK
case 5:
YY_RULE_SETUP
-#line 32 /home/Patrick/work/coreboot/util/sconfig/sconfig.l
{return(DEVICE);}
YY_BREAK
case 6:
YY_RULE_SETUP
-#line 33 /home/Patrick/work/coreboot/util/sconfig/sconfig.l
{return(REGISTER);}
YY_BREAK
case 7:
YY_RULE_SETUP
-#line 34 /home/Patrick/work/coreboot/util/sconfig/sconfig.l
{yylval.number=1; return(BOOL);}
YY_BREAK
case 8:
YY_RULE_SETUP
-#line 35 /home/Patrick/work/coreboot/util/sconfig/sconfig.l
{yylval.number=0; return(BOOL);}
YY_BREAK
case 9:
YY_RULE_SETUP
-#line 36 /home/Patrick/work/coreboot/util/sconfig/sconfig.l
{yylval.number=PCI; return(BUS);}
YY_BREAK
case 10:
YY_RULE_SETUP
-#line 37 /home/Patrick/work/coreboot/util/sconfig/sconfig.l
{yylval.number=PNP; return(BUS);}
YY_BREAK
case 11:
YY_RULE_SETUP
-#line 38 /home/Patrick/work/coreboot/util/sconfig/sconfig.l
{yylval.number=I2C; return(BUS);}
YY_BREAK
case 12:
YY_RULE_SETUP
-#line 39 /home/Patrick/work/coreboot/util/sconfig/sconfig.l
{yylval.number=APIC; return(BUS);}
YY_BREAK
case 13:
YY_RULE_SETUP
-#line 40 /home/Patrick/work/coreboot/util/sconfig/sconfig.l
{yylval.number=APIC_CLUSTER; return(BUS);}
YY_BREAK
case 14:
YY_RULE_SETUP
-#line 41 /home/Patrick/work/coreboot/util/sconfig/sconfig.l
{yylval.number=PCI_DOMAIN; return(BUS);}
YY_BREAK
case 15:
YY_RULE_SETUP
-#line 42 /home/Patrick/work/coreboot/util/sconfig/sconfig.l
{yylval.number=IRQ; return(RESOURCE);}
YY_BREAK
case 16:
YY_RULE_SETUP
-#line 43 /home/Patrick/work/coreboot/util/sconfig/sconfig.l
{yylval.number=DRQ; return(RESOURCE);}
YY_BREAK
case 17:
YY_RULE_SETUP
-#line 44 /home/Patrick/work/coreboot/util/sconfig/sconfig.l
{yylval.number=IO; return(RESOURCE);}
YY_BREAK
case 18:
YY_RULE_SETUP
-#line 45 /home/Patrick/work/coreboot/util/sconfig/sconfig.l
[coreboot] [commit] r5378 - in trunk: . util/sconfig
Author: stepan Date: Thu Apr 8 15:16:32 2010 New Revision: 5378 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5378 Log: output cosmetics Signed-off-by: Stefan Reinauer ste...@coresystems.de Acked-by: Stefan Reinauer ste...@coresystems.de Modified: trunk/Makefile trunk/util/sconfig/Makefile.inc Modified: trunk/Makefile == --- trunk/Makefile Thu Apr 8 14:59:41 2010(r5377) +++ trunk/Makefile Thu Apr 8 15:16:32 2010(r5378) @@ -150,6 +150,7 @@ # needed objects that every mainboard uses # Creation of these is architecture and mainboard independent $(obj)/mainboard/$(MAINBOARDDIR)/static.c: $(src)/mainboard/$(MAINBOARDDIR)/devicetree.cb $(obj)/util/sconfig/sconfig + @printf SCONFIG$(subst $(src)/,,$())\n mkdir -p $(obj)/mainboard/$(MAINBOARDDIR) $(obj)/util/sconfig/sconfig $(MAINBOARDDIR) $(obj)/mainboard/$(MAINBOARDDIR) Modified: trunk/util/sconfig/Makefile.inc == --- trunk/util/sconfig/Makefile.inc Thu Apr 8 14:59:41 2010(r5377) +++ trunk/util/sconfig/Makefile.inc Thu Apr 8 15:16:32 2010(r5378) @@ -27,5 +27,5 @@ cp $ $@ $(obj)/util/sconfig/sconfig: $(obj)/util/sconfig $(addprefix $(obj)/util/sconfig/,$(sconfigobj)) - printf HOSTCXX$(subst $(obj)/,,$(@)) (link)\n - $(HOSTCXX) $(SCONFIGFLAGS) -o $@ $(addprefix $(obj)/util/sconfig/,$(sconfigobj)) + printf HOSTCC $(subst $(obj)/,,$(@)) (link)\n + $(HOSTCC) $(SCONFIGFLAGS) -o $@ $(addprefix $(obj)/util/sconfig/,$(sconfigobj)) -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] build service results for r5377
Dear coreboot readers! This is the automatic build system of coreboot. The developer oxygene checked in revision 5377 to the coreboot repository. This caused the following changes: Change Log: Remove #line statements in processed parser source, to avoid clutter in revision history. Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de Acked-by: Patrick Georgi patrick.geo...@coresystems.de Build Log: Compilation of amd:norwich has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5377device=norwichvendor=amdnum=2 If something broke during this checkin please be a pain in oxygene's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] build service results for r5378
Dear coreboot readers! This is the automatic build system of coreboot. The developer stepan checked in revision 5378 to the coreboot repository. This caused the following changes: Change Log: output cosmetics Signed-off-by: Stefan Reinauer ste...@coresystems.de Acked-by: Stefan Reinauer ste...@coresystems.de Build Log: Compilation of amd:norwich has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r5379 - in trunk/src: . northbridge/amd northbridge/amd/amdht
Author: myles Date: Thu Apr 8 17:02:39 2010 New Revision: 5379 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5379 Log: Move Kconfig for HT limits to northbridge/amd/Kconfig. Guard the code with CONFIG_EXPERT to remove warnings. Make it only show up for fam10, since it isn't implemented for K8 yet. Signed-off-by: Myles Watson myle...@gmail.com Acked-by: Myles Watson myle...@gmail.com Modified: trunk/src/Kconfig trunk/src/northbridge/amd/Kconfig trunk/src/northbridge/amd/amdht/h3finit.c Modified: trunk/src/Kconfig == --- trunk/src/Kconfig Thu Apr 8 15:16:32 2010(r5378) +++ trunk/src/Kconfig Thu Apr 8 17:02:39 2010(r5379) @@ -90,96 +90,6 @@ comment CPU source src/cpu/Kconfig comment Northbridge - -menu HyperTransport setup - depends on (NORTHBRIDGE_AMD_AMDK8 || NORTHBRIDGE_AMD_AMDFAM10) EXPERT - -choice - prompt HyperTransport frequency - default LIMIT_HT_SPEED_AUTO - help - This option sets the maximum permissible HyperTransport link - frequency. - - Use of this option will only limit the autodetected HT frequency. - It will not (and cannot) increase the frequency beyond the - autodetected limits. - - This is primarily used to work around poorly designed or laid out - HT traces on certain motherboards. - -config LIMIT_HT_SPEED_200 - bool Limit HT frequency to 200MHz -config LIMIT_HT_SPEED_400 - bool Limit HT frequency to 400MHz -config LIMIT_HT_SPEED_600 - bool Limit HT frequency to 600MHz -config LIMIT_HT_SPEED_800 - bool Limit HT frequency to 800MHz -config LIMIT_HT_SPEED_1000 - bool Limit HT frequency to 1.0GHz -config LIMIT_HT_SPEED_1200 - bool Limit HT frequency to 1.2GHz -config LIMIT_HT_SPEED_1400 - bool Limit HT frequency to 1.4GHz -config LIMIT_HT_SPEED_1600 - bool Limit HT frequency to 1.6GHz -config LIMIT_HT_SPEED_1800 - bool Limit HT frequency to 1.8GHz -config LIMIT_HT_SPEED_2000 - bool Limit HT frequency to 2.0GHz -config LIMIT_HT_SPEED_2200 - bool Limit HT frequency to 2.2GHz -config LIMIT_HT_SPEED_2400 - bool Limit HT frequency to 2.4GHz -config LIMIT_HT_SPEED_2600 - bool Limit HT frequency to 2.6GHz -config LIMIT_HT_SPEED_AUTO - bool Autodetect HT frequency -endchoice - -choice - prompt HyperTransport downlink width - default LIMIT_HT_DOWN_WIDTH_16 - help - This option sets the maximum permissible HyperTransport - downlink width. - - Use of this option will only limit the autodetected HT width. - It will not (and cannot) increase the width beyond the autodetected - limits. - - This is primarily used to work around poorly designed or laid out HT - traces on certain motherboards. - -config LIMIT_HT_DOWN_WIDTH_8 - bool 8 bits -config LIMIT_HT_DOWN_WIDTH_16 - bool 16 bits -endchoice - -choice - prompt HyperTransport uplink width - default LIMIT_HT_UP_WIDTH_16 - help - This option sets the maximum permissible HyperTransport - uplink width. - - Use of this option will only limit the autodetected HT width. - It will not (and cannot) increase the width beyond the autodetected - limits. - - This is primarily used to work around poorly designed or laid out HT - traces on certain motherboards. - -config LIMIT_HT_UP_WIDTH_8 - bool 8 bits -config LIMIT_HT_UP_WIDTH_16 - bool 16 bits -endchoice - -endmenu - source src/northbridge/Kconfig comment Southbridge source src/southbridge/Kconfig Modified: trunk/src/northbridge/amd/Kconfig == --- trunk/src/northbridge/amd/Kconfig Thu Apr 8 15:16:32 2010(r5378) +++ trunk/src/northbridge/amd/Kconfig Thu Apr 8 17:02:39 2010(r5379) @@ -3,3 +3,92 @@ source src/northbridge/amd/gx2/Kconfig source src/northbridge/amd/amdfam10/Kconfig source src/northbridge/amd/lx/Kconfig +menu HyperTransport setup + #could be implemented for K8 (NORTHBRIDGE_AMD_AMDK8) + depends on (NORTHBRIDGE_AMD_AMDFAM10) EXPERT + +choice + prompt HyperTransport frequency + default LIMIT_HT_SPEED_AUTO + help + This option sets the maximum permissible HyperTransport link + frequency. + + Use of this option will only limit the autodetected HT frequency. + It will not (and cannot) increase the frequency beyond the + autodetected limits. + + This is primarily used to work around poorly designed or laid out + HT traces on certain motherboards. + +config LIMIT_HT_SPEED_200 + bool Limit HT frequency to 200MHz +config LIMIT_HT_SPEED_400 + bool Limit HT frequency to 400MHz +config LIMIT_HT_SPEED_600 + bool Limit HT frequency to 600MHz +config
[coreboot] [commit] r5382 - in trunk/src: cpu/amd/model_10xxx cpu/amd/model_fxx include/cpu/amd northbridge/amd/amdfam10 northbridge/amd/amdmct/mct
Author: myles
Date: Thu Apr 8 17:12:18 2010
New Revision: 5382
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5382
Log:
Cosmetically make init_cpus more similar for fam10 and K8.
Remove some fam10 warnings.
Signed-off-by: Myles Watson myle...@gmail.com
Acked-by: Myles Watson myle...@gmail.com
Modified:
trunk/src/cpu/amd/model_10xxx/init_cpus.c
trunk/src/cpu/amd/model_10xxx/model_10xxx_init.c
trunk/src/cpu/amd/model_fxx/init_cpus.c
trunk/src/include/cpu/amd/model_10xxx_msr.h
trunk/src/include/cpu/amd/model_fxx_rev.h
trunk/src/northbridge/amd/amdfam10/northbridge.c
trunk/src/northbridge/amd/amdfam10/raminit_amdmct.c
trunk/src/northbridge/amd/amdmct/mct/mct_d.h
trunk/src/northbridge/amd/amdmct/mct/mctdqs_d.c
trunk/src/northbridge/amd/amdmct/mct/mctpro_d.c
trunk/src/northbridge/amd/amdmct/mct/mctsrc.c
Modified: trunk/src/cpu/amd/model_10xxx/init_cpus.c
==
--- trunk/src/cpu/amd/model_10xxx/init_cpus.c Thu Apr 8 17:09:53 2010
(r5381)
+++ trunk/src/cpu/amd/model_10xxx/init_cpus.c Thu Apr 8 17:12:18 2010
(r5382)
@@ -26,33 +26,10 @@
#ifndef SET_FIDVID_CORE0_ONLY
/* MSR FIDVID_CTL and FIDVID_STATUS are shared by cores,
- Need to do every AP to set common FID/VID*/
+ Need to do every AP to set common FID/VID */
#define SET_FIDVID_CORE0_ONLY 0
#endif
-static void print_initcpu8 (const char *strval, u8 val)
-{
- printk(BIOS_DEBUG, %s%02x\n, strval, val);
-}
-
-static void print_initcpu8_nocr (const char *strval, u8 val)
-{
- printk(BIOS_DEBUG, %s%02x, strval, val);
-}
-
-
-static void print_initcpu16 (const char *strval, u16 val)
-{
- printk(BIOS_DEBUG, %s%04x\n, strval, val);
-}
-
-
-static void print_initcpu(const char *strval, u32 val)
-{
- printk(BIOS_DEBUG, %s%08x\n, strval, val);
-}
-
-
void update_microcode(u32 cpu_deviceid);
static void prep_fid_change(void);
static void init_fidvid_stage2(u32 apicid, u32 nodeid);
@@ -65,14 +42,13 @@
msr_t msr;
msr = rdmsr(NB_CFG_MSR);
// EnableCf8ExtCfg: We need that to access CONFIG_PCI_IO_CFG_EXT 4K
range
- msr.hi |= (1(46-32));
+ msr.hi |= (1 (46 - 32));
wrmsr(NB_CFG_MSR, msr);
}
#else
static void set_EnableCf8ExtCfg(void) { }
#endif
-
/*[39:8] */
#define PCI_MMIO_BASE 0xfe00
/* because we will use gs to store hi, so need to make sure lo can start
@@ -85,34 +61,31 @@
msr = rdmsr(0xc0010058);
msr.lo = ~(0xfff0 | (0xf 2));
// 256 bus per segment, MMIO reg will be 4G , enable MMIO Config space
- msr.lo |= ((8+CONFIG_PCI_BUS_SEGN_BITS) 2) | (1 0);
+ msr.lo |= ((8 + CONFIG_PCI_BUS_SEGN_BITS) 2) | (1 0);
msr.hi = ~(0x);
- msr.hi |= (PCI_MMIO_BASE (32-8));
- wrmsr(0xc0010058, msr); // MMIO Config Base Address Reg
+ msr.hi |= (PCI_MMIO_BASE (32 - 8));
+ wrmsr(0xc0010058, msr); // MMIO Config Base Address Reg
//mtrr for that range?
// set_var_mtrr_x(7, PCI_MMIO_BASE8, PCI_MMIO_BASE(32-8),
0x, 0x01, MTRR_TYPE_UNCACHEABLE);
set_wrap32dis();
- msr.hi = (PCI_MMIO_BASE (32-8));
+ msr.hi = (PCI_MMIO_BASE (32 - 8));
msr.lo = 0;
- wrmsr(0xc101, msr); //GS_Base Reg
-
-
+ wrmsr(0xc101, msr); //GS_Base Reg
#endif
}
-
-typedef void (*process_ap_t)(u32 apicid, void *gp);
+typedef void (*process_ap_t) (u32 apicid, void *gp);
//core_range = 0 : all cores
//core range = 1 : core 0 only
//core range = 2 : cores other than core0
-static void for_each_ap(u32 bsp_apicid, u32 core_range,
- process_ap_t process_ap, void *gp)
+static void for_each_ap(u32 bsp_apicid, u32 core_range, process_ap_t
process_ap,
+ void *gp)
{
// here assume the OS don't change our apicid
u32 ap_apicid;
@@ -122,7 +95,7 @@
u32 disable_siblings;
u32 cores_found;
u32 nb_cfg_54;
- int i,j;
+ int i, j;
u32 ApicIdCoreIdSize;
/* get_nodes define in ht_wrapper.c */
@@ -130,8 +103,8 @@
disable_siblings = !CONFIG_LOGICAL_CPUS;
-#if CONFIG_LOGICAL_CPUS == 1
- if(read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) != 0) {
// 0 mean multi core
+#if CONFIG_LOGICAL_CPUS == 1 CONFIG_HAVE_OPTION_TABLE == 1
+ if (read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) != 0)
{// 0 mean multi core
disable_siblings = 1;
}
#endif
@@ -141,10 +114,10 @@
nb_cfg_54 = read_nb_cfg_54();
ApicIdCoreIdSize = (cpuid_ecx(0x8008) 12 0xf);
- if(ApicIdCoreIdSize) {
+ if (ApicIdCoreIdSize) {
siblings = ((1 ApicIdCoreIdSize) - 1);
} else {
- siblings = 3; //quad core
+ siblings = 3; //quad core
}
for (i = 0; i nodes;
Re: [coreboot] [commit] r5286 - ...
This is not all boards yet, but I send them out so I can go to bed :-) Here's one for all boards. Signed-off-by: Myles Watson myle...@gmail.com Thanks, Myles Index: svn/src/mainboard/amd/dbm690t/acpi_tables.c === --- svn.orig/src/mainboard/amd/dbm690t/acpi_tables.c +++ svn/src/mainboard/amd/dbm690t/acpi_tables.c @@ -57,7 +57,7 @@ static void dump_mem(u32 start, u32 end) } #endif -extern const acpi_header_t AmlCode; +extern const unsigned char AmlCode[]; #define IO_APIC_ADDR 0xfec0UL @@ -187,8 +187,9 @@ unsigned long write_acpi_tables(unsigned /* DSDT */ printk(BIOS_DEBUG, ACPI:* DSDT\n); dsdt = (acpi_header_t *)current; - current += AmlCode.length; - memcpy((void *)dsdt, AmlCode, AmlCode.length); + memcpy(dsdt, AmlCode, sizeof(acpi_header_t)); + current += dsdt-length; + memcpy(dsdt, AmlCode, dsdt-length); printk(BIOS_DEBUG, ACPI:* DSDT @ %p Length %x\n, dsdt, dsdt-length); /* FADT */ printk(BIOS_DEBUG, ACPI:* FADT\n); Index: svn/src/mainboard/amd/mahogany/acpi_tables.c === --- svn.orig/src/mainboard/amd/mahogany/acpi_tables.c +++ svn/src/mainboard/amd/mahogany/acpi_tables.c @@ -57,13 +57,13 @@ static void dump_mem(u32 start, u32 end) } #endif -extern const acpi_header_t AmlCode; +extern const unsigned char AmlCode[]; #if CONFIG_ACPI_SSDTX_NUM = 1 -extern const acpi_header_t AmlCode_ssdt2; -extern const acpi_header_t AmlCode_ssdt3; -extern const acpi_header_t AmlCode_ssdt4; -extern const acpi_header_t AmlCode_ssdt5; +extern const unsigned char AmlCode_ssdt2[]; +extern const unsigned char AmlCode_ssdt3[]; +extern const unsigned char AmlCode_ssdt4[]; +extern const unsigned char AmlCode_ssdt5[]; #endif #define IO_APIC_ADDR 0xfec0UL @@ -144,7 +144,7 @@ unsigned long write_acpi_tables(unsigned acpi_header_t *ssdt; #if CONFIG_ACPI_SSDTX_NUM = 1 acpi_header_t *ssdtx; - acpi_header_t const *p; + void *p; int i; #endif @@ -223,8 +223,9 @@ unsigned long write_acpi_tables(unsigned p = AmlCode_ssdt5; break; } - current += p-length; - memcpy((void *)ssdtx, p, p-length); + memcpy(ssdtx, p, sizeof(acpi_header_t)); + current += ssdtx-length; + memcpy(ssdtx, p, ssdtx-length); update_ssdtx((void *)ssdtx, i); ssdtx-checksum = 0; ssdtx-checksum = acpi_checksum((u8 *)ssdtx, ssdtx-length); @@ -240,9 +241,10 @@ unsigned long write_acpi_tables(unsigned /* DSDT */ printk(BIOS_DEBUG, ACPI:* DSDT\n); - dsdt = (acpi_header_t *) current; - memcpy((void *)dsdt, AmlCode, AmlCode.length); + dsdt = (acpi_header_t *)current; + memcpy(dsdt, AmlCode, sizeof(acpi_header_t)); current += dsdt-length; + memcpy(dsdt, AmlCode, dsdt-length); printk(BIOS_DEBUG, ACPI:* DSDT @ %p Length %x\n, dsdt, dsdt-length); /* FADT */ printk(BIOS_DEBUG, ACPI:* FADT\n); Index: svn/src/mainboard/amd/mahogany_fam10/acpi_tables.c === --- svn.orig/src/mainboard/amd/mahogany_fam10/acpi_tables.c +++ svn/src/mainboard/amd/mahogany_fam10/acpi_tables.c @@ -46,14 +46,14 @@ static void dump_mem(u32 start, u32 end) } #endif -extern const acpi_header_t AmlCode; -extern const acpi_header_t AmlCode_ssdt; +extern const unsigned char AmlCode[]; +extern const unsigned char AmlCode_ssdt[]; #if CONFIG_ACPI_SSDTX_NUM = 1 -extern const acpi_header_t AmlCode_ssdt2; -extern const acpi_header_t AmlCode_ssdt3; -extern const acpi_header_t AmlCode_ssdt4; -extern const acpi_header_t AmlCode_ssdt5; +extern const unsigned char AmlCode_ssdt2[]; +extern const unsigned char AmlCode_ssdt3[]; +extern const unsigned char AmlCode_ssdt4[]; +extern const unsigned char AmlCode_ssdt5[]; #endif #define IO_APIC_ADDR 0xfec0UL @@ -132,7 +132,7 @@ unsigned long write_acpi_tables(unsigned acpi_header_t *ssdt; #if CONFIG_ACPI_SSDTX_NUM = 1 acpi_header_t *ssdtx; - acpi_header_t const *p; + void *p; int i; #endif @@ -194,8 +194,9 @@ unsigned long write_acpi_tables(unsigned current = ( current + 0x0f) -0x10; printk(BIOS_DEBUG, ACPI:* SSDT at %lx\n, current); ssdt = (acpi_header_t *)current; - current += AmlCode_ssdt.length; - memcpy((void *)ssdt, AmlCode_ssdt, AmlCode_ssdt.length); + memcpy(ssdt, AmlCode_ssdt, sizeof(acpi_header_t)); + current += ssdt-length; + memcpy(ssdt, AmlCode_ssdt, ssdt-length); //Here you need to set value in pci1234, sblk and sbdn in get_bus_conf.c update_ssdt((void*)ssdt); /* recalculate checksum */ @@ -237,8 +238,9 @@ unsigned long write_acpi_tables(unsigned p = AmlCode_ssdt5; break; } - current += p-length; - memcpy((void *)ssdtx, p, p-length); + memcpy(ssdtx, p, sizeof(acpi_header_t)); + current += ssdtx-length; + memcpy(ssdtx, p, ssdtx-length); update_ssdtx((void *)ssdtx, i); ssdtx-checksum = 0; ssdtx-checksum = acpi_checksum((u8 *)ssdtx, ssdtx-length); @@ -250,8 +252,9 @@ unsigned long write_acpi_tables(unsigned
[coreboot] password
I have a lenovo x300 somebody set the password on and ... as you guess, forgot. So, question: anyone have any idea how deep into the machine the password is kept no new machines? Deep in TPM? in other words, were flashrom to work on this box, can the password be reset? ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] password
ron minnich wrote: I have a lenovo x300 somebody set the password on and ... as you guess, forgot. So, question: anyone have any idea how deep into the machine the password is kept no new machines? Deep in TPM? in other words, were flashrom to work on this box, can the password be reset? flashrom likely isn't enough. :\ ThinkPads at least used to have a special high security EEPROM, plus they've had fairly much more sophisticated ECs compared to other laptop designs, for a long time. I'm sure it's possible to reset that password, but I don't know where, and I'm pretty sure it's somewhere unusual. If you want to dive into the ThinkPad world of ECs, there was a lot of good work done on the T43 - although that one is old by now, maybe it can still be helpful: http://forum.thinkpads.com/viewtopic.php?t=20958 http://www.thinkwiki.org/wiki/Embedded_Controller_Firmware It may be quickest to just order a new system board for the laptop off eBay. //Peter -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] password
On Thu, 8 Apr 2010 18:45:34 +, ron minnich rminn...@gmail.com wrote: I have a lenovo x300 somebody set the password on and ... as you guess, forgot. So, question: anyone have any idea how deep into the machine the password is kept no new machines? Deep in TPM? in other words, were flashrom to work on this box, can the password be reset? I had an IBM Laptop that I had gotten used and it was password protected by the bios. I had found from googling around that there is a seperate EC on the board that held the password. By shorting 2 pins on the EC and powering it on, cleared it and I was able to use it. Hope that helps. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [PATCH]refactor crt0.S.lb
(retry, the first attempt seems to have been eaten by the list daemon) Hi, attached patch splits crt0.S.lb, adds the first part of it as first element of crt0s, adds the second part as last element of crt0s on romcc boards (it was guarded with #if CONFIG_USE_DCACHE_RAM==0), renames crt0_includes.h to crt0.S and runs this, instead of crt0.S.lb through the assembler. Minor clean up, but I hope it's clearer what's loaded when with this change. It passes abuild. Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de Index: src/arch/i386/Makefile.bootblock.inc === --- src/arch/i386/Makefile.bootblock.inc(revision 5378) +++ src/arch/i386/Makefile.bootblock.inc(working copy) @@ -96,7 +96,7 @@ mkdir -p $(obj)/romstage printf '$(foreach ldscript,ldoptions location.ld $(ldscripts),INCLUDE $(ldscript:$(obj)/%=%)\n)' $@ -$(obj)/romstage/crt0_includes.h: $$(crt0s) +$(obj)/romstage/crt0.S: $$(crt0s) @printf GEN$(subst $(obj)/,,$(@))\n mkdir -p $(obj)/romstage printf '$(foreach crt0,config.h $(crt0s),#include $(crt0:$(obj)/%=%)\n)' $@ @@ -105,7 +105,7 @@ @printf CC $(subst $(obj)/,,$(@))\n $(CC) -I$(obj) -Wa,-acdlns -c -o $@ $ $(dir $@)/crt0.disasm -$(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(src)/arch/i386/init/crt0.S.lb $(obj)/romstage/crt0_includes.h +$(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(obj)/romstage/crt0.S @printf CC $(subst $(obj)/,,$(@))\n $(CC) -x assembler-with-cpp -DASSEMBLY -E -I$(src)/include -I$(src)/arch/i386/include -I$(obj) -I$(obj)/romstage -include $(obj)/config.h -I. -I$(src) $ $...@.new mv $...@.new $@ Index: src/arch/i386/init/crt0.S.lb === --- src/arch/i386/init/crt0.S.lb(revision 5378) +++ src/arch/i386/init/crt0.S.lb(working copy) @@ -1,147 +0,0 @@ -/* -*- asm -*- - * $ $ - * - */ - -/* - * Copyright (C) 1996-2002 Markus Franz Xaver Johannes Oberhumer - * - * This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * Originally this code was part of ucl the data compression library - * for upx the ``Ultimate Packer of eXecutables''. - * - * - Converted to gas assembly, and refitted to work with etherboot. - * Eric Biederman 20 Aug 2002 - * - Merged the nrv2b decompressor into crt0.base of coreboot - * Eric Biederman 26 Sept 2002 - */ - - -#include arch/asm.h -#include arch/intel.h -#include console/loglevel.h - -#ifndef ASM_CONSOLE_LOGLEVEL -#define ASM_CONSOLE_LOGLEVEL CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -#endif - -/* - * This is the entry code the code in .reset section - * jumps to this address. - * - */ -.section .rom.data, a, @progbits -.section .rom.text, ax, @progbits - - post_code(0x01) /* delay for chipsets */ - -#include crt0_includes.h - -#if CONFIG_USE_DCACHE_RAM == 0 -#ifndef CONSOLE_DEBUG_TX_STRING - /* uses: esp, ebx, ax, dx */ -# define __CRT_CONSOLE_TX_STRING(string) \ - mov string, %ebx; \ - CALLSP(crt_console_tx_string) - -# if defined(CONFIG_TTYS0_BASE) (ASM_CONSOLE_LOGLEVEL BIOS_DEBUG) -# define CONSOLE_DEBUG_TX_STRING(string) __CRT_CONSOLE_TX_STRING(string) -# else -# define CONSOLE_DEBUG_TX_STRING(string) -# endif -#endif - - /* clear boot_complete flag */ - xorl%ebp, %ebp -__main: - CONSOLE_DEBUG_TX_STRING($str_copying_to_ram) - - /* -* Copy data into RAM and clear the BSS. Since these segments -* isn\'t really that big we just copy/clear using bytes, not -* double words. -*/ - post_code(0x11) /* post 11 */ - - cld /* clear direction flag */ - - /* copy coreboot from it's initial load location to -* the location it is compiled to run at. -* Normally this is copying from FLASH ROM to RAM. -*/ - movl%ebp, %esi - /* FIXME: look for a proper place for the stack */ - movl$0x400, %esp - movl%esp, %ebp - pushl %esi - pushl $str_coreboot_ram_name - call cbfs_and_run_core - -.Lhlt: - post_code(0xee) /* post fe */ - hlt - jmp .Lhlt - -#ifdef __CRT_CONSOLE_TX_STRING - /* Uses esp, ebx, ax, dx */ -crt_console_tx_string: - mov (%ebx), %al - inc %ebx - cmp $0, %al - jne 9f - RETSP -9: -/* Base Address */ -#ifndef CONFIG_TTYS0_BASE -#define CONFIG_TTYS0_BASE 0x3f8 -#endif -/* Data */ -#define TTYS0_RBR (CONFIG_TTYS0_BASE+0x00) - -/* Control */ -#define TTYS0_TBR TTYS0_RBR -#define TTYS0_IER (CONFIG_TTYS0_BASE+0x01) -#define TTYS0_IIR
Re: [coreboot] [PATCH]refactor crt0.S.lb
Acked-by: Stefan Reinauer ste...@coresystems.de On 4/8/10 10:17 PM, Patrick Georgi wrote: (retry, the first attempt seems to have been eaten by the list daemon) Hi, attached patch splits crt0.S.lb, adds the first part of it as first element of crt0s, adds the second part as last element of crt0s on romcc boards (it was guarded with #if CONFIG_USE_DCACHE_RAM==0), renames crt0_includes.h to crt0.S and runs this, instead of crt0.S.lb through the assembler. Minor clean up, but I hope it's clearer what's loaded when with this change. It passes abuild. Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] CAR on Intel P6 Series - Support for model_6bx
On 4/8/10 8:09 AM, Joseph Smith wrote: Signed-off-by: Joseph Smith j...@settoplinux.org Nice! Thanks, Joseph! Index: src/cpu/intel/Kconfig === --- src/cpu/intel/Kconfig (revision 5372) +++ src/cpu/intel/Kconfig (working copy) +source src/cpu/intel/socket_mfcbga479/Kconfig source src/cpu/intel/socket_mFCPGA478/Kconfig source src/cpu/intel/socket_mPGA478/Kconfig source src/cpu/intel/socket_mPGA479M/Kconfig I think you should keep the naming convention here: mFCBGA479 Index: src/cpu/intel/Makefile.inc === --- src/cpu/intel/Makefile.inc(revision 5372) +++ src/cpu/intel/Makefile.inc(working copy) @@ -6,6 +6,7 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_441) += socket_441 subdirs-$(CONFIG_CPU_INTEL_SOCKET_BGA956) += bga956 subdirs-$(CONFIG_CPU_INTEL_EP80579) += ep80579 +subdirs-$(CONFIG_CPU_INTEL_SOCKET_MFCBGA479) += socket_mfcbga479 ditto Index: src/cpu/intel/model_6bx/Kconfig === --- src/cpu/intel/model_6bx/Kconfig (revision 0) +++ src/cpu/intel/model_6bx/Kconfig (revision 0) @@ -0,0 +1,3 @@ +config CPU_INTEL_CORE + bool + select SMP Now, this is definitely wrong. Index: src/cpu/intel/socket_mfcbga479/Kconfig === --- src/cpu/intel/socket_mfcbga479/Kconfig(revision 0) +++ src/cpu/intel/socket_mfcbga479/Kconfig(revision 0) @@ -0,0 +1,5 @@ +config CPU_INTEL_SOCKET_MFCBGA479 + bool + select CPU_INTEL_MODEL_6BX Where is CPU_INTEL_MODEL_6BX defined? With above issues fixed this is Acked-by: Stefan Reinauer ste...@coresystems.de Stefan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r5383 - in trunk: . src/arch/i386 src/arch/i386/init
Author: oxygene Date: Thu Apr 8 23:04:45 2010 New Revision: 5383 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5383 Log: Split crt0.S.lb into prologue and epilogue (the latter only for romcc), rename crt0_includes.h to crt0.S, and compile that directly. Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de Acked-by: Stefan Reinauer ste...@coresystems.de Added: trunk/src/arch/i386/init/crt0_prologue.inc - copied, changed from r5378, trunk/src/arch/i386/init/crt0.S.lb trunk/src/arch/i386/init/crt0_romcc_epilogue.inc - copied, changed from r5378, trunk/src/arch/i386/init/crt0.S.lb Deleted: trunk/src/arch/i386/init/crt0.S.lb Modified: trunk/Makefile trunk/src/arch/i386/Makefile.bigbootblock.inc trunk/src/arch/i386/Makefile.bootblock.inc trunk/src/arch/i386/Makefile.inc Modified: trunk/Makefile == --- trunk/Makefile Thu Apr 8 17:12:18 2010(r5382) +++ trunk/Makefile Thu Apr 8 23:04:45 2010(r5383) @@ -320,7 +320,7 @@ rm -f $(DEPENDENCIES) rm -f $(obj)/coreboot_ram* $(obj)/coreboot.romstage $(obj)/coreboot.pre* $(obj)/coreboot.bootblock $(obj)/coreboot.a rm -rf $(obj)/bootblock* $(obj)/romstage* $(obj)/location.* - rm -f $(obj)/option_table.* $(obj)/crt0_includes.h $(obj)/ldscript + rm -f $(obj)/option_table.* $(obj)/crt0.S $(obj)/ldscript rm -f $(obj)/mainboard/$(MAINBOARDDIR)/static.c $(obj)/mainboard/$(MAINBOARDDIR)/config.py $(obj)/mainboard/$(MAINBOARDDIR)/static.dot rm -f $(obj)/mainboard/$(MAINBOARDDIR)/crt0.s $(obj)/mainboard/$(MAINBOARDDIR)/crt0.disasm rm -f $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc Modified: trunk/src/arch/i386/Makefile.bigbootblock.inc == --- trunk/src/arch/i386/Makefile.bigbootblock.inc Thu Apr 8 17:12:18 2010(r5382) +++ trunk/src/arch/i386/Makefile.bigbootblock.inc Thu Apr 8 23:04:45 2010(r5383) @@ -16,7 +16,7 @@ printf 'INCLUDE ldoptions\n' $@ printf '$(foreach ldscript,$(ldscripts),INCLUDE $(ldscript:$(obj)/%=%)\n)' $@ -$(obj)/crt0_includes.h: $$(crt0s) +$(obj)/crt0.S: $$(crt0s) @printf GEN$(subst $(obj)/,,$(@))\n printf '$(foreach crt0,config.h $(crt0s),#include $(crt0:$(obj)/%=%)\n)' $@ @@ -24,7 +24,7 @@ @printf CC $(subst $(obj)/,,$(@))\n $(CC) -MMD -I$(obj) -Wa,-acdlns -c -o $@ $ $(dir $@)/crt0.disasm -$(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(src)/arch/i386/init/crt0.S.lb $(obj)/crt0_includes.h +$(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(obj)/crt0.S @printf CC $(subst $(obj)/,,$(@))\n $(CC) -MMD -x assembler-with-cpp -DASSEMBLY -E -I$(src)/include -I$(src)/arch/i386/include -I$(obj) -include $(obj)/config.h -I. -I$(src) $ $...@.new mv $...@.new $@ Modified: trunk/src/arch/i386/Makefile.bootblock.inc == --- trunk/src/arch/i386/Makefile.bootblock.inc Thu Apr 8 17:12:18 2010 (r5382) +++ trunk/src/arch/i386/Makefile.bootblock.inc Thu Apr 8 23:04:45 2010 (r5383) @@ -96,7 +96,7 @@ mkdir -p $(obj)/romstage printf '$(foreach ldscript,ldoptions location.ld $(ldscripts),INCLUDE $(ldscript:$(obj)/%=%)\n)' $@ -$(obj)/romstage/crt0_includes.h: $$(crt0s) +$(obj)/romstage/crt0.S: $$(crt0s) @printf GEN$(subst $(obj)/,,$(@))\n mkdir -p $(obj)/romstage printf '$(foreach crt0,config.h $(crt0s),#include $(crt0:$(obj)/%=%)\n)' $@ @@ -105,7 +105,7 @@ @printf CC $(subst $(obj)/,,$(@))\n $(CC) -I$(obj) -Wa,-acdlns -c -o $@ $ $(dir $@)/crt0.disasm -$(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(src)/arch/i386/init/crt0.S.lb $(obj)/romstage/crt0_includes.h +$(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(obj)/romstage/crt0.S @printf CC $(subst $(obj)/,,$(@))\n $(CC) -x assembler-with-cpp -DASSEMBLY -E -I$(src)/include -I$(src)/arch/i386/include -I$(obj) -I$(obj)/romstage -include $(obj)/config.h -I. -I$(src) $ $...@.new mv $...@.new $@ Modified: trunk/src/arch/i386/Makefile.inc == --- trunk/src/arch/i386/Makefile.incThu Apr 8 17:12:18 2010(r5382) +++ trunk/src/arch/i386/Makefile.incThu Apr 8 23:04:45 2010(r5383) @@ -100,7 +100,7 @@ ### # done -crt0s = +crt0s = $(src)/arch/i386/init/crt0_prologue.inc ldscripts = ldscripts += $(src)/arch/i386/init/ldscript_fallback_cbfs.lb ifeq ($(CONFIG_BIG_BOOTBLOCK),y) @@ -196,6 +196,10 @@ ldscripts += $(chipset_bootblock_lds) endif +ifeq ($(CONFIG_ROMCC),y) +crt0s += $(src)/arch/i386/init/crt0_romcc_epilogue.inc +endif +
Re: [coreboot] [PATCH] CAR on Intel P6 Series - Support for model_6bx
On Thu, 08 Apr 2010 22:51:25 +0200, Stefan Reinauer ste...@coresystems.de wrote: On 4/8/10 8:09 AM, Joseph Smith wrote: Signed-off-by: Joseph Smith j...@settoplinux.org Nice! Thanks, Joseph! Index: src/cpu/intel/Kconfig === --- src/cpu/intel/Kconfig(revision 5372) +++ src/cpu/intel/Kconfig(working copy) +source src/cpu/intel/socket_mfcbga479/Kconfig source src/cpu/intel/socket_mFCPGA478/Kconfig source src/cpu/intel/socket_mPGA478/Kconfig source src/cpu/intel/socket_mPGA479M/Kconfig I think you should keep the naming convention here: mFCBGA479 Ok I can do that. Index: src/cpu/intel/Makefile.inc === --- src/cpu/intel/Makefile.inc (revision 5372) +++ src/cpu/intel/Makefile.inc (working copy) @@ -6,6 +6,7 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_441) += socket_441 subdirs-$(CONFIG_CPU_INTEL_SOCKET_BGA956) += bga956 subdirs-$(CONFIG_CPU_INTEL_EP80579) += ep80579 +subdirs-$(CONFIG_CPU_INTEL_SOCKET_MFCBGA479) += socket_mfcbga479 ditto Index: src/cpu/intel/model_6bx/Kconfig === --- src/cpu/intel/model_6bx/Kconfig (revision 0) +++ src/cpu/intel/model_6bx/Kconfig (revision 0) @@ -0,0 +1,3 @@ +config CPU_INTEL_CORE +bool +select SMP Now, this is definitely wrong. Oops, I will fix that. Index: src/cpu/intel/socket_mfcbga479/Kconfig === --- src/cpu/intel/socket_mfcbga479/Kconfig (revision 0) +++ src/cpu/intel/socket_mfcbga479/Kconfig (revision 0) @@ -0,0 +1,5 @@ +config CPU_INTEL_SOCKET_MFCBGA479 +bool +select CPU_INTEL_MODEL_6BX Where is CPU_INTEL_MODEL_6BX defined? Not sure what you mean. It is defined by the socket. With above issues fixed this is Acked-by: Stefan Reinauer ste...@coresystems.de -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] CAR on Intel P6 Series - Support for model_6bx
On 4/8/10 11:32 PM, Joseph Smith wrote: Index: src/cpu/intel/model_6bx/Kconfig === --- src/cpu/intel/model_6bx/Kconfig (revision 0) +++ src/cpu/intel/model_6bx/Kconfig (revision 0) @@ -0,0 +1,3 @@ +config CPU_INTEL_CORE + bool + select SMP Now, this is definitely wrong. Oops, I will fix that. Index: src/cpu/intel/socket_mfcbga479/Kconfig === --- src/cpu/intel/socket_mfcbga479/Kconfig (revision 0) +++ src/cpu/intel/socket_mfcbga479/Kconfig (revision 0) @@ -0,0 +1,5 @@ +config CPU_INTEL_SOCKET_MFCBGA479 + bool + select CPU_INTEL_MODEL_6BX Where is CPU_INTEL_MODEL_6BX defined? Not sure what you mean. It is defined by the socket. No, it's not. It's used in the socket, but it's never defined anywhere. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] CAR on Intel P6 Series - Support for model_6bx
On Thu, 08 Apr 2010 23:37:59 +0200, Stefan Reinauer ste...@coresystems.de wrote: On 4/8/10 11:32 PM, Joseph Smith wrote: Index: src/cpu/intel/model_6bx/Kconfig === --- src/cpu/intel/model_6bx/Kconfig(revision 0) +++ src/cpu/intel/model_6bx/Kconfig(revision 0) @@ -0,0 +1,3 @@ +config CPU_INTEL_CORE + bool + select SMP Now, this is definitely wrong. Oops, I will fix that. Index: src/cpu/intel/socket_mfcbga479/Kconfig === --- src/cpu/intel/socket_mfcbga479/Kconfig (revision 0) +++ src/cpu/intel/socket_mfcbga479/Kconfig (revision 0) @@ -0,0 +1,5 @@ +config CPU_INTEL_SOCKET_MFCBGA479 + bool + select CPU_INTEL_MODEL_6BX Where is CPU_INTEL_MODEL_6BX defined? Not sure what you mean. It is defined by the socket. No, it's not. It's used in the socket, but it's never defined anywhere. hmm, ok I will look into it. Thanks for your review Stefan. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] CAR on Intel P6 Series - Support for model_6bx
On Thu, 08 Apr 2010 23:37:59 +0200, Stefan Reinauer ste...@coresystems.de wrote: On 4/8/10 11:32 PM, Joseph Smith wrote: Index: src/cpu/intel/model_6bx/Kconfig === --- src/cpu/intel/model_6bx/Kconfig(revision 0) +++ src/cpu/intel/model_6bx/Kconfig(revision 0) @@ -0,0 +1,3 @@ +config CPU_INTEL_CORE + bool + select SMP This looks like it was copied directly from cpu/intel/model_6ex/Kconfig. You are redefining CPU_INTEL_CORE here. This is probably where you wanted to define CPU_INTEL_MODEL_6BX. Myles -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] CAR on Intel P6 Series - Support for model_6bx
On Thu, 8 Apr 2010 15:45:50 -0600, Myles Watson myle...@gmail.com wrote: On Thu, 08 Apr 2010 23:37:59 +0200, Stefan Reinauer ste...@coresystems.de wrote: On 4/8/10 11:32 PM, Joseph Smith wrote: Index: src/cpu/intel/model_6bx/Kconfig === --- src/cpu/intel/model_6bx/Kconfig(revision 0) +++ src/cpu/intel/model_6bx/Kconfig(revision 0) @@ -0,0 +1,3 @@ +config CPU_INTEL_CORE + bool + select SMP This looks like it was copied directly from cpu/intel/model_6ex/Kconfig. You are redefining CPU_INTEL_CORE here. This is probably where you wanted to define CPU_INTEL_MODEL_6BX. Ah ok thanks Myles. So there is not actually a: #define CPU_INTEL_MODEL_6BX blabla preprocessing directive anywhere. It just needs to be defined in Kconfig. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] CAR on Intel P6 Series - Support for model_6bx
-Original Message- From: Joseph Smith [mailto:j...@settoplinux.org] Sent: Thursday, April 08, 2010 3:59 PM To: Myles Watson Cc: Stefan Reinauer; coreboot@coreboot.org Subject: Re: [coreboot] [PATCH] CAR on Intel P6 Series - Support for model_6bx On 4/8/10 11:32 PM, Joseph Smith wrote: Index: src/cpu/intel/model_6bx/Kconfig === --- src/cpu/intel/model_6bx/Kconfig(revision 0) +++ src/cpu/intel/model_6bx/Kconfig(revision 0) @@ -0,0 +1,3 @@ +config CPU_INTEL_CORE + bool + select SMP This looks like it was copied directly from cpu/intel/model_6ex/Kconfig. You are redefining CPU_INTEL_CORE here. This is probably where you wanted to define CPU_INTEL_MODEL_6BX. Ah ok thanks Myles. So there is not actually a: #define CPU_INTEL_MODEL_6BX blabla preprocessing directive anywhere. It just needs to be defined in Kconfig. That's right. config FOO defines CONFIG_FOO. select FOO just sets it if it exists. You can check in your .config file to make sure the symbols you expect to be defined are showing up. Thanks, Myles -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] CAR on Intel P6 Series - Support for model_6bx
On Thu, 8 Apr 2010 16:02:09 -0600, Myles Watson myle...@gmail.com wrote: -Original Message- From: Joseph Smith [mailto:j...@settoplinux.org] Sent: Thursday, April 08, 2010 3:59 PM To: Myles Watson Cc: Stefan Reinauer; coreboot@coreboot.org Subject: Re: [coreboot] [PATCH] CAR on Intel P6 Series - Support for model_6bx On 4/8/10 11:32 PM, Joseph Smith wrote: Index: src/cpu/intel/model_6bx/Kconfig === --- src/cpu/intel/model_6bx/Kconfig(revision 0) +++ src/cpu/intel/model_6bx/Kconfig(revision 0) @@ -0,0 +1,3 @@ +config CPU_INTEL_CORE + bool + select SMP This looks like it was copied directly from cpu/intel/model_6ex/Kconfig. You are redefining CPU_INTEL_CORE here. This is probably where you wanted to define CPU_INTEL_MODEL_6BX. Ah ok thanks Myles. So there is not actually a: #define CPU_INTEL_MODEL_6BX blabla preprocessing directive anywhere. It just needs to be defined in Kconfig. That's right. config FOO defines CONFIG_FOO. select FOO just sets it if it exists. You can check in your .config file to make sure the symbols you expect to be defined are showing up. Hmm, I wonder why this did not throw an error at me? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] P2B-LS status for wiki
On Thu, Mar 25, 2010 at 12:18:37AM -0400, Keith Hui wrote: Hi all, As title. Can someone enter this into the wiki? Sorry for the delay. I was about to add it, but then noticed you already got an account and did it. Some notes below: On-board hardware On-board IDE 3.5: Secondary IDE works. There are some problems with primary IDE. Hm, strange. What kind of problems? (sorry if you already mentioned this, haven't read all my backlog yet) On-board ethernet: OK - Works only when not listed in the mainboard's device tree. Also strange. This should not happen, probably a side-effect of incorrect PIRQ tables (?) Add-on slots ISA add-on cards: OK - Tested with Sound Blaster AWE64 ISA. Detected, initialized, ALSA driver loaded, no sound PCI add-on cards: OK - Tested with a PCI NE2000 NIC in one slot Please note that for all ISA/PCI/PCIe slots you always have to specify which slots exactly you tested. One PCI slot for instance could work fine while the other two on the same board are not working (due to incorrect PIRQ table / MPtable / ACPI table). If you get a chance, please test the same NIC in all PCI slots etc. to be sure everything works. SMBus: OK This entry is not for the SMBus to talk to the EEPROM on the RAM DIMMs btw, but should rather indicate if an SMBus / I2C pin header on the board have been tested and work (if any). This _may_ be the same status as for the SMBus setup to talk to DIMM EEPROMs, but probably not necessarily, so should be tested independently. If you don't have such a header on the P2B-LS, you can mark it as N/A. flashrom: OK You wrote Board not directly supported by flashrom; force P2B-F as the mainboard target. which sounds strange. Please contact us in #flashrom on IRC or on the flashrom mailing list to figure this out, thanks! It's likely that the board needs a board-enable chunk of code in flashrom. I'll have a look at your other 440BX related patches soonish, after reading my backlog, have been way too busy with other projects (mostly http://sigrok.org, for the curious), sorry. Uwe. -- http://www.hermann-uwe.de | http://www.randomprojects.org http://www.crazy-hacks.org | http://www.unmaintained-free-software.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] CAR on Intel P6 Series - Support for model_6bx
On Thu, Apr 8, 2010 at 4:12 PM, Joseph Smith j...@settoplinux.org wrote: On Thu, 8 Apr 2010 16:02:09 -0600, Myles Watson myle...@gmail.com wrote: -Original Message- From: Joseph Smith [mailto:j...@settoplinux.org] Sent: Thursday, April 08, 2010 3:59 PM To: Myles Watson Cc: Stefan Reinauer; coreboot@coreboot.org Subject: Re: [coreboot] [PATCH] CAR on Intel P6 Series - Support for model_6bx On 4/8/10 11:32 PM, Joseph Smith wrote: Index: src/cpu/intel/model_6bx/Kconfig === --- src/cpu/intel/model_6bx/Kconfig(revision 0) +++ src/cpu/intel/model_6bx/Kconfig(revision 0) @@ -0,0 +1,3 @@ +config CPU_INTEL_CORE + bool + select SMP This looks like it was copied directly from cpu/intel/model_6ex/Kconfig. You are redefining CPU_INTEL_CORE here. This is probably where you wanted to define CPU_INTEL_MODEL_6BX. Ah ok thanks Myles. So there is not actually a: #define CPU_INTEL_MODEL_6BX blabla preprocessing directive anywhere. It just needs to be defined in Kconfig. That's right. config FOO defines CONFIG_FOO. select FOO just sets it if it exists. You can check in your .config file to make sure the symbols you expect to be defined are showing up. Hmm, I wonder why this did not throw an error at me? Selecting undefined config options doesn't throw an error. I think it would be nice if it did, but there might be some reason that I don't know of why you want to be able to select undefined things and have nothing happen. Thanks, Myles -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] password
On 08.04.2010 20:45, ron minnich wrote: I have a lenovo x300 somebody set the password on and ... as you guess, forgot. BIOS password or boot password? So, question: anyone have any idea how deep into the machine the password is kept no new machines? Deep in TPM? in other words, were flashrom to work on this box, can the password be reset? It depends. I know that you can reset the password with flashrom on HP machines (got a success report about that a few weeks ago). Not sure about Lenovo. You can store a password (or a hash of it) in flash or NVRAM or a small SPI EEPROM or an I2C EEPROM or even the TPM or any combination thereof. How much time/money are you willing to invest? - The easiest and probably most expensive way (could be a few hundred dollars) is to send the laptop with a proof of ownership to Lenovo to have it unlocked. - A risky and fast (if you can recover from a misflashed ROM) way is to simply flash a new ROM image which is pretty much guaranteed to have no builtin protection, but it won't help at all if the protection is not dependent on flash contents. Messing with nvramtool might have other effects, but hey, you can try that as well. - If you have a good logic analyzer, you can watch the traffic to the TPM, NVRAM, flash, and all other EEPROMs around the time you enter the password. If you find a good way to get the password removed, there's always the option of selling that knowledge to non-Lenovo repair shops. Good luck! Regards, Carl-Daniel -- http://www.hailfinger.org/ -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [commit] r5286 - ...
On 4/8/10 7:07 PM, Myles Watson wrote: Here's one for all boards. Signed-off-by: Myles Watson myle...@gmail.com mailto:myle...@gmail.com Acked-by: Stefan Reinauer ste...@coresystems.de Index: svn/src/mainboard/amd/dbm690t/acpi_tables.c === --- svn.orig/src/mainboard/amd/dbm690t/acpi_tables.c +++ svn/src/mainboard/amd/dbm690t/acpi_tables.c @@ -57,7 +57,7 @@ static void dump_mem(u32 start, u32 end) } #endif -extern const acpi_header_t AmlCode; +extern const unsigned char AmlCode[]; I don't think defining them const here gains us much, as they're not defined const when they're created. Can we change that, maybe? Extra sed s/unsigned char AmlCode/const unsigned char AmlCode/g on the iasl output maybe? Stefan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r5384 - in trunk/src: mainboard/amd/dbm690t mainboard/amd/mahogany mainboard/amd/mahogany_fam10 mainboard/amd/pistachio mainboard/amd/serengeti_cheetah mainboard/amd/serengeti_chee
Author: myles Date: Fri Apr 9 05:41:23 2010 New Revision: 5384 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5384 Log: Copy acpi blobs in two parts to make sure gcc does the right thing. Signed-off-by: Myles Watson myle...@gmail.com Acked-by: Stefan Reinauer ste...@coresystems.de Modified: trunk/src/mainboard/amd/dbm690t/acpi_tables.c trunk/src/mainboard/amd/mahogany/acpi_tables.c trunk/src/mainboard/amd/mahogany_fam10/acpi_tables.c trunk/src/mainboard/amd/pistachio/acpi_tables.c trunk/src/mainboard/amd/serengeti_cheetah/acpi_tables.c trunk/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c trunk/src/mainboard/asrock/939a785gmh/acpi_tables.c trunk/src/mainboard/asus/a8v-e_se/acpi_tables.c trunk/src/mainboard/asus/m2v-mx_se/acpi_tables.c trunk/src/mainboard/gigabyte/m57sli/acpi_tables.c trunk/src/mainboard/intel/d945gclf/acpi_tables.c trunk/src/mainboard/intel/eagleheights/acpi_tables.c trunk/src/mainboard/iwill/dk8_htx/acpi_tables.c trunk/src/mainboard/kontron/986lcd-m/acpi_tables.c trunk/src/mainboard/kontron/kt690/acpi_tables.c trunk/src/mainboard/msi/ms9652_fam10/acpi_tables.c trunk/src/mainboard/roda/rk886ex/acpi_tables.c trunk/src/mainboard/technexion/tim5690/acpi_tables.c trunk/src/mainboard/technexion/tim8690/acpi_tables.c trunk/src/mainboard/tyan/s2891/acpi_tables.c trunk/src/mainboard/tyan/s2892/acpi_tables.c trunk/src/mainboard/tyan/s2895/acpi_tables.c trunk/src/mainboard/via/epia-m/acpi_tables.c trunk/src/mainboard/via/epia-m700/acpi_tables.c trunk/src/mainboard/via/epia-n/acpi_tables.c trunk/src/mainboard/via/vt8454c/acpi_tables.c trunk/src/northbridge/amd/amdfam10/amdfam10_acpi.c Modified: trunk/src/mainboard/amd/dbm690t/acpi_tables.c == --- trunk/src/mainboard/amd/dbm690t/acpi_tables.c Thu Apr 8 23:04:45 2010(r5383) +++ trunk/src/mainboard/amd/dbm690t/acpi_tables.c Fri Apr 9 05:41:23 2010(r5384) @@ -57,7 +57,7 @@ } #endif -extern const acpi_header_t AmlCode; +extern const unsigned char AmlCode[]; #define IO_APIC_ADDR 0xfec0UL @@ -187,8 +187,9 @@ /* DSDT */ printk(BIOS_DEBUG, ACPI:* DSDT\n); dsdt = (acpi_header_t *)current; - current += AmlCode.length; - memcpy((void *)dsdt, AmlCode, AmlCode.length); + memcpy(dsdt, AmlCode, sizeof(acpi_header_t)); + current += dsdt-length; + memcpy(dsdt, AmlCode, dsdt-length); printk(BIOS_DEBUG, ACPI:* DSDT @ %p Length %x\n, dsdt, dsdt-length); /* FADT */ printk(BIOS_DEBUG, ACPI:* FADT\n); Modified: trunk/src/mainboard/amd/mahogany/acpi_tables.c == --- trunk/src/mainboard/amd/mahogany/acpi_tables.c Thu Apr 8 23:04:45 2010(r5383) +++ trunk/src/mainboard/amd/mahogany/acpi_tables.c Fri Apr 9 05:41:23 2010(r5384) @@ -57,13 +57,13 @@ } #endif -extern const acpi_header_t AmlCode; +extern const unsigned char AmlCode[]; #if CONFIG_ACPI_SSDTX_NUM = 1 -extern const acpi_header_t AmlCode_ssdt2; -extern const acpi_header_t AmlCode_ssdt3; -extern const acpi_header_t AmlCode_ssdt4; -extern const acpi_header_t AmlCode_ssdt5; +extern const unsigned char AmlCode_ssdt2[]; +extern const unsigned char AmlCode_ssdt3[]; +extern const unsigned char AmlCode_ssdt4[]; +extern const unsigned char AmlCode_ssdt5[]; #endif #define IO_APIC_ADDR 0xfec0UL @@ -144,7 +144,7 @@ acpi_header_t *ssdt; #if CONFIG_ACPI_SSDTX_NUM = 1 acpi_header_t *ssdtx; - acpi_header_t const *p; + void *p; int i; #endif @@ -223,8 +223,9 @@ p = AmlCode_ssdt5; break; } - current += p-length; - memcpy((void *)ssdtx, p, p-length); + memcpy(ssdtx, p, sizeof(acpi_header_t)); + current += ssdtx-length; + memcpy(ssdtx, p, ssdtx-length); update_ssdtx((void *)ssdtx, i); ssdtx-checksum = 0; ssdtx-checksum = acpi_checksum((u8 *)ssdtx, ssdtx-length); @@ -240,9 +241,10 @@ /* DSDT */ printk(BIOS_DEBUG, ACPI:* DSDT\n); - dsdt = (acpi_header_t *) current; - memcpy((void *)dsdt, AmlCode, AmlCode.length); + dsdt = (acpi_header_t *)current; + memcpy(dsdt, AmlCode, sizeof(acpi_header_t)); current += dsdt-length; + memcpy(dsdt, AmlCode, dsdt-length); printk(BIOS_DEBUG, ACPI:* DSDT @ %p Length %x\n, dsdt, dsdt-length); /* FADT */ printk(BIOS_DEBUG, ACPI:* FADT\n); Modified: trunk/src/mainboard/amd/mahogany_fam10/acpi_tables.c == --- trunk/src/mainboard/amd/mahogany_fam10/acpi_tables.cThu Apr 8 23:04:45 2010
Re: [coreboot] password
I'm not sure if this will work and it's risky as well, but you might want to try it out: In most BIOS, shorting the address pins (or the equivalent of that act) upon boot will force the machine to boot from the bootblock BIOS. The bootblock routine usually searches for BIOS binary file to flash, because the assumption is the system BIOS a.k.a main BIOS module is corrupt and need replacement. I'm not sure how to provide this new BIOS binary file replacement for your case. However, most BIOS requires boot floppy (in recent days FAT16 formatted USB sticks) which contains an autoexec.bat file with the routine to flash the new BIOS binary and the BIOS binary file itself. On 4/9/10, Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net wrote: On 08.04.2010 20:45, ron minnich wrote: I have a lenovo x300 somebody set the password on and ... as you guess, forgot. BIOS password or boot password? So, question: anyone have any idea how deep into the machine the password is kept no new machines? Deep in TPM? in other words, were flashrom to work on this box, can the password be reset? It depends. I know that you can reset the password with flashrom on HP machines (got a success report about that a few weeks ago). Not sure about Lenovo. You can store a password (or a hash of it) in flash or NVRAM or a small SPI EEPROM or an I2C EEPROM or even the TPM or any combination thereof. How much time/money are you willing to invest? - The easiest and probably most expensive way (could be a few hundred dollars) is to send the laptop with a proof of ownership to Lenovo to have it unlocked. - A risky and fast (if you can recover from a misflashed ROM) way is to simply flash a new ROM image which is pretty much guaranteed to have no builtin protection, but it won't help at all if the protection is not dependent on flash contents. Messing with nvramtool might have other effects, but hey, you can try that as well. - If you have a good logic analyzer, you can watch the traffic to the TPM, NVRAM, flash, and all other EEPROMs around the time you enter the password. If you find a good way to get the password removed, there's always the option of selling that knowledge to non-Lenovo repair shops. Good luck! Regards, Carl-Daniel -- http://www.hailfinger.org/ -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- -= Human knowledge belongs to the world =- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [commit] r5286 - ...
On Thu, Apr 8, 2010 at 5:03 PM, Stefan Reinauer ste...@coresystems.dewrote: On 4/8/10 7:07 PM, Myles Watson wrote: Here's one for all boards. Signed-off-by: Myles Watson myle...@gmail.com Acked-by: Stefan Reinauer ste...@coresystems.de ste...@coresystems.de Rev. 5384 Index: svn/src/mainboard/amd/dbm690t/acpi_tables.c === --- svn.orig/src/mainboard/amd/dbm690t/acpi_tables.c +++ svn/src/mainboard/amd/dbm690t/acpi_tables.c @@ -57,7 +57,7 @@ static void dump_mem(u32 start, u32 end) } #endif -extern const acpi_header_t AmlCode; +extern const unsigned char AmlCode[]; I don't think defining them const here gains us much, as they're not defined const when they're created. I thought that making them const here would make it so that you couldn't do: AmlCode[23] = 'c'; without a warning. Can we change that, maybe? Extra sed s/unsigned char AmlCode/const unsigned char AmlCode/g on the iasl output maybe? That would be fine with me. It might be more effort than it's worth. As long as we copy it before anything else, there shouldn't be any problems. Thanks, Myles -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [PATCH] 440BX raminit cleanup
Attached patch does the following on 440BX RAM init code: 1. Restore DUMPNORTH() macro. dump_pci_device() never really went away, as romstages for all 440BX boards included lib/debug.c required for it. 2. Move the NB macro up and changed DUMPNORTH() to use it as well. 3. Resolves a number of TODO items. That also means filling in some additional register descriptions marked as such. 4. Change register_values[] static array from array of long to array of u8. Takes up only 1/4 of previous size and still do the same thing. 5. Remove the extra line that unconditionally sets SDRAMPWR, which is just wrong now that it is contained in register_values[] array and properly conditioned by a config option. 6. Small cosmetic tidy-ups. If I have submitted a previous patch for the same (I don't even remember now :-O), this patch supersedes it. abuild-tested on all 440BX targets. Boot tested on P2B-LS. Signed-off-by: Keith Hui buu...@gmail.com romstage boot log with detailed RAM init debug enabled: coreboot-4.0-r5383M Thu Apr 8 23:21:32 EDT 2010 starting... SMBus controller enabled Northbridge prior to SDRAM init: PCI: 00:00.00 00: 86 80 90 71 06 00 10 22 03 00 00 06 00 00 00 00 10: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 04 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 60: 01 01 01 01 01 01 01 01 00 00 00 00 00 00 00 00 70: 00 1f 02 38 00 00 00 00 00 00 00 38 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 80 00 00 00 04 61 00 00 00 05 00 00 00 00 00 00 a0: 02 00 10 00 03 02 00 1f 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 18 0c 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 0c 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 f8 00 00 20 0f 00 00 00 00 00 00 Found DIMM in slot 00 Found DIMM in slot 01 PGPOL[BPR] has been set to 0x0f RPS has been set to 0x00a5 NBXECC[31:24] has been set to 0xff DRAMC has been set to 0x08 RAM Enable 1: Apply NOP RAM Enable 2: Precharge all RAM Enable 3: CBR RAM Enable 4: Mode register set RAM Enable 5: Normal operation RAM Enable 6: Enable refresh Enabling refresh (DRAMC = 0x09) for DIMM 00 Enabling refresh (DRAMC = 0x09) for DIMM 01 Northbridge following SDRAM init: PCI: 00:00.00 00: 86 80 90 71 06 00 10 22 03 00 00 06 00 00 00 00 10: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 0c 80 00 ff 00 00 00 09 03 30 33 33 33 33 33 33 60: 08 10 20 30 30 30 30 30 00 ec 2b 00 a0 ba 00 00 70: 00 1f 02 38 a5 00 10 00 00 0f 10 38 10 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 80 00 00 00 04 61 00 00 00 05 00 00 00 00 00 00 a0: 02 00 10 00 03 02 00 1f 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 18 0c e4 ff 5f 00 00 00 d0: 00 00 00 00 00 00 00 00 0c 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 f8 00 00 20 0f 00 00 00 00 00 00 Testing DRAM : -000a DRAM fill: -000a 000a DRAM filled DRAM verify: -000a 000a DRAM range verified. Done. Copying coreboot to RAM. Loading stage image. Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x10 (147456 bytes), entry @ 0x10 Stage: done loading. Jumping to image. 440bxraminitcleanup.patch Description: Binary data -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r5385 - in trunk/src/cpu/amd: model_10xxx model_fxx
Author: myles
Date: Fri Apr 9 06:01:55 2010
New Revision: 5385
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5385
Log:
Indent model_fxx_init and model_10xx_init.
Signed-off-by: Myles Watson myle...@gmail.com
Acked-by: Myles Watson myle...@gmail.com
Modified:
trunk/src/cpu/amd/model_10xxx/model_10xxx_init.c
trunk/src/cpu/amd/model_fxx/model_fxx_init.c
Modified: trunk/src/cpu/amd/model_10xxx/model_10xxx_init.c
==
--- trunk/src/cpu/amd/model_10xxx/model_10xxx_init.cFri Apr 9 05:41:23
2010(r5384)
+++ trunk/src/cpu/amd/model_10xxx/model_10xxx_init.cFri Apr 9 06:01:55
2010(r5385)
@@ -43,26 +43,24 @@
msr_t rdmsr_amd(u32 index)
{
-msr_t result;
-__asm__ __volatile__ (
-rdmsr
-: =a (result.lo), =d (result.hi)
-: c (index), D (0x9c5a203a)
-);
-return result;
+ msr_t result;
+ __asm__ __volatile__(
+ rdmsr
+ :=a(result.lo), =d(result.hi)
+ :c(index), D(0x9c5a203a)
+ );
+ return result;
}
-
void wrmsr_amd(u32 index, msr_t msr)
{
- __asm__ __volatile__ (
+ __asm__ __volatile__(
wrmsr
- : /* No outputs */
- : c (index), a (msr.lo), d (msr.hi), D (0x9c5a203a)
- );
+ : /* No outputs */
+ :c(index), a(msr.lo), d(msr.hi), D(0x9c5a203a)
+ );
}
-
static void model_10xxx_init(device_t dev)
{
u8 i;
@@ -72,7 +70,7 @@
u32 siblings;
#endif
- id = get_node_core_id(read_nb_cfg_54()); /* nb_cfg_54 can not be set */
+ id = get_node_core_id(read_nb_cfg_54());/* nb_cfg_54 can not be
set */
printk(BIOS_DEBUG, nodeid = %02d, coreid = %02d\n, id.nodeid,
id.coreid);
/* Turn on caching if we haven't already */
@@ -85,11 +83,10 @@
/* zero the machine check error status registers */
msr.lo = 0;
msr.hi = 0;
- for(i=0; i 5; i++) {
- wrmsr(MCI_STATUS + (i * 4),msr);
+ for (i = 0; i 5; i++) {
+ wrmsr(MCI_STATUS + (i * 4), msr);
}
-
enable_cache();
/* Enable the local cpu apics */
@@ -107,7 +104,7 @@
wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
- msr.hi |= 1 (33-32);
+ msr.hi |= 1 (33 - 32);
wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
}
printk(BIOS_DEBUG, siblings = %02d, , siblings);
@@ -115,7 +112,7 @@
/* DisableCf8ExtCfg */
msr = rdmsr(NB_CFG_MSR);
- msr.hi = ~(1 (46-32));
+ msr.hi = ~(1 (46 - 32));
wrmsr(NB_CFG_MSR, msr);
/* Write protect SMM space with SMMLOCK. */
@@ -128,6 +125,7 @@
static struct device_operations cpu_dev_ops = {
.init = model_10xxx_init,
};
+
static struct cpu_device_id cpu_table[] = {
//AMD_GH_SUPPORT
{ X86_VENDOR_AMD, 0x100f00 }, /* SH-F0 L1 */
@@ -144,7 +142,8 @@
{ X86_VENDOR_AMD, 0x100F80 }, /* HY-D0 */
{ 0, 0 },
};
+
static const struct cpu_driver model_10xxx __cpu_driver = {
- .ops = cpu_dev_ops,
+ .ops = cpu_dev_ops,
.id_table = cpu_table,
};
Modified: trunk/src/cpu/amd/model_fxx/model_fxx_init.c
==
--- trunk/src/cpu/amd/model_fxx/model_fxx_init.cFri Apr 9 05:41:23
2010(r5384)
+++ trunk/src/cpu/amd/model_fxx/model_fxx_init.cFri Apr 9 06:01:55
2010(r5385)
@@ -44,66 +44,66 @@
#if CONFIG_K8_REV_F_SUPPORT == 0
int is_e0_later_in_bsp(int nodeid)
{
-uint32_t val;
-uint32_t val_old;
-int e0_later;
-if(nodeid==0) { // we don't need to do that for node 0 in core0/node0
-return !is_cpu_pre_e0();
-}
-// d0 will be treated as e0 with this methods, but the d0 nb_cfg_54
always 0
-device_t dev;
-dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid,2));
-if(!dev) return 0;
-val_old = pci_read_config32(dev, 0x80);
-val = val_old;
-val |= (13);
-pci_write_config32(dev, 0x80, val);
-val = pci_read_config32(dev, 0x80);
-e0_later = !!(val (13));
-if(e0_later) { // pre_e0 bit 3 always be 0 and can not be changed
-pci_write_config32(dev, 0x80, val_old); // restore it
-}
+ uint32_t val;
+ uint32_t val_old;
+ int e0_later;
+ if (nodeid == 0) { // we don't need to do that for node 0 in
core0/node0
+ return !is_cpu_pre_e0();
+ }
+ // d0 will be treated as e0 with this methods, but the d0 nb_cfg_54
always 0
+ device_t dev;
+ dev = dev_find_slot(0, PCI_DEVFN(0x18 + nodeid, 2));
+ if (!dev)
Re: [coreboot] memset called to somewhere high on the stack (uncached)
On Tue, Apr 6, 2010 at 4:21 PM, Myles Watson myle...@gmail.com wrote: I'm seeing code reads to memset() in coreboot_ram interleaved with byte writes to somewhere high on the stack (_estack -0x1fC). This is a k8. It turns out init_processor_name() was being called with the cache disabled. It doesn't look like it needs to be. Boot tested on my box. This makes it more similar to model_10. Signed-off-by: Myles Watson myle...@gmail.com Thanks, Myles Index: svn/src/cpu/amd/model_fxx/model_fxx_init.c === --- svn.orig/src/cpu/amd/model_fxx/model_fxx_init.c +++ svn/src/cpu/amd/model_fxx/model_fxx_init.c @@ -515,11 +515,11 @@ static void model_fxx_init(device_t dev) msr.lo |= (1 0); wrmsr(HWCR_MSR, msr); + enable_cache(); + /* Set the processor name string */ init_processor_name(); - enable_cache(); - /* Enable the local cpu apics */ setup_lapic(); -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
