[coreboot] Error downloading source
[...@smitty2m ~]$ svn co svn://coreboot.org/coreboot/trunk coreboot svn: Can't find a temporary directory: Internal error Googling around it looks like eithor /tmp on the server is not writable or the diskspace is full. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Dualbios on GA-MA770-UD3
Hello, Sorry for my bad english. I'm going to try coreboot on Gigabyte GA-MA770-UD3. It's AMD 770 (RX780 / SB700). I've prepared the image for it based on code for mahogany fam10 with some modifications. I've tried it with simnow using the configuration close to mine as much as possible - it even boots with my native BIOS. And it boots with coreboot image. My motherboard supports hardware dual bios - with two chips on it. I'm going to try flashing backup chip and boot from it. It seems to be possible - I've tested it (flashing at least). Chips on this board could be switched by changing bit 0 at undocumented register EF on LDN 7 of IT8720. I can use slightly patched flashrom for accessing any chip I want without any problems. And this is tested many times. My idea is to use backup chip for debugging - that always keeps my chance to reboot from main bios chip. And removes the need for desoldering etc. But the problems are when I'm trying to boot - and I expected them. It seems that after warm reboot it is trying to boot from selected chip as I want, but reboots againg in a second. AFAIK there is some hardware watchdog on these dualbios motherboards. There are many possibilities - northbridge, southbridge, superio. My main question is - is anybody working on it or may be have some info on it. I definitely will find the way to turn the watchdog off but may be somebody already did that? And second problem is that original bios is checking second chip - and trying to recover it by flashing the bios from main chip on reboot? rewriting coreboot. AFAICS this could be solved by including some signatures etc. It seems to be easy to find out. May be someone is working on this? BTW I can send the patch for flashrom - but I think that with information I mentioned above somebody could make it much better than my ugly hack. I hope the regs should be the same for all latest Gigabyte MBs using IT8720/18 Please, post any info you have that can help me. -- Best regards, Vadim Girlin -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r5386 - in trunk/src: arch/i386/include/arch arch/i386/init cpu/amd/car cpu/x86/car
Author: stepan Date: Fri Apr 9 12:12:18 2010 New Revision: 5386 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5386 Log: thin out romcc epilogue and have it call copy_and_run as all the others do. Make sure copy_and_run is called with the right calling convention. Fix up 2 license headers. Signed-off-by: Stefan Reinauer ste...@coresystems.de Acked-by: Stefan Reinauer ste...@coresystems.de Modified: trunk/src/arch/i386/include/arch/acpi.h trunk/src/arch/i386/init/crt0_prologue.inc trunk/src/arch/i386/init/crt0_romcc_epilogue.inc trunk/src/cpu/amd/car/copy_and_run.c trunk/src/cpu/x86/car/copy_and_run.c Modified: trunk/src/arch/i386/include/arch/acpi.h == --- trunk/src/arch/i386/include/arch/acpi.h Fri Apr 9 06:01:55 2010 (r5385) +++ trunk/src/arch/i386/include/arch/acpi.h Fri Apr 9 12:12:18 2010 (r5386) @@ -407,7 +407,6 @@ void suspend_resume(void); void *acpi_find_wakeup_vector(void); void *acpi_get_wakeup_rsdp(void); -void acpi_jmp_to_realm_wakeup(u32 linear_addr) __attribute__((regparm(0))); void acpi_jump_to_wakeup(void *wakeup_addr); int acpi_get_sleep_type(void); Modified: trunk/src/arch/i386/init/crt0_prologue.inc == --- trunk/src/arch/i386/init/crt0_prologue.inc Fri Apr 9 06:01:55 2010 (r5385) +++ trunk/src/arch/i386/init/crt0_prologue.inc Fri Apr 9 12:12:18 2010 (r5386) @@ -3,8 +3,7 @@ * * This file is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. + * published by the Free Software Foundation; version 2 of the License. */ Modified: trunk/src/arch/i386/init/crt0_romcc_epilogue.inc == --- trunk/src/arch/i386/init/crt0_romcc_epilogue.incFri Apr 9 06:01:55 2010(r5385) +++ trunk/src/arch/i386/init/crt0_romcc_epilogue.incFri Apr 9 12:12:18 2010(r5386) @@ -1,124 +1,27 @@ -/* -*- asm -*- - * $ $ - * - */ - /* - * Copyright (C) 1996-2002 Markus Franz Xaver Johannes Oberhumer + * Copyright 2002 Eric Biederman * * This file is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * Originally this code was part of ucl the data compression library - * for upx the ``Ultimate Packer of eXecutables''. - * - * - Converted to gas assembly, and refitted to work with etherboot. - * Eric Biederman 20 Aug 2002 - * - Merged the nrv2b decompressor into crt0.base of coreboot - * Eric Biederman 26 Sept 2002 + * published by the Free Software Foundation; version 2 of the License. */ - -#ifndef CONSOLE_DEBUG_TX_STRING - /* uses: esp, ebx, ax, dx */ -# define __CRT_CONSOLE_TX_STRING(string) \ - mov string, %ebx; \ - CALLSP(crt_console_tx_string) - -# if defined(CONFIG_TTYS0_BASE) (ASM_CONSOLE_LOGLEVEL BIOS_DEBUG) -# define CONSOLE_DEBUG_TX_STRING(string) __CRT_CONSOLE_TX_STRING(string) -# else -# define CONSOLE_DEBUG_TX_STRING(string) -# endif -#endif - /* clear boot_complete flag */ xorl%ebp, %ebp __main: - CONSOLE_DEBUG_TX_STRING($str_copying_to_ram) - - /* -* Copy data into RAM and clear the BSS. Since these segments -* isn\'t really that big we just copy/clear using bytes, not -* double words. -*/ - post_code(0x11) /* post 11 */ - - cld /* clear direction flag */ + post_code(0x11) + cld /* clear direction flag */ - /* copy coreboot from it's initial load location to -* the location it is compiled to run at. -* Normally this is copying from FLASH ROM to RAM. -*/ movl%ebp, %esi + /* FIXME: look for a proper place for the stack */ movl$0x400, %esp movl%esp, %ebp pushl %esi - pushl $str_coreboot_ram_name - call cbfs_and_run_core + call copy_and_run .Lhlt: - post_code(0xee) /* post fe */ + post_code(0xee) hlt jmp .Lhlt -#ifdef __CRT_CONSOLE_TX_STRING - /* Uses esp, ebx, ax, dx */ -crt_console_tx_string: - mov (%ebx), %al - inc %ebx - cmp $0, %al - jne 9f - RETSP -9: -/* Base Address */ -#ifndef CONFIG_TTYS0_BASE -#define CONFIG_TTYS0_BASE 0x3f8 -#endif -/* Data */ -#define TTYS0_RBR (CONFIG_TTYS0_BASE+0x00) - -/* Control */ -#define TTYS0_TBR TTYS0_RBR -#define TTYS0_IER
[coreboot] build service results for r5386
Dear coreboot readers! This is the automatic build system of coreboot. The developer stepan checked in revision 5386 to the coreboot repository. This caused the following changes: Change Log: thin out romcc epilogue and have it call copy_and_run as all the others do. Make sure copy_and_run is called with the right calling convention. Fix up 2 license headers. Signed-off-by: Stefan Reinauer ste...@coresystems.de Acked-by: Stefan Reinauer ste...@coresystems.de Build Log: Compilation of a-trend:atc-6220 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5386device=atc-6220vendor=a-trendnum=2 Compilation of a-trend:atc-6240 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5386device=atc-6240vendor=a-trendnum=2 Compilation of abit:be6-ii_v2_0 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5386device=be6-ii_v2_0vendor=abitnum=2 Compilation of advantech:pcm-5820 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5386device=pcm-5820vendor=advantechnum=2 Compilation of amd:rumba has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5386device=rumbavendor=amdnum=2 Compilation of asi:mb_5blgp has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5386device=mb_5blgpvendor=asinum=2 Compilation of asi:mb_5blmp has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5386device=mb_5blmpvendor=asinum=2 Compilation of asus:mew-am has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5386device=mew-amvendor=asusnum=2 Compilation of asus:mew-vm has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5386device=mew-vmvendor=asusnum=2 Compilation of asus:p2b has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5386device=p2bvendor=asusnum=2 Compilation of asus:p2b-d has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5386device=p2b-dvendor=asusnum=2 Compilation of asus:p2b-ds has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5386device=p2b-dsvendor=asusnum=2 Compilation of asus:p2b-f has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5386device=p2b-fvendor=asusnum=2 Compilation of asus:p2b-ls has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5386device=p2b-lsvendor=asusnum=2 Compilation of asus:p3b-f has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5386device=p3b-fvendor=asusnum=2 Compilation of axus:tc320 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5386device=tc320vendor=axusnum=2 Compilation of azza:pt-6ibd has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5386device=pt-6ibdvendor=azzanum=2 Compilation of bcom:winnet100 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5386device=winnet100vendor=bcomnum=2 Compilation of biostar:m6tba has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5386device=m6tbavendor=biostarnum=2 Compilation of compaq:deskpro_en_sff_p600 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5386device=deskpro_en_sff_p600vendor=compaqnum=2 Compilation of dell:s1850 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5386device=s1850vendor=dellnum=2 Compilation of digitallogic:adl855pc has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5386device=adl855pcvendor=digitallogicnum=2 Compilation of digitallogic:msm586seg has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5386device=msm586segvendor=digitallogicnum=2 Compilation of eaglelion:5bcm has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5386device=5bcmvendor=eaglelionnum=2 Compilation of emulation:qemu-x86 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5386device=qemu-x86vendor=emulationnum=2 Compilation of gigabyte:ga-6bxc has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5386device=ga-6bxcvendor=gigabytenum=2 Compilation of hp:e_vectra_p2706t has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5386device=e_vectra_p2706tvendor=hpnum=2 Compilation of iei:juki-511p has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5386device=juki-511pvendor=ieinum=2 Compilation of iei:nova4899r has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5386device=nova4899rvendor=ieinum=2 Compilation of intel:jarrell has been broken See the error
[coreboot] [commit] r5387 - in trunk/src: arch/i386/lib cpu/amd/car cpu/intel/model_106cx cpu/intel/model_6ex cpu/intel/model_6fx cpu/x86/car mainboard/amd/dbm690t mainboard/amd/mahogany mainboard/amd
Author: stepan
Date: Fri Apr 9 12:43:49 2010
New Revision: 5387
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5387
Log:
copy_and_run.c is not needed twice, and it is used on non-car too.
So move it to src/arch/i386/lib/cbfs_and_run.c
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by: Stefan Reinauer ste...@coresystems.de
Deleted:
trunk/src/cpu/amd/car/copy_and_run.c
trunk/src/cpu/x86/car/copy_and_run.c
Modified:
trunk/src/arch/i386/lib/cbfs_and_run.c
trunk/src/cpu/intel/model_106cx/cache_as_ram_disable.c
trunk/src/cpu/intel/model_6ex/cache_as_ram_disable.c
trunk/src/cpu/intel/model_6fx/cache_as_ram_disable.c
trunk/src/mainboard/amd/dbm690t/romstage.c
trunk/src/mainboard/amd/mahogany/romstage.c
trunk/src/mainboard/amd/mahogany_fam10/romstage.c
trunk/src/mainboard/amd/pistachio/romstage.c
trunk/src/mainboard/amd/serengeti_cheetah/romstage.c
trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
trunk/src/mainboard/arima/hdama/romstage.c
trunk/src/mainboard/asrock/939a785gmh/romstage.c
trunk/src/mainboard/asus/a8n_e/romstage.c
trunk/src/mainboard/asus/a8v-e_se/romstage.c
trunk/src/mainboard/asus/m2v-mx_se/romstage.c
trunk/src/mainboard/broadcom/blast/romstage.c
trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
trunk/src/mainboard/gigabyte/m57sli/romstage.c
trunk/src/mainboard/hp/dl145_g3/romstage.c
trunk/src/mainboard/ibm/e325/romstage.c
trunk/src/mainboard/ibm/e326/romstage.c
trunk/src/mainboard/iwill/dk8_htx/romstage.c
trunk/src/mainboard/iwill/dk8s2/romstage.c
trunk/src/mainboard/iwill/dk8x/romstage.c
trunk/src/mainboard/kontron/kt690/romstage.c
trunk/src/mainboard/msi/ms7135/romstage.c
trunk/src/mainboard/msi/ms7260/romstage.c
trunk/src/mainboard/msi/ms9185/romstage.c
trunk/src/mainboard/msi/ms9282/romstage.c
trunk/src/mainboard/msi/ms9652_fam10/romstage.c
trunk/src/mainboard/newisys/khepri/romstage.c
trunk/src/mainboard/nvidia/l1_2pvv/romstage.c
trunk/src/mainboard/sunw/ultra40/romstage.c
trunk/src/mainboard/supermicro/h8dme/romstage.c
trunk/src/mainboard/supermicro/h8dmr/romstage.c
trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c
trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c
trunk/src/mainboard/technexion/tim5690/romstage.c
trunk/src/mainboard/technexion/tim8690/romstage.c
trunk/src/mainboard/tyan/s2735/romstage.c
trunk/src/mainboard/tyan/s2850/romstage.c
trunk/src/mainboard/tyan/s2875/romstage.c
trunk/src/mainboard/tyan/s2880/romstage.c
trunk/src/mainboard/tyan/s2881/romstage.c
trunk/src/mainboard/tyan/s2882/romstage.c
trunk/src/mainboard/tyan/s2885/romstage.c
trunk/src/mainboard/tyan/s2891/romstage.c
trunk/src/mainboard/tyan/s2892/romstage.c
trunk/src/mainboard/tyan/s2895/romstage.c
trunk/src/mainboard/tyan/s2912/romstage.c
trunk/src/mainboard/tyan/s2912_fam10/romstage.c
trunk/src/mainboard/tyan/s4880/romstage.c
trunk/src/mainboard/tyan/s4882/romstage.c
trunk/src/mainboard/via/epia-m700/romstage.c
trunk/src/mainboard/via/vt8454c/romstage.c
trunk/src/northbridge/via/vx800/examples/romstage.c
Modified: trunk/src/arch/i386/lib/cbfs_and_run.c
==
--- trunk/src/arch/i386/lib/cbfs_and_run.c Fri Apr 9 12:12:18 2010
(r5386)
+++ trunk/src/arch/i386/lib/cbfs_and_run.c Fri Apr 9 12:43:49 2010
(r5387)
@@ -40,3 +40,21 @@
:: a(ebp), D(dst)
);
}
+
+void __attribute__((regparm(0))) copy_and_run(unsigned cpu_reset);
+
+void __attribute__((regparm(0))) copy_and_run(unsigned cpu_reset)
+{
+ // FIXME fix input parameters instead normalizing them here.
+ if (cpu_reset == 1) cpu_reset = -1;
+ else cpu_reset = 0;
+
+ cbfs_and_run_core(CONFIG_CBFS_PREFIX /coreboot_ram, cpu_reset);
+}
+
+#if CONFIG_AP_CODE_IN_CAR == 1
+static void __attribute__((regparm(0))) copy_and_run_ap_code_in_car(unsigned
ret_addr)
+{
+ cbfs_and_run_core(CONFIG_CBFS_PREFIX /coreboot_ap, ret_addr);
+}
+#endif
Modified: trunk/src/cpu/intel/model_106cx/cache_as_ram_disable.c
==
--- trunk/src/cpu/intel/model_106cx/cache_as_ram_disable.c Fri Apr 9
12:12:18 2010(r5386)
+++ trunk/src/cpu/intel/model_106cx/cache_as_ram_disable.c Fri Apr 9
12:43:49 2010(r5387)
@@ -17,7 +17,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#include cpu/x86/car/copy_and_run.c
+
/* called from assembler code */
void stage1_main(unsigned long bist);
Modified: trunk/src/cpu/intel/model_6ex/cache_as_ram_disable.c
==
--- trunk/src/cpu/intel/model_6ex/cache_as_ram_disable.cFri Apr 9
12:12:18 2010(r5386)
+++ trunk/src/cpu/intel/model_6ex/cache_as_ram_disable.cFri
Re: [coreboot] password
Hi Ron, Thinkpads has special EEPROM for password 24RF08 http://www.allservice.ro/store/utils/index.htm Hook it and use that software to read it. I think it is stored as scan codes. WARNING! this eeprom has hardware bug! Avoid ANY write short transactions. All transactions which just sends Start cond, addr and R/W, Stop cond will not work! There is a bug in state machine which causes to ignore the stop conditions making the further probing as chip writes. The BIOS is very very pissed off if the EEPROM is corrupted. Cleaning the eeprom is not enough because it sets the HDD password! Carefull with that! Check also: http://www.thinkwiki.org/wiki/Maintenance recovering bios passwords For X300 above is also true, I think you can check the testpoints http://www.allservice.ro/forum/viewtopic.php?t=52 http://www.allservice.ro/forum/images/x300.jpg Good luck, Rudolf Rudolf -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] memset called to somewhere high on the stack (uncached)
Does this interfere with suspend/resume? Is there a ticket already created for this? It looks like something that would be hard to debug in system. It does, but I ignore that because I think this code is not used when CAR is used? Rudolf -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] build service results for r5387
Dear coreboot readers! This is the automatic build system of coreboot. The developer stepan checked in revision 5387 to the coreboot repository. This caused the following changes: Change Log: copy_and_run.c is not needed twice, and it is used on non-car too. So move it to src/arch/i386/lib/cbfs_and_run.c Signed-off-by: Stefan Reinauer ste...@coresystems.de Acked-by: Stefan Reinauer ste...@coresystems.de Build Log: Compilation of a-trend:atc-6220 has been fixed Compilation of a-trend:atc-6240 has been fixed Compilation of abit:be6-ii_v2_0 has been fixed Compilation of advantech:pcm-5820 has been fixed Compilation of amd:rumba has been fixed Compilation of asi:mb_5blgp has been fixed Compilation of asi:mb_5blmp has been fixed Compilation of asus:mew-am has been fixed Compilation of asus:mew-vm has been fixed Compilation of asus:p2b has been fixed Compilation of asus:p2b-d has been fixed Compilation of asus:p2b-ds has been fixed Compilation of asus:p2b-f has been fixed Compilation of asus:p2b-ls has been fixed Compilation of asus:p3b-f has been fixed Compilation of axus:tc320 has been fixed Compilation of azza:pt-6ibd has been fixed Compilation of bcom:winnet100 has been fixed Compilation of biostar:m6tba has been fixed Compilation of compaq:deskpro_en_sff_p600 has been fixed Compilation of dell:s1850 has been fixed Compilation of digitallogic:adl855pc has been fixed Compilation of digitallogic:msm586seg has been fixed Compilation of eaglelion:5bcm has been fixed Compilation of emulation:qemu-x86 has been fixed Compilation of gigabyte:ga-6bxc has been fixed Compilation of hp:e_vectra_p2706t has been fixed Compilation of iei:juki-511p has been fixed Compilation of iei:nova4899r has been fixed Compilation of intel:jarrell has been fixed Compilation of intel:mtarvon has been fixed Compilation of intel:truxton has been fixed Compilation of intel:xe7501devkit has been fixed Compilation of lippert:frontrunner has been fixed Compilation of mitac:6513wu has been fixed Compilation of msi:ms6119 has been fixed Compilation of msi:ms6147 has been fixed Compilation of msi:ms6156 has been fixed Compilation of msi:ms6178 has been fixed Compilation of nec:powermate2000 has been fixed Compilation of olpc:btest has been fixed Compilation of olpc:rev_a has been fixed Compilation of rca:rm4100 has been fixed Compilation of soyo:sy-6ba-plus-iii has been fixed Compilation of supermicro:x6dai_g has been fixed Compilation of supermicro:x6dhe_g has been fixed Compilation of supermicro:x6dhe_g2 has been fixed Compilation of supermicro:x6dhr_ig has been fixed Compilation of supermicro:x6dhr_ig2 has been fixed Compilation of technologic:ts5300 has been fixed Compilation of televideo:tc7020 has been fixed Compilation of thomson:ip1000 has been fixed Compilation of tyan:s1846 has been fixed Compilation of via:epia has been fixed Compilation of via:epia-cn has been fixed Compilation of via:epia-m has been fixed Compilation of via:epia-n has been fixed Compilation of via:pc2500e has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r5388 - in trunk/src: arch/i386 arch/i386/include/arch arch/i386/lib cpu/intel cpu/intel/model_6bx cpu/intel/model_6ex cpu/intel/socket_mFCBGA479 include mainboard/rca/rm4100 mainb
Author: stepan
Date: Fri Apr 9 13:10:25 2010
New Revision: 5388
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5388
Log:
1. This patch adds CAR for Intel P6 series processors.
2. Add support for Micro-FCBGA 479 Celeron and PIII's
3. Add support for model_6bx and microcode updates
4. Add support for CAR and Tinybootblock on RCA RM4100 and Thomson
IP1000
Build and boot tested.
Signed-off-by: Joseph Smith j...@settoplinux.org
The change to CAR reveiled a few more warnings in the ICH4 and i830 code,
I fixed them on the fly.
Checking this in because my last two commits broke Joseph's CAR patch. This
version fixes the issues.
Acked-by: Stefan Reinauer ste...@coresystems.de
Added:
trunk/src/arch/i386/include/arch/stages.h
trunk/src/cpu/intel/model_6bx/
trunk/src/cpu/intel/model_6bx/Kconfig
trunk/src/cpu/intel/model_6bx/Makefile.inc
trunk/src/cpu/intel/model_6bx/cache_as_ram_disable.c
trunk/src/cpu/intel/model_6bx/microcode-737-MU16b11c.h
trunk/src/cpu/intel/model_6bx/microcode-738-MU16b11d.h
trunk/src/cpu/intel/model_6bx/microcode-875-MU16b401.h
trunk/src/cpu/intel/model_6bx/microcode-885-MU16b402.h
trunk/src/cpu/intel/model_6bx/model_6bx_init.c
trunk/src/cpu/intel/socket_mFCBGA479/
trunk/src/cpu/intel/socket_mFCBGA479/Kconfig
trunk/src/cpu/intel/socket_mFCBGA479/Makefile.inc
trunk/src/cpu/intel/socket_mFCBGA479/chip.h
trunk/src/cpu/intel/socket_mFCBGA479/socket_mFCBGA479.c
Modified:
trunk/src/arch/i386/Makefile.inc
trunk/src/arch/i386/lib/cbfs_and_run.c
trunk/src/cpu/intel/Kconfig
trunk/src/cpu/intel/Makefile.inc
trunk/src/cpu/intel/model_6ex/cache_as_ram_disable.c
trunk/src/include/cbfs.h
trunk/src/mainboard/rca/rm4100/Kconfig
trunk/src/mainboard/rca/rm4100/Makefile.inc
trunk/src/mainboard/rca/rm4100/devicetree.cb
trunk/src/mainboard/rca/rm4100/romstage.c
trunk/src/mainboard/thomson/ip1000/Kconfig
trunk/src/mainboard/thomson/ip1000/Makefile.inc
trunk/src/mainboard/thomson/ip1000/devicetree.cb
trunk/src/mainboard/thomson/ip1000/romstage.c
trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c
trunk/src/northbridge/intel/i82830/raminit.c
trunk/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c
trunk/src/southbridge/intel/i82801dx/i82801dx_tco_timer.c
Modified: trunk/src/arch/i386/Makefile.inc
==
--- trunk/src/arch/i386/Makefile.incFri Apr 9 12:43:49 2010(r5387)
+++ trunk/src/arch/i386/Makefile.incFri Apr 9 13:10:25 2010(r5388)
@@ -165,6 +165,9 @@
ifeq ($(CONFIG_CPU_INTEL_SOCKET_BGA956),y)
crt0s += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
endif
+ifeq ($(CONFIG_CPU_INTEL_SOCKET_MFCBGA479),y)
+crt0s += $(src)/cpu/x86/car/cache_as_ram.inc
+endif
# should be CONFIG_CPU_VIA_C7, but bcom/winnetp680, jetway/j7f24, via/epia-cn,
via/pc2500e don't use CAR yet
ifeq ($(CONFIG_BOARD_VIA_VT8454C),y)
crt0s += $(src)/cpu/via/car/cache_as_ram.inc
Added: trunk/src/arch/i386/include/arch/stages.h
==
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ trunk/src/arch/i386/include/arch/stages.h Fri Apr 9 13:10:25 2010
(r5388)
@@ -0,0 +1,5 @@
+void cbfs_and_run_core(const char *filename, unsigned int ebp);
+void __attribute__((regparm(0))) copy_and_run(unsigned cpu_reset);
+void __attribute__((regparm(0))) copy_and_run_ap_code_in_car(unsigned
ret_addr);
+
+
Modified: trunk/src/arch/i386/lib/cbfs_and_run.c
==
--- trunk/src/arch/i386/lib/cbfs_and_run.c Fri Apr 9 12:43:49 2010
(r5387)
+++ trunk/src/arch/i386/lib/cbfs_and_run.c Fri Apr 9 13:10:25 2010
(r5388)
@@ -19,6 +19,7 @@
#include console/console.h
#include cbfs.h
+#include arch/stages.h
void cbfs_and_run_core(const char *filename, unsigned ebp)
{
@@ -41,8 +42,6 @@
);
}
-void __attribute__((regparm(0))) copy_and_run(unsigned cpu_reset);
-
void __attribute__((regparm(0))) copy_and_run(unsigned cpu_reset)
{
// FIXME fix input parameters instead normalizing them here.
@@ -53,7 +52,7 @@
}
#if CONFIG_AP_CODE_IN_CAR == 1
-static void __attribute__((regparm(0))) copy_and_run_ap_code_in_car(unsigned
ret_addr)
+void __attribute__((regparm(0))) copy_and_run_ap_code_in_car(unsigned ret_addr)
{
cbfs_and_run_core(CONFIG_CBFS_PREFIX /coreboot_ap, ret_addr);
}
Modified: trunk/src/cpu/intel/Kconfig
==
--- trunk/src/cpu/intel/Kconfig Fri Apr 9 12:43:49 2010(r5387)
+++ trunk/src/cpu/intel/Kconfig Fri Apr 9 13:10:25 2010(r5388)
@@ -1,6 +1,7 @@
# CPU models
source src/cpu/intel/model_6xx/Kconfig
source src/cpu/intel/model_69x/Kconfig
+source src/cpu/intel/model_6bx/Kconfig
source src/cpu/intel/model_6dx/Kconfig
source
Re: [coreboot] [PATCH] CAR on Intel P6 Series - Support for model_6bx
On 4/8/10 8:09 AM, Joseph Smith wrote: Hello, 1. This patch adds CAR for Intel P6 series processors. 2. Add support for Micro-FCBGA 479 Celeron and PIII's 3. Add support for model_6bx and microcode updates 4. Add support for CAR and Tinybootblock on RCA RM4100 and Thomson IP1000 Build and boot tested (bootlog attached). Signed-off-by: Joseph Smith j...@settoplinux.org Thanks, r5388. -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [commit] r5330 - in trunk: . src/arch/i386
Myles Watson myle...@gmail.com writes: On Tue, Mar 30, 2010 at 2:32 PM, repository service s...@coreboot.org wrote: Author: stepan Date: Tue Mar 30 22:32:01 2010 New Revision: 5330 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5330 Log: make crt0s and ldscripts evaluate late, so the chipset_* variables are there at the time they are finally used. This should solve the Problem Myles was seeing earlier today. It does. Hm, this only seems to be effective if CONFIG_BIG_BOOTBLOCK is set. Not sure why? The s2912_fam10 mainboard had TINY_BOOTBLOCK set, and stopped working when I updated today. I'm not sure why that is, either, but I see both the serengeti_fam10 and mahogany_fam10 mainboards have it set as well. I made a quick attempt at fixing this, but ran into linker script problems like: .../crossgcc/xgcc/bin/../lib/gcc/i386-elf/4.4.2/../../../../i386-elf/bin/ld: section .id loaded at [ff61,ff7f] overlaps section .rom loaded at [,00010cdf] .../crossgcc/xgcc/bin/../lib/gcc/i386-elf/4.4.2/../../../../i386-elf/bin/ld: build/coreboot: section .id vma 0xff61 overlaps previous sections .../crossgcc/xgcc/bin/../lib/gcc/i386-elf/4.4.2/../../../../i386-elf/bin/ld: build/coreboot: section .romstrap vma 0xffa0 overlaps previous sections .../crossgcc/xgcc/bin/../lib/gcc/i386-elf/4.4.2/../../../../i386-elf/bin/ld: build/coreboot: section .reset vma 0xfff0 overlaps previous sections .../crossgcc/xgcc/bin/../lib/gcc/i386-elf/4.4.2/../../../../i386-elf/bin/ld: build/coreboot: section .text vma 0x10d00 overlaps previous sections collect2: ld returned 1 exit status which I didn't really have the time to pursue. I'm reverting my local checkout for now. If anyone has pointers regarding how to resolve this, I'd be happy to hear them. -- Arne. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [commit] r5330 - in trunk: . src/arch/i386
On 4/9/10 1:21 PM, Arne Georg Gleditsch wrote: Myles Watson myle...@gmail.com writes: On Tue, Mar 30, 2010 at 2:32 PM, repository service s...@coreboot.org wrote: Author: stepan Date: Tue Mar 30 22:32:01 2010 New Revision: 5330 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5330 Log: make crt0s and ldscripts evaluate late, so the chipset_* variables are there at the time they are finally used. This should solve the Problem Myles was seeing earlier today. It does. Hm, this only seems to be effective if CONFIG_BIG_BOOTBLOCK is set. Not sure why? The s2912_fam10 mainboard had TINY_BOOTBLOCK set, and stopped working when I updated today. I'm not sure why that is, either, but I see both the serengeti_fam10 and mahogany_fam10 mainboards have it set as well. I made a quick attempt at fixing this, but ran into linker script problems like: .../crossgcc/xgcc/bin/../lib/gcc/i386-elf/4.4.2/../../../../i386-elf/bin/ld: section .id loaded at [ff61,ff7f] overlaps section .rom loaded at [,00010cdf] .../crossgcc/xgcc/bin/../lib/gcc/i386-elf/4.4.2/../../../../i386-elf/bin/ld: build/coreboot: section .id vma 0xff61 overlaps previous sections .../crossgcc/xgcc/bin/../lib/gcc/i386-elf/4.4.2/../../../../i386-elf/bin/ld: build/coreboot: section .romstrap vma 0xffa0 overlaps previous sections .../crossgcc/xgcc/bin/../lib/gcc/i386-elf/4.4.2/../../../../i386-elf/bin/ld: build/coreboot: section .reset vma 0xfff0 overlaps previous sections .../crossgcc/xgcc/bin/../lib/gcc/i386-elf/4.4.2/../../../../i386-elf/bin/ld: build/coreboot: section .text vma 0x10d00 overlaps previous sections collect2: ld returned 1 exit status which I didn't really have the time to pursue. I'm reverting my local checkout for now. If anyone has pointers regarding how to resolve this, I'd be happy to hear them. What was your local patch? -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] memset called to somewhere high on the stack (uncached)
On 4/9/10 12:47 PM, Rudolf Marek wrote: Does this interfere with suspend/resume? Is there a ticket already created for this? It looks like something that would be hard to debug in system. It does, but I ignore that because I think this code is not used when CAR is used? On intel core / core 2 we use CONFIG_RAMBASE + HIGH_MEMORY_SAFE for the stack, so it lives in the area we are backing up (and thus are allowed to overwrite) This needs much cleanup but check src/cpu/intel/model_6ex/cache_as_ram_disable.c Stefan -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r5389 - in trunk/src: northbridge/intel/i440bx northbridge/intel/i440lx northbridge/intel/i82810 northbridge/intel/i82830 northbridge/via/cn400 northbridge/via/cn700 northbridge/vi
Author: stepan
Date: Fri Apr 9 13:34:59 2010
New Revision: 5389
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5389
Log:
zero warning days.
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by: Stefan Reinauer ste...@coresystems.de
Modified:
trunk/src/northbridge/intel/i440bx/raminit.c
trunk/src/northbridge/intel/i440lx/raminit.c
trunk/src/northbridge/intel/i82810/raminit.c
trunk/src/northbridge/intel/i82830/raminit.c
trunk/src/northbridge/via/cn400/raminit.c
trunk/src/northbridge/via/cn700/raminit.c
trunk/src/northbridge/via/cx700/raminit.c
trunk/src/northbridge/via/vx800/raminit.c
trunk/src/southbridge/amd/rs690/rs690_gfx.c
trunk/src/southbridge/amd/sb600/sb600_reset.c
trunk/src/southbridge/amd/sb700/sb700_early_setup.c
Modified: trunk/src/northbridge/intel/i440bx/raminit.c
==
--- trunk/src/northbridge/intel/i440bx/raminit.cFri Apr 9 13:10:25
2010(r5388)
+++ trunk/src/northbridge/intel/i440bx/raminit.cFri Apr 9 13:34:59
2010(r5389)
@@ -20,7 +20,6 @@
*/
#include spd.h
-#include sdram_mode.h
#include delay.h
#include stdlib.h
#include i440bx.h
Modified: trunk/src/northbridge/intel/i440lx/raminit.c
==
--- trunk/src/northbridge/intel/i440lx/raminit.cFri Apr 9 13:10:25
2010(r5388)
+++ trunk/src/northbridge/intel/i440lx/raminit.cFri Apr 9 13:34:59
2010(r5389)
@@ -20,7 +20,6 @@
*/
#include spd.h
-#include sdram_mode.h
#include delay.h
#include stdlib.h
#include i440lx.h
Modified: trunk/src/northbridge/intel/i82810/raminit.c
==
--- trunk/src/northbridge/intel/i82810/raminit.cFri Apr 9 13:10:25
2010(r5388)
+++ trunk/src/northbridge/intel/i82810/raminit.cFri Apr 9 13:34:59
2010(r5389)
@@ -21,7 +21,6 @@
*/
#include spd.h
-#include sdram_mode.h
#include delay.h
#include i82810.h
Modified: trunk/src/northbridge/intel/i82830/raminit.c
==
--- trunk/src/northbridge/intel/i82830/raminit.cFri Apr 9 13:10:25
2010(r5388)
+++ trunk/src/northbridge/intel/i82830/raminit.cFri Apr 9 13:34:59
2010(r5389)
@@ -20,7 +20,6 @@
*/
#include spd.h
-#include sdram_mode.h
#include delay.h
#include lib/debug.c
#include i82830.h
Modified: trunk/src/northbridge/via/cn400/raminit.c
==
--- trunk/src/northbridge/via/cn400/raminit.c Fri Apr 9 13:10:25 2010
(r5388)
+++ trunk/src/northbridge/via/cn400/raminit.c Fri Apr 9 13:34:59 2010
(r5389)
@@ -29,7 +29,6 @@
/* ported from Via VT8263 Code*/
#include spd.h
-#include sdram_mode.h
#include delay.h
#include cpu/x86/mtrr.h
#include cn400.h
Modified: trunk/src/northbridge/via/cn700/raminit.c
==
--- trunk/src/northbridge/via/cn700/raminit.c Fri Apr 9 13:10:25 2010
(r5388)
+++ trunk/src/northbridge/via/cn700/raminit.c Fri Apr 9 13:34:59 2010
(r5389)
@@ -21,7 +21,6 @@
*/
#include spd.h
-#include sdram_mode.h
#include delay.h
#include cn700.h
Modified: trunk/src/northbridge/via/cx700/raminit.c
==
--- trunk/src/northbridge/via/cx700/raminit.c Fri Apr 9 13:10:25 2010
(r5388)
+++ trunk/src/northbridge/via/cx700/raminit.c Fri Apr 9 13:34:59 2010
(r5389)
@@ -20,7 +20,6 @@
#include types.h
#include spd.h
#include spd_ddr2.h
-#include sdram_mode.h
#include delay.h
#include cx700_registers.h
Modified: trunk/src/northbridge/via/vx800/raminit.c
==
--- trunk/src/northbridge/via/vx800/raminit.c Fri Apr 9 13:10:25 2010
(r5388)
+++ trunk/src/northbridge/via/vx800/raminit.c Fri Apr 9 13:34:59 2010
(r5389)
@@ -18,7 +18,6 @@
*/
#include spd.h
-#include sdram_mode.h
#include delay.h
#if CONFIG_DEBUG_RAM_SETUP
Modified: trunk/src/southbridge/amd/rs690/rs690_gfx.c
==
--- trunk/src/southbridge/amd/rs690/rs690_gfx.c Fri Apr 9 13:10:25 2010
(r5388)
+++ trunk/src/southbridge/amd/rs690/rs690_gfx.c Fri Apr 9 13:34:59 2010
(r5389)
@@ -34,6 +34,7 @@
#define CLK_CNTL_INDEX 0x8
#define CLK_CNTL_DATA 0xC
+#if 0
static u32 clkind_read(device_t dev, u32 index)
{
u32 gfx_bar2 = pci_read_config32(dev, 0x18) ~0xF;
@@ -41,6 +42,7 @@
*(u32*)(gfx_bar2+CLK_CNTL_INDEX) = index 0x7F;
return *(u32*)(gfx_bar2+CLK_CNTL_DATA);
}
+#endif
static void
[coreboot] [commit] r5390 - in trunk/src/arch/i386: init lib
Author: stepan Date: Fri Apr 9 13:37:58 2010 New Revision: 5390 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5390 Log: drop unused files, and we only use ASM_LOG_LEVEL in one file now (LX CAR) Signed-off-by: Stefan Reinauer ste...@coresystems.de Acked-by: Stefan Reinauer ste...@coresystems.de Deleted: trunk/src/arch/i386/lib/jmp_auto.inc trunk/src/arch/i386/lib/jmp_auto_out.inc trunk/src/arch/i386/lib/noop_failover.inc Modified: trunk/src/arch/i386/init/crt0_prologue.inc Modified: trunk/src/arch/i386/init/crt0_prologue.inc == --- trunk/src/arch/i386/init/crt0_prologue.inc Fri Apr 9 13:34:59 2010 (r5389) +++ trunk/src/arch/i386/init/crt0_prologue.inc Fri Apr 9 13:37:58 2010 (r5390) @@ -6,18 +6,13 @@ * published by the Free Software Foundation; version 2 of the License. */ - #include arch/asm.h #include arch/intel.h #include console/loglevel.h -#ifndef ASM_CONSOLE_LOGLEVEL -#define ASM_CONSOLE_LOGLEVEL CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -#endif - /* - * This is the entry code the code in .reset section - * jumps to this address. + * This is the entry code. + * The code in the .reset section jumps to this address. * */ .section .rom.data, a, @progbits -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r5391 - in trunk/src/mainboard/amd: dbm690t mahogany pistachio
Author: stepan
Date: Fri Apr 9 13:55:43 2010
New Revision: 5391
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5391
Log:
remove some amd mainboard warnings.
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by: Stefan Reinauer ste...@coresystems.de
Modified:
trunk/src/mainboard/amd/dbm690t/acpi_tables.c
trunk/src/mainboard/amd/dbm690t/mainboard.c
trunk/src/mainboard/amd/mahogany/get_bus_conf.c
trunk/src/mainboard/amd/pistachio/mainboard.c
Modified: trunk/src/mainboard/amd/dbm690t/acpi_tables.c
==
--- trunk/src/mainboard/amd/dbm690t/acpi_tables.c Fri Apr 9 13:37:58
2010(r5390)
+++ trunk/src/mainboard/amd/dbm690t/acpi_tables.c Fri Apr 9 13:55:43
2010(r5391)
@@ -92,8 +92,6 @@
return current;
}
-
-
static void update_ssdtx(void *ssdtx, int i)
{
uint8_t *PCI;
Modified: trunk/src/mainboard/amd/dbm690t/mainboard.c
==
--- trunk/src/mainboard/amd/dbm690t/mainboard.c Fri Apr 9 13:37:58 2010
(r5390)
+++ trunk/src/mainboard/amd/dbm690t/mainboard.c Fri Apr 9 13:55:43 2010
(r5391)
@@ -22,6 +22,7 @@
#include device/pci.h
#include arch/io.h
#include boot/coreboot_tables.h
+#include arch/coreboot_tables.h
#include cpu/x86/msr.h
#include cpu/amd/mtrr.h
#include device/pci_def.h
@@ -57,7 +58,7 @@
* RRG4.2.3.1 GPM pins as Input
* RRG4.2.3.2 GPM pins as Output
/
-static void enable_onboard_nic()
+static void enable_onboard_nic(void)
{
u8 byte;
@@ -94,7 +95,7 @@
* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to
* get the cable type, 40 pin or 80 pin?
/
-static void get_ide_dma66()
+static void get_ide_dma66(void)
{
u8 byte;
struct device *sm_dev;
@@ -120,7 +121,7 @@
/*
* set thermal config
*/
-static void set_thermal_config()
+static void set_thermal_config(void)
{
u8 byte;
u16 word;
@@ -185,11 +186,8 @@
* enable the dedicated function in dbm690t board.
* This function called early than rs690_enable.
*/
-void dbm690t_enable(device_t dev)
+static void dbm690t_enable(device_t dev)
{
- struct mainboard_config *mainboard =
- (struct mainboard_config *)dev-chip_info;
-
printk(BIOS_INFO, Mainboard DBM690T Enable. dev=0x%p\n, dev);
#if (CONFIG_GFXUMA == 1)
@@ -249,6 +247,7 @@
lb_add_memory_range(mem, LB_MEM_RESERVED,
uma_memory_base, uma_memory_size);
#endif
+ return 0;
}
struct chip_operations mainboard_ops = {
Modified: trunk/src/mainboard/amd/mahogany/get_bus_conf.c
==
--- trunk/src/mainboard/amd/mahogany/get_bus_conf.c Fri Apr 9 13:37:58
2010(r5390)
+++ trunk/src/mainboard/amd/mahogany/get_bus_conf.c Fri Apr 9 13:55:43
2010(r5391)
@@ -63,8 +63,6 @@
static u32 get_bus_conf_done = 0;
-void get_bus_conf(void);
-
void get_bus_conf(void)
{
u32 apicid_base;
Modified: trunk/src/mainboard/amd/pistachio/mainboard.c
==
--- trunk/src/mainboard/amd/pistachio/mainboard.c Fri Apr 9 13:37:58
2010(r5390)
+++ trunk/src/mainboard/amd/pistachio/mainboard.c Fri Apr 9 13:55:43
2010(r5391)
@@ -22,6 +22,7 @@
#include device/pci.h
#include arch/io.h
#include boot/coreboot_tables.h
+#include arch/coreboot_tables.h
#include cpu/x86/msr.h
#include cpu/amd/mtrr.h
#include device/pci_def.h
@@ -57,7 +58,7 @@
* The R77 (on BRASS) / R81 (on Bronze) is not load!
* So NIC can work whether this function runs.
/
-static void enable_onboard_nic()
+static void enable_onboard_nic(void)
{
u8 byte;
@@ -77,7 +78,7 @@
/*
* set thermal config
*/
-static void set_thermal_config()
+static void set_thermal_config(void)
{
u8 byte, byte2;
u16 word;
@@ -256,11 +257,8 @@
* enable the dedicated function in pistachio board.
* This function called early than rs690_enable.
*/
-void pistachio_enable(device_t dev)
+static void pistachio_enable(device_t dev)
{
- struct mainboard_config *mainboard =
- (struct mainboard_config *)dev-chip_info;
-
printk(BIOS_INFO, Mainboard Pistachio Enable. dev=0x%p\n, dev);
#if (CONFIG_GFXUMA == 1)
@@ -320,6 +318,7 @@
lb_add_memory_range(mem, LB_MEM_RESERVED,
uma_memory_base, uma_memory_size);
#endif
+ return 0;
}
struct chip_operations mainboard_ops = {
--
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[coreboot] Will coreboot work on my machine?
Will my computer work with Coreboot?Step1: MB - ECS P4M900T-M; CPU - Intel(R) Core(TM)2 CPU 4400 @ 2.00GHz; SB - VT8237A; NB - P4M900Step2: delphist2...@delphist2008-desktop ~ $ lspci -tvnn-+-[:80]---01.0 VIA Technologies, Inc. VT1708/A [Azalia HDAC] (VIA High Definition Audio Controller) [1106:3288] \-[:00]-+-00.0 VIA Technologies, Inc. CN896/VN896/P4M900 Host Bridge [1106:0364] +-00.1 VIA Technologies, Inc. CN896/VN896/P4M900 Host Bridge [1106:1364] +-00.2 VIA Technologies, Inc. CN896/VN896/P4M900 Host Bridge [1106:2364] +-00.3 VIA Technologies, Inc. CN896/VN896/P4M900 Host Bridge [1106:3364] +-00.4 VIA Technologies, Inc. CN896/VN896/P4M900 Host Bridge [1106:4364] +-00.5 VIA Technologies, Inc. CN896/VN896/P4M900 I/O APIC Interrupt Controller [1106:5364] +-00.6 VIA Technologies, Inc. CN896/VN896/P4M900 Security Device [1106:6364] +-00.7 VIA Technologies, Inc. CN896/VN896/P4M900 Host Bridge [1106:7364] +-01.0-[:01]-- +-02.0-[:02]00.0 nVidia Corporation Device [10de:0640] +-03.0-[:03]-- +-08.0 Creative Labs SB Audigy [1102:0004] +-08.1 Creative Labs SB Audigy Game Port [1102:7003] +-08.2 Creative Labs SB Audigy FireWire Port [1102:4001] +-09.0 Philips Semiconductors SAA7146 [1131:7146] +-0f.0 VIA Technologies, Inc. Device [1106:5337] +-0f.1 VIA Technologies, Inc. VT82C586A/B/VT82C686/A/B/VT823x/A/C PIPC Bus Master IDE [1106:0571] +-10.0 VIA Technologies, Inc. VT82x UHCI USB 1.1 Controller [1106:3038] +-10.1 VIA Technologies, Inc. VT82x UHCI USB 1.1 Controller [1106:3038] +-10.2 VIA Technologies, Inc. VT82x UHCI USB 1.1 Controller [1106:3038] +-10.3 VIA Technologies, Inc. VT82x UHCI USB 1.1 Controller [1106:3038] +-10.4 VIA Technologies, Inc. USB 2.0 [1106:3104] +-11.0 VIA Technologies, Inc. VT8237A PCI to ISA Bridge [1106:3337] +-11.7 VIA Technologies, Inc. VT8251 Ultra VLINK Controller [1106:287e] +-12.0 VIA Technologies, Inc. VT6102 [Rhine-II] [1106:3065] \-13.0 VIA Technologies, Inc. VT8237A Host Bridge [1106:337b]Step3: ITE IT8718FStep4:flashrom v0.9.1-r706No coreboot table found.Found chipset "VIA VT8237A", enabling flash write... OK.This chipset supports the following protocols: Non-SPI.Calibrating delay loop... 563M loops per second, 100 myus = 198 us. OK.Probing for AMD Am29F010A/B, 128 KB: probe_29f040b: id1 0xff, id2 0xffProbing for AMD Am29F002(N)BB, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xbf, id2 0x50, id2 is normal flash contentProbing for AMD Am29F002(N)BT, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xbf, id2 0x50, id2 is normal flash contentProbing for AMD Am29F016D, 2048 KB: probe_29f040b: id1 0xff, id2 0xffProbing for AMD Am29F040B, 512 KB: probe_29f040b: id1 0xff, id2 0xffProbing for AMD Am29F080B, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash contentProbing for AMD Am29LV040B, 512 KB: probe_29f040b: id1 0xff, id2 0xffProbing for AMD Am29LV081B, 1024 KB: probe_29f040b: id1 0xff, id2 0xffProbing for ASD AE49F2008, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xbf, id2 0x50, id2 is normal flash contentProbing for Atmel AT25DF021, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.Probing for Atmel AT25DF041A, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.Probing for Atmel AT25DF081, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.Probing for Atmel AT25DF161, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.Probing for Atmel AT25DF321, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.Probing for Atmel AT25DF321A, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.Probing for Atmel AT25DF641, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.Probing for Atmel AT25F512B, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.Probing for Atmel AT25FS010, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.Probing for Atmel AT25FS040, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.Probing for Atmel AT26DF041, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.Probing for Atmel AT26DF081A, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.Probing for Atmel AT26DF161, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.Probing for Atmel AT26DF161A, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.Probing for Atmel AT26F004, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.Probing for Atmel AT29C512, 64 KB: probe_jedec:
Re: [coreboot] [commit] r5330 - in trunk: . src/arch/i386
Stefan Reinauer ste...@coresystems.de writes: I made a quick attempt at fixing this, but ran into linker script problems like: .../crossgcc/xgcc/bin/../lib/gcc/i386-elf/4.4.2/../../../../i386-elf/bin/ld: section .id loaded at [ff61,ff7f] overlaps section .rom loaded at [,00010cdf] .../crossgcc/xgcc/bin/../lib/gcc/i386-elf/4.4.2/../../../../i386-elf/bin/ld: build/coreboot: section .id vma 0xff61 overlaps previous sections .../crossgcc/xgcc/bin/../lib/gcc/i386-elf/4.4.2/../../../../i386-elf/bin/ld: build/coreboot: section .romstrap vma 0xffa0 overlaps previous sections .../crossgcc/xgcc/bin/../lib/gcc/i386-elf/4.4.2/../../../../i386-elf/bin/ld: build/coreboot: section .reset vma 0xfff0 overlaps previous sections .../crossgcc/xgcc/bin/../lib/gcc/i386-elf/4.4.2/../../../../i386-elf/bin/ld: build/coreboot: section .text vma 0x10d00 overlaps previous sections collect2: ld returned 1 exit status which I didn't really have the time to pursue. I'm reverting my local checkout for now. If anyone has pointers regarding how to resolve this, I'd be happy to hear them. What was your local patch? I tried both disabling the TINY_BOOTBLOCK directive as well as modifying src/arch/i386/Makefile.inc to include chipset_bootblock_* unconditionally, both resulted in similar errors. (I do have other local changes as well, but none that should affect this. They might affect code size, though.) -- Arne. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Dualbios on GA-MA770-UD3
Hi Vadim, thanks for your mail. I have added the flashrom mailing list in CC: because we should develop a generic way to handle DualBIOS and similar techniques. On 09.04.2010 08:12, Vadim Girlin wrote: I'm going to try coreboot on Gigabyte GA-MA770-UD3. It's AMD 770 (RX780 / SB700). My motherboard supports hardware dual bios - with two chips on it. I'm going to try flashing backup chip and boot from it. It seems to be possible - I've tested it (flashing at least). Chips on this board could be switched by changing bit 0 at undocumented register EF on LDN 7 of IT8720. I can use slightly patched flashrom for accessing any chip I want without any problems. And this is tested many times. My idea is to use backup chip for debugging - that always keeps my chance to reboot from main bios chip. And removes the need for desoldering etc. And second problem is that original bios is checking second chip - and trying to recover it by flashing the bios from main chip on reboot? rewriting coreboot. AFAICS this could be solved by including some signatures etc. It seems to be easy to find out. May be someone is working on this? BTW I can send the patch for flashrom - but I think that with information I mentioned above somebody could make it much better than my ugly hack. I hope the regs should be the same for all latest Gigabyte MBs using IT8720/18 It would be great if you could send that patch. It will help us make a flashrom design decision that works for all boards with multiple flash chips. By the way, some of us have good contacts at ITE, so we can ask ITE for details about the undocumented registers. Regards, Carl-Daniel -- http://www.hailfinger.org/ -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] password
On 09.04.2010 05:17, Darmawan Salihun wrote: I'm not sure if this will work and it's risky as well, but you might want to try it out: In most BIOS, shorting the address pins (or the equivalent of that act) upon boot will force the machine to boot from the bootblock BIOS. The bootblock routine usually searches for BIOS binary file to flash, because the assumption is the system BIOS a.k.a main BIOS module is corrupt and need replacement. This can't work on LPC/FWH/SPI flash because there are no address lines on these chips. And even on old-style parallel flash, I don't understand how this is supposed to work. If we short all address lines, the CPU is going to read garbage from the ROM and won't even start up. Same problem applies if you short the lowest address line. Shorting some intermediate address line like A8 could work if the BIOS image is carefully crafted. Shorting the uppermost address line could work as well. And if an EC is using that parallel flash chip as well, you'd better make sure it will _never_ read garbage or you have some really big problems. I'd appreciate a real-world example where shorting an address pin works. Please include the flash chip type and tell me which address pin was shorted, and whether the pin was tied to 0 or to 1. Regards, Carl-Daniel -- http://www.hailfinger.org/ -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Dualbios on GA-MA770-UD3
On 09.04.2010 14:35, Andriy Gapon wrote: on 09/04/2010 15:18 Carl-Daniel Hailfinger said the following: By the way, some of us have good contacts at ITE, so we can ask ITE for details about the undocumented registers. BTW: http://www.flashrom.org/pipermail/flashrom/2009-September/000542.html Doesn't look like anybody showed interest that time. I'm very sorry about that. Your mail is still on my huge TODO list (final university exams are eating up my time). Two weeks from now I'll finally have time to start tackling all flashrom TODOs. Regards, Carl-Daniel -- http://www.hailfinger.org/ -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Dualbios on GA-MA770-UD3
on 09/04/2010 15:42 Carl-Daniel Hailfinger said the following: On 09.04.2010 14:35, Andriy Gapon wrote: on 09/04/2010 15:18 Carl-Daniel Hailfinger said the following: By the way, some of us have good contacts at ITE, so we can ask ITE for details about the undocumented registers. BTW: http://www.flashrom.org/pipermail/flashrom/2009-September/000542.html Doesn't look like anybody showed interest that time. I'm very sorry about that. Your mail is still on my huge TODO list (final university exams are eating up my time). Two weeks from now I'll finally have time to start tackling all flashrom TODOs. No problem, I frequently find myself in the same situation. -- Andriy Gapon -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Dualbios on GA-MA770-UD3
on 09/04/2010 15:18 Carl-Daniel Hailfinger said the following: By the way, some of us have good contacts at ITE, so we can ask ITE for details about the undocumented registers. BTW: http://www.flashrom.org/pipermail/flashrom/2009-September/000542.html Doesn't look like anybody showed interest that time. -- Andriy Gapon -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r5392 - in trunk/src/cpu: amd/car amd/dualcore x86/16bit x86/32bit x86/car
Author: stepan
Date: Fri Apr 9 15:31:07 2010
New Revision: 5392
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5392
Log:
drop unused files
drop some non-car code from amd/dualcore (there is no AMD dualcore without CAR)
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by: Stefan Reinauer ste...@coresystems.de
Deleted:
trunk/src/cpu/amd/car/cache_as_ram.lds
trunk/src/cpu/x86/32bit/reset32.inc
trunk/src/cpu/x86/32bit/reset32.lds
Modified:
trunk/src/cpu/amd/car/post_cache_as_ram.c
trunk/src/cpu/amd/dualcore/dualcore.c
trunk/src/cpu/x86/16bit/entry16.lds
trunk/src/cpu/x86/car/cache_as_ram.lds
Modified: trunk/src/cpu/amd/car/post_cache_as_ram.c
==
--- trunk/src/cpu/amd/car/post_cache_as_ram.c Fri Apr 9 13:55:43 2010
(r5391)
+++ trunk/src/cpu/amd/car/post_cache_as_ram.c Fri Apr 9 15:31:07 2010
(r5392)
@@ -1,6 +1,7 @@
/* 2005.6 by yhlu
* 2006.3 yhlu add copy data from CAR to ram
*/
+#include arch/stages.h
#include cpu/amd/car/disable_cache_as_ram.c
static inline void print_debug_pcar(const char *strval, uint32_t val)
Modified: trunk/src/cpu/amd/dualcore/dualcore.c
==
--- trunk/src/cpu/amd/dualcore/dualcore.c Fri Apr 9 13:55:43 2010
(r5391)
+++ trunk/src/cpu/amd/dualcore/dualcore.c Fri Apr 9 15:31:07 2010
(r5392)
@@ -70,95 +70,5 @@
}
}
-#if CONFIG_USE_DCACHE_RAM == 0
-static void do_k8_init_and_stop_secondaries(void)
-{
- struct node_core_id id;
- device_t dev;
- unsigned apicid;
- unsigned max_siblings;
- msr_t msr;
-
- /* Skip this if there was a built in self test failure */
- if (is_cpu_pre_e0()) {
- id.nodeid = lapicid() 0x7;
- id.coreid = 0;
- } else {
- /* Which cpu are we on? */
- id = get_node_core_id_x();
- /* Set NB_CFG_MSR
-* Linux expect the core to be in the least signficant bits.
-*/
- msr = rdmsr(NB_CFG_MSR);
- msr.hi |= (1(54-32)); // InitApicIdCpuIdLo
- wrmsr(NB_CFG_MSR, msr);
- }
-
- /* For now assume all cpus have the same number of siblings */
- max_siblings = (cpuid_ecx(0x8008) 0xff) + 1;
-
- /* Enable extended apic ids */
- device_t dev_f0 = PCI_DEV(0, 0x18+id.nodeid, 0);
- unsigned val = pci_read_config32(dev_f0, 0x68);
- val |= (1 18) | (1 17);
- pci_write_config32(dev_f0, 0x68, val);
-
- /* Set the lapicid */
-#if (CONFIG_ENABLE_APIC_EXT_ID == 1)
-unsigned initial_apicid = get_initial_apicid();
-#if CONFIG_LIFT_BSP_APIC_ID == 0
-if( initial_apicid != 0 ) // other than bsp
-#endif
-{
-/* use initial apic id to lift it */
-uint32_t dword = lapic_read(LAPIC_ID);
-dword = ~(0xff24);
-dword |= (((initial_apicid +
CONFIG_APIC_ID_OFFSET) 0xff)24);
-
-lapic_write(LAPIC_ID, dword);
-}
-
-#if CONFIG_LIFT_BSP_APIC_ID == 1
-bsp_apicid += CONFIG_APIC_ID_OFFSET;
-#endif
-
-#endif
-
-
- /* Remember the cpuid */
- if (id.coreid == 0) {
- dev = PCI_DEV(0, 0x18 + id.nodeid, 2);
- pci_write_config32(dev, 0x9c, cpuid_eax(1));
- }
-
- /* Maybe call distinguish_cpu_resets only on the last core? */
- distinguish_cpu_resets(id.nodeid);
- if (!boot_cpu()) {
- stop_this_cpu();
- }
-}
-
-static void k8_init_and_stop_secondaries(void)
-{
- /* This doesn't work with Cache As Ram because it messes with
- the MTRR state, which breaks the init detection.
- do_k8_init_and_stop_secondaries should be usable by CAR code.
- */
-
- int init_detected;
-
- init_detected = early_mtrr_init_detected();
- amd_early_mtrr_init();
-
- enable_lapic();
- init_timer();
- if (init_detected) {
- asm volatile (jmp __cpu_reset);
- }
-
- do_k8_init_and_stop_secondaries();
-}
-
-#endif
Modified: trunk/src/cpu/x86/16bit/entry16.lds
==
--- trunk/src/cpu/x86/16bit/entry16.lds Fri Apr 9 13:55:43 2010(r5391)
+++ trunk/src/cpu/x86/16bit/entry16.lds Fri Apr 9 15:31:07 2010(r5392)
@@ -1,2 +1 @@
gdtptr16_offset = gdtptr16 0x;
- _start_offset = _start 0x;
Modified: trunk/src/cpu/x86/car/cache_as_ram.lds
==
---
[coreboot] [commit] r5393 - in trunk/src: arch/i386/lib cpu/x86/car mainboard/dell/s1850 mainboard/intel/jarrell mainboard/intel/mtarvon mainboard/intel/truxton mainboard/supermicro/x6dai_g mainboard/
Author: stepan
Date: Fri Apr 9 15:33:59 2010
New Revision: 5393
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5393
Log:
Drop the need for cpu_reset, it's really just a short cut to stage2.
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by: Stefan Reinauer ste...@coresystems.de
Added:
trunk/src/arch/i386/lib/stages.c
Modified:
trunk/src/cpu/x86/car/cache_as_ram.lds
trunk/src/mainboard/dell/s1850/romstage.c
trunk/src/mainboard/intel/jarrell/romstage.c
trunk/src/mainboard/intel/mtarvon/romstage.c
trunk/src/mainboard/intel/truxton/romstage.c
trunk/src/mainboard/supermicro/x6dai_g/romstage.c
trunk/src/mainboard/supermicro/x6dhe_g/romstage.c
trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c
trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c
trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c
Added: trunk/src/arch/i386/lib/stages.c
==
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ trunk/src/arch/i386/lib/stages.cFri Apr 9 15:33:59 2010(r5393)
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+static void skip_romstage(void)
+{
+ asm volatile (
+ /* set the boot_complete flag */\n
+ movl $0x, %%ebp\n
+ jmp__main\n
+ );
+}
+
Modified: trunk/src/cpu/x86/car/cache_as_ram.lds
==
--- trunk/src/cpu/x86/car/cache_as_ram.lds Fri Apr 9 15:31:07 2010
(r5392)
+++ trunk/src/cpu/x86/car/cache_as_ram.lds Fri Apr 9 15:33:59 2010
(r5393)
@@ -5,8 +5,7 @@
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
+ * the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
Modified: trunk/src/mainboard/dell/s1850/romstage.c
==
--- trunk/src/mainboard/dell/s1850/romstage.c Fri Apr 9 15:31:07 2010
(r5392)
+++ trunk/src/mainboard/dell/s1850/romstage.c Fri Apr 9 15:33:59 2010
(r5393)
@@ -157,6 +157,8 @@
/* end IPMI garbage */
+#include arch/i386/lib/stages.c
+
static void main(unsigned long bist)
{
u8 b;
@@ -277,7 +279,7 @@
/* Skip this if there was a built in self test failure */
early_mtrr_init();
if (memory_initialized()) {
- asm volatile (jmp __cpu_reset);
+ skip_romstage();
}
}
/* Setup the console */
Modified: trunk/src/mainboard/intel/jarrell/romstage.c
==
--- trunk/src/mainboard/intel/jarrell/romstage.cFri Apr 9 15:31:07
2010(r5392)
+++ trunk/src/mainboard/intel/jarrell/romstage.cFri Apr 9 15:33:59
2010(r5393)
@@ -50,6 +50,7 @@
#include northbridge/intel/e7520/raminit.c
#include lib/generic_sdram.c
#include debug.c
+#include arch/i386/lib/stages.c
static void main(unsigned long bist)
{
@@ -75,7 +76,7 @@
/* Skip this if there was a built in self test failure */
early_mtrr_init();
if (memory_initialized()) {
- asm volatile (jmp __cpu_reset);
+ skip_romstage();
}
}
/* Setup the console */
Modified: trunk/src/mainboard/intel/mtarvon/romstage.c
==
--- trunk/src/mainboard/intel/mtarvon/romstage.cFri Apr 9 15:31:07
2010(r5392)
+++ trunk/src/mainboard/intel/mtarvon/romstage.cFri Apr 9 15:33:59
2010(r5393)
@@ -58,6 +58,7 @@
#include northbridge/intel/i3100/raminit.c
#include lib/generic_sdram.c
#include ../jarrell/debug.c
+#include
[coreboot] [commit] r5394 - in trunk/src: northbridge/amd/amdfam10 northbridge/amd/amdht northbridge/amd/amdmct/mct southbridge/amd/amd8111 southbridge/amd/sb700
Author: stepan
Date: Fri Apr 9 15:35:03 2010
New Revision: 5394
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5394
Log:
zero warnings days.
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by: Stefan Reinauer ste...@coresystems.de
Modified:
trunk/src/northbridge/amd/amdfam10/northbridge.h
trunk/src/northbridge/amd/amdht/h3ncmn.c
trunk/src/northbridge/amd/amdmct/mct/mctdqs_d.c
trunk/src/northbridge/amd/amdmct/mct/mctsrc1p.c
trunk/src/southbridge/amd/amd8111/amd8111_early_ctrl.c
trunk/src/southbridge/amd/sb700/sb700_reset.c
Modified: trunk/src/northbridge/amd/amdfam10/northbridge.h
==
--- trunk/src/northbridge/amd/amdfam10/northbridge.hFri Apr 9 15:33:59
2010(r5393)
+++ trunk/src/northbridge/amd/amdfam10/northbridge.hFri Apr 9 15:35:03
2010(r5394)
@@ -20,6 +20,6 @@
#ifndef NORTHBRIDGE_AMD_AMDFAM10_H
#define NORTHBRIDGE_AMD_AMDFAM10_H
-extern u32 amdfam10_scan_root_bus(device_t root, u32 max);
+u32 amdfam10_scan_root_bus(device_t root, u32 max);
#endif /* NORTHBRIDGE_AMD_AMDFAM10_H */
Modified: trunk/src/northbridge/amd/amdht/h3ncmn.c
==
--- trunk/src/northbridge/amd/amdht/h3ncmn.cFri Apr 9 15:33:59 2010
(r5393)
+++ trunk/src/northbridge/amd/amdht/h3ncmn.cFri Apr 9 15:35:03 2010
(r5394)
@@ -166,7 +166,7 @@
/**
*
- * void
+ * static void
* writeRoutingTable(u8 node, u8 target, u8 Link, cNorthBridge *nb)
*
* Description:
@@ -188,7 +188,7 @@
*
---
*/
-void writeRoutingTable(u8 node, u8 target, u8 link, cNorthBridge *nb)
+static void writeRoutingTable(u8 node, u8 target, u8 link, cNorthBridge *nb)
{
#ifndef HT_BUILD_NC_ONLY
u32 temp = (nb-selfRouteResponseMask | nb-selfRouteRequestMask)
(link + 1);
@@ -206,7 +206,7 @@
/**
*
- * void
+ * static void
* writeNodeID(u8 node, u8 nodeID, cNorthBridge *nb)
*
* Description:
@@ -220,7 +220,7 @@
*
---
*/
-void writeNodeID(u8 node, u8 nodeID, cNorthBridge *nb)
+static void writeNodeID(u8 node, u8 nodeID, cNorthBridge *nb)
{
u32 temp = nodeID;
ASSERT((node nb-maxNodes) (nodeID nb-maxNodes));
@@ -234,7 +234,7 @@
/**
*
- * void
+ * static void
* readDefLnk(u8 node, cNorthBridge *nb)
*
* Description:
@@ -252,7 +252,7 @@
*
---
*/
-u8 readDefLnk(u8 node, cNorthBridge *nb)
+static u8 readDefLnk(u8 node, cNorthBridge *nb)
{
u32 deflink = 0;
SBDFO licr;
@@ -273,7 +273,7 @@
/**
*
- * void
+ * static void
* enableRoutingTables(u8 node, cNorthBridge *nb)
*
* Description:
@@ -286,7 +286,7 @@
*
---
*/
-void enableRoutingTables(u8 node, cNorthBridge *nb)
+static void enableRoutingTables(u8 node, cNorthBridge *nb)
{
u32 temp = 0;
ASSERT((node nb-maxNodes));
@@ -301,7 +301,7 @@
/**
*
- * void
+ * static BOOL
* verifyLinkIsCoherent(u8 node, u8 Link, cNorthBridge *nbk)
*
* Description:
@@ -322,7 +322,7 @@
*
---
*/
-BOOL verifyLinkIsCoherent(u8 node, u8 link, cNorthBridge *nb)
+static BOOL verifyLinkIsCoherent(u8 node, u8 link, cNorthBridge *nb)
{
#ifndef HT_BUILD_NC_ONLY
@@ -345,7 +345,7 @@
/**
*
- * bool
+ * static bool
* readTrueLinkFailStatus(u8 node, u8 link, sMainData *pDat, cNorthBridge *nb)
*
* Description:
@@ -371,7 +371,7 @@
*
*
---
*/
-BOOL readTrueLinkFailStatus(u8 node, u8 link, sMainData *pDat, cNorthBridge
*nb)
+static BOOL readTrueLinkFailStatus(u8 node, u8 link, sMainData *pDat,
cNorthBridge *nb)
{
u32 before, after, unconnected, crc;
SBDFO linkBase;
@@ -436,7 +436,7 @@
/**
*
- * u8
+ * static u8
* readToken(u8 node, cNorthBridge *nb)
*
* Description:
@@ -452,7 +452,7 @@
*
*
Re: [coreboot] [commit] r5388 - in trunk/src: arch/i3 86 arch/i386/include/arch arch/i386/lib cpu/intel cpu/intel/mod el_6bx cpu/intel/model_6ex cpu/intel/socket_mFCBGA479 inc lude mainboard/rca/rm410
On Fri, 09 Apr 2010 13:10:26 +0200, repository service s...@coreboot.org wrote: Author: stepan Date: Fri Apr 9 13:10:25 2010 New Revision: 5388 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5388 Log: 1. This patch adds CAR for Intel P6 series processors. 2. Add support for Micro-FCBGA 479 Celeron and PIII's 3. Add support for model_6bx and microcode updates 4. Add support for CAR and Tinybootblock on RCA RM4100 and Thomson IP1000 Build and boot tested. Signed-off-by: Joseph Smith j...@settoplinux.org The change to CAR reveiled a few more warnings in the ICH4 and i830 code, I fixed them on the fly. Checking this in because my last two commits broke Joseph's CAR patch. This version fixes the issues. Ok thanks Stefan. My next patch was to take care of those warnings, and now that I can printk in car, I was going to revamp raminit. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r5395 - in trunk/src/arch/i386: . lib
Author: stepan Date: Fri Apr 9 15:49:48 2010 New Revision: 5395 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5395 Log: drop now unussed cpu_reset.inc make it more clear if coreboot is building without payload. Signed-off-by: Stefan Reinauer ste...@coresystems.de Acked-by: Stefan Reinauer ste...@coresystems.de Deleted: trunk/src/arch/i386/lib/cpu_reset.inc Modified: trunk/src/arch/i386/Makefile.inc Modified: trunk/src/arch/i386/Makefile.inc == --- trunk/src/arch/i386/Makefile.incFri Apr 9 15:35:03 2010(r5394) +++ trunk/src/arch/i386/Makefile.incFri Apr 9 15:49:48 2010(r5395) @@ -35,7 +35,7 @@ fi $(CBFSTOOL) $...@.tmp add-stage $(obj)/coreboot_ram $(CONFIG_CBFS_PREFIX)/coreboot_ram $(CBFS_COMPRESS_FLAG) ifeq ($(CONFIG_PAYLOAD_NONE),y) - printf PAYLOADnone (as specified by user)\n + printf PAYLOAD\e[1;31mnone (as specified by user)\e[0m\n else printf PAYLOAD$(CONFIG_FALLBACK_PAYLOAD_FILE) $(CBFS_PAYLOAD_COMPRESS_FLAG)\n $(CBFSTOOL) $...@.tmp add-payload $(CONFIG_FALLBACK_PAYLOAD_FILE) $(CONFIG_CBFS_PREFIX)/payload $(CBFS_PAYLOAD_COMPRESS_FLAG) @@ -112,9 +112,6 @@ ifeq ($(CONFIG_BIG_BOOTBLOCK),y) crt0s += $(src)/cpu/x86/16bit/reset16.inc ldscripts += $(src)/cpu/x86/16bit/reset16.lds -ifeq ($(CONFIG_ROMCC),y) -crt0s += $(src)/arch/i386/lib/cpu_reset.inc -endif crt0s += $(src)/arch/i386/lib/id.inc ldscripts += $(src)/arch/i386/lib/id.lds endif -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [commit] r5388 - in trunk/src: arch/i386 arch/i386/include/arch arch/i386/lib cpu/intel cpu/intel/model_6bx cpu/intel/model_6ex cpu/intel/socket_mFCBGA479 include mainboard/rca/rm4100 m
On 4/9/10 3:36 PM, Joseph Smith wrote: My next patch was to take care of those warnings, and now that I can printk in car, I was going to revamp raminit. Please go ahead! Stefan -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] password
On Thursday 08 April 2010 20:45:34 ron minnich wrote: I have a lenovo x300 somebody set the password on and ... as you guess, forgot. As Rudof suggested, you can probably use the master password for recovery if it works. Otherwise I recommend for such situations the cmospwd utility from cgsecurity (also pretty well know for their testdisk utility). As far I used the cmospwd utility it worked like a charm. http://www.cgsecurity.org/wiki/CmosPwd So, question: anyone have any idea how deep into the machine the password is kept no new machines? Deep in TPM? I think it's most likely stored in CMOS/EEPROM, but the solutions on that goal varies from manufacturer to manufacturer. in other words, were flashrom to work on this box, can the password be reset? Try to use the tool mentioned above, I had until now always success with that. ron Harald -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [commit] r5330 - in trunk: . src/arch/i386
On 4/9/10 1:50 PM, Arne Georg Gleditsch wrote: Stefan Reinauer ste...@coresystems.de writes: I made a quick attempt at fixing this, but ran into linker script problems like: .../crossgcc/xgcc/bin/../lib/gcc/i386-elf/4.4.2/../../../../i386-elf/bin/ld: section .id loaded at [ff61,ff7f] overlaps section .rom loaded at [,00010cdf] .../crossgcc/xgcc/bin/../lib/gcc/i386-elf/4.4.2/../../../../i386-elf/bin/ld: build/coreboot: section .id vma 0xff61 overlaps previous sections .../crossgcc/xgcc/bin/../lib/gcc/i386-elf/4.4.2/../../../../i386-elf/bin/ld: build/coreboot: section .romstrap vma 0xffa0 overlaps previous sections .../crossgcc/xgcc/bin/../lib/gcc/i386-elf/4.4.2/../../../../i386-elf/bin/ld: build/coreboot: section .reset vma 0xfff0 overlaps previous sections .../crossgcc/xgcc/bin/../lib/gcc/i386-elf/4.4.2/../../../../i386-elf/bin/ld: build/coreboot: section .text vma 0x10d00 overlaps previous sections collect2: ld returned 1 exit status which I didn't really have the time to pursue. I'm reverting my local checkout for now. If anyone has pointers regarding how to resolve this, I'd be happy to hear them. What was your local patch? I tried both disabling the TINY_BOOTBLOCK directive as well as modifying src/arch/i386/Makefile.inc to include chipset_bootblock_* unconditionally, both resulted in similar errors. (I do have other local changes as well, but none that should affect this. They might affect code size, though.) Ah, the error above may occur if changing significant parts of Kconfig variables, such as tiny bootblock ;) please remove build/ and try again. There should be a dependency fix for this. -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] password
On Friday 09 April 2010 16:12:28 Harald Gutmann wrote: On Thursday 08 April 2010 20:45:34 ron minnich wrote: I have a lenovo x300 somebody set the password on and ... as you guess, forgot. As Rudof suggested, you can probably use the master password for recovery if it works. I just read his posting quite fast, and he didn't mention a master password, just a eeprom chip name. Otherwise I recommend for such situations the cmospwd utility from cgsecurity (also pretty well know for their testdisk utility). As far I used the cmospwd utility it worked like a charm. http://www.cgsecurity.org/wiki/CmosPwd According to it's Readme the tool won't work really fine on the Thinkpads, as those laptops use the chip Rudolf described. So, question: anyone have any idea how deep into the machine the password is kept no new machines? Deep in TPM? I think it's most likely stored in CMOS/EEPROM, but the solutions on that goal varies from manufacturer to manufacturer. In this case, its stored in a separate EEPROM, but the question is if it would be hard to read it in linux. Quote form the CmosPwd utilities Readme section Laptops: IBM Thinkpad X20: eeprom 24RFC08CN, password in scan code at 0x338 IBM TP 240: eeprom ?, password in scan code at 0x338. IBM TP 380Z: eeprom 24c01, password in scan code at 0x38 and 0x40 IBM TP 390: eeprom 24c03 (be carrefull, there are two eeprom) IBM TP 560X: eeprom 24c01, password in scan code at 0x38 and 0x40 IBM TP 570: eeprom ?, password in scan code at 0x338 and 0x3B8. IBM TP 750C,755CX,760C,765D: eeprom 93c46, password in scan code at 0x38 and 0x40 OKI M811b may be written on the chip. Search near pcmcia slot or adjacent the floppy connector on the top side of the board IBM TP 770: eeprom 24c01 IBM TP 600E, T21, T23: 14 PIN 24RF08 IBM TP T20: 24RF08, password in scan code at 0x338 and 0x3B8 -snip- You can get/buy eeprom programmer in electronic shops or labs, you need another PC to use it. You can desolder the eeprom with hot air or you can try to clip the eeprom. With the eeprom programmer, backup your eeprom and run cmospwd /d /l eeprom_backup. If you don't see the password, you can try to fill the eeprom with zero or FF, don't forget the reset the cmos. in other words, were flashrom to work on this box, can the password be reset? I guess if the assumption is right, that the X300 uses also a 24c0X eeprom to save the passwords, it's just a matter of how to read that without an external programmer, or if it is even possible to read it within an OS. Try to use the tool mentioned above, I had until now always success with that. Yes, but never used it on thinkpads... But pretty successful on desktop computers. ron Harald -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r5396 - in trunk/src: cpu/x86/mtrr mainboard/tyan/s2895 northbridge/amd/amdk8 southbridge/nvidia/ck804 superio/smsc/lpc47b397
Author: stepan
Date: Fri Apr 9 16:46:51 2010
New Revision: 5396
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5396
Log:
zero warnings days.
The tyan s2895 is down to 3 warnings, 2 of which are caused by #warning.
The 1000 ways of how the AMD code waits for the cores to be started up
are a real pain for the brain.
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by: Stefan Reinauer ste...@coresystems.de
Modified:
trunk/src/cpu/x86/mtrr/earlymtrr.c
trunk/src/mainboard/tyan/s2895/romstage.c
trunk/src/northbridge/amd/amdk8/debug.c
trunk/src/northbridge/amd/amdk8/incoherent_ht.c
trunk/src/northbridge/amd/amdk8/northbridge.c
trunk/src/northbridge/amd/amdk8/raminit.c
trunk/src/northbridge/amd/amdk8/raminit.h
trunk/src/northbridge/amd/amdk8/setup_resource_map.c
trunk/src/southbridge/nvidia/ck804/ck804_early_smbus.c
trunk/src/southbridge/nvidia/ck804/ck804_smbus.h
trunk/src/superio/smsc/lpc47b397/lpc47b397_early_gpio.c
Modified: trunk/src/cpu/x86/mtrr/earlymtrr.c
==
--- trunk/src/cpu/x86/mtrr/earlymtrr.c Fri Apr 9 15:49:48 2010(r5395)
+++ trunk/src/cpu/x86/mtrr/earlymtrr.c Fri Apr 9 16:46:51 2010(r5396)
@@ -97,7 +97,7 @@
}
-static void early_mtrr_init(void)
+static inline void early_mtrr_init(void)
{
static const unsigned long mtrr_msrs[] = {
/* fixed mtrr */
Modified: trunk/src/mainboard/tyan/s2895/romstage.c
==
--- trunk/src/mainboard/tyan/s2895/romstage.c Fri Apr 9 15:49:48 2010
(r5395)
+++ trunk/src/mainboard/tyan/s2895/romstage.c Fri Apr 9 16:46:51 2010
(r5396)
@@ -15,35 +15,26 @@
#include cpu/x86/lapic.h
#include option_table.h
#include pc80/mc146818rtc_early.c
-
#include pc80/serial.c
#include console/console.c
#include lib/ramtest.c
-
#include cpu/amd/model_fxx_rev.h
-
#include northbridge/amd/amdk8/incoherent_ht.c
#include southbridge/nvidia/ck804/ck804_early_smbus.c
#include northbridge/amd/amdk8/raminit.h
#include cpu/amd/model_fxx/apic_timer.c
#include lib/delay.c
-
#include cpu/x86/lapic/boot_cpu.c
#include northbridge/amd/amdk8/reset_test.c
#include superio/smsc/lpc47b397/lpc47b397_early_serial.c
#include superio/smsc/lpc47b397/lpc47b397_early_gpio.c
#define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
-
#define SUPERIO_GPIO_IO_BASE 0x400
-
#include cpu/x86/bist.h
-
#include northbridge/amd/amdk8/debug.c
-
-#include cpu/amd/mtrr/amd_earlymtrr.c
-
+#include cpu/amd/mtrr.h
+#include cpu/x86/mtrr/earlymtrr.c
#include northbridge/amd/amdk8/setup_resource_map.c
-
#define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
static void memreset_setup(void)
@@ -54,15 +45,14 @@
{
}
-static void sio_gpio_setup(void){
-
+static void sio_gpio_setup(void)
+{
unsigned value;
/*Enable onboard scsi*/
lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c,
(17)|(02)|(01)|(00)); // GP21, offset 0x2c, DISABLE_SCSI_L
value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(11)));
-
}
static inline void activate_spd_rom(const struct mem_controller *ctrl)
@@ -111,10 +101,9 @@
static void sio_setup(void)
{
-
unsigned value;
- uint32_t dword;
- uint8_t byte;
+ u32 dword;
+ u8 byte;
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
@@ -134,18 +123,15 @@
value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
value = 0xbf;
lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
-
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
- static const uint16_t spd_addr [] = {
+ static const u16 spd_addr [] = {
(0xa3)|0, (0xa3)|2, 0, 0,
(0xa3)|1, (0xa3)|3, 0, 0,
-#if CONFIG_MAX_PHYSICAL_CPUS 1
(0xa3)|4, (0xa3)|6, 0, 0,
(0xa3)|5, (0xa3)|7, 0, 0,
-#endif
};
int needs_reset;
@@ -170,8 +156,6 @@
bsp_apicid = init_cpus(cpu_init_detectedx);
}
-// post_code(0x32);
-
lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
@@ -186,11 +170,10 @@
needs_reset = setup_coherent_ht_domain();
wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS==1
+
// It is said that we should start core1 after all core0 launched
start_other_cores();
wait_all_other_cores_started(bsp_apicid);
-#endif
needs_reset |= ht_setup_chains_x();
Modified: trunk/src/northbridge/amd/amdk8/debug.c
==
--- trunk/src/northbridge/amd/amdk8/debug.c Fri Apr 9 15:49:48 2010
(r5395)
+++
Re: [coreboot] Dualbios on GA-MA770-UD3
On 04/09/2010 04:18 PM, Carl-Daniel Hailfinger wrote:
Hi Vadim,
thanks for your mail. I have added the flashrom mailing list in CC:
because we should develop a generic way to handle DualBIOS and similar
techniques.
On 09.04.2010 08:12, Vadim Girlin wrote:
I'm going to try coreboot on Gigabyte GA-MA770-UD3.
It's AMD 770 (RX780 / SB700).
My motherboard supports hardware dual bios - with two chips on it.
I'm going to try flashing backup chip and boot from it. It seems to be
possible - I've tested it (flashing at least). Chips on this board could
be switched by changing bit 0 at undocumented register EF on LDN 7 of
IT8720. I can use slightly patched flashrom for accessing any chip I
want without any problems. And this is tested many times.
My idea is to use backup chip for debugging - that always keeps my
chance to reboot from main bios chip. And removes the need for
desoldering etc.
And second problem is that original bios is checking second chip - and
trying to recover it by flashing the bios from main chip on reboot?
rewriting coreboot. AFAICS this could be solved by including some
signatures etc. It seems to be easy to find out. May be someone is
working on this?
BTW I can send the patch for flashrom - but I think that with
information I mentioned above somebody could make it much better than my
ugly hack. I hope the regs should be the same for all latest Gigabyte
MBs using IT8720/18
It would be great if you could send that patch. It will help us make a
flashrom design decision that works for all boards with multiple flash
chips.
OK, I'm sending the patch for flashrom - but it is based on RE and needs
careful testing.
It works fine on GA-MA770-UD3 (rev 1.0) but should be tested with other MBs.
Anyway I hope it should work for all latest Gigabyte MBs with dual bios
chips connected through IT8720/18.
I think it's not ready for inclusion in flashrom - it probably should be
done in more safe and generic way.
Probably it should check for default values in regs etc.
It may be used as following:
flashrom -p it87spi:gbdualindex=0 ...
flashrom -p it87spi:gbdualindex=1 ...
This value needs to be set only once and further ops on selected chip
can be performed without parameters.
Index: it87spi.c
===
--- it87spi.c (revision 992)
+++ it87spi.c (working copy)
@@ -155,6 +155,28 @@
sio_write(port, 0x65, (flashport 0xff));
free(portpos);
}
+
+ portpos = extract_param(programmer_param,
+ gbdualindex=, ,:);
+ if (portpos) {
+ int chip_index = strtol(portpos, (char **)NULL,
0);
+ if ((chip_index!=0) (chip_index!=1)) {
+ msg_perr(Dual bios: Invalid chip index
requested: %d\n,chip_index);
+ flashport=0;
+ } else {
+ tmp=sio_read(port,0xEF);
+ msg_pinfo(Dual bios: Current chip :
%d\n,tmp1);
+ if (chip_index!=(tmp1)) {
+
sio_write(port,0xEF,(tmp0xFE)|chip_index);
+ tmp=sio_read(port,0xEF)1;
+ if (tmp!=chip_index) {
+ msg_perr(Dual bios:
Chip selection failed.\n);
+ flashport=0;
+ } else msg_pinfo(Dual bios:
Selected chip: %d\n,tmp1);
+ }
+ }
+ free(portpos);
+ }
}
exit_conf_mode_ite(port);
break;
By the way, some of us have good contacts at ITE, so we can ask ITE for
details about the undocumented registers.
That could be very helpful for me. This register (LDN 7 reg EF) seems to
be very interesting. Bit 0 is chip select, but also bits 2,4,5,6 are
used in bios code. Bit 6 probably is some watchdog setting - setting it
on with resetting other bits causes reboot in ~ a second.
Also there is some moment in bios code about test reg 2F @ LDN F4 - it
is toggled in some place and this could be important - may be enabling
some undocumented features.
Another interesting moment is checking for status of RI2 event (LDN 4
reg F1 bit 1) - it's almost first op in bios startup code. AFAICS RI2
event causes switch to chip 1 (Backup) and reboot - but there is no COM2
port on that board. And settings at reg 29 after boot told me that RI2
pin is switched to GPIO mode. So it is probably some debugging
[coreboot] build service results for r5396
Dear coreboot readers! This is the automatic build system of coreboot. The developer stepan checked in revision 5396 to the coreboot repository. This caused the following changes: Change Log: zero warnings days. The tyan s2895 is down to 3 warnings, 2 of which are caused by #warning. The 1000 ways of how the AMD code waits for the cores to be started up are a real pain for the brain. Signed-off-by: Stefan Reinauer ste...@coresystems.de Acked-by: Stefan Reinauer ste...@coresystems.de Build Log: Compilation of asus:a8n_e has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5396device=a8n_evendor=asusnum=2 Compilation of asus:a8v-e_se has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5396device=a8v-e_sevendor=asusnum=2 Compilation of tyan:s2891 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5396device=s2891vendor=tyannum=2 If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r5397 - in trunk/src: arch/i386/include/arch mainboard/asus/a8v-e_se mainboard/asus/m2v-mx_se mainboard/broadcom/blast northbridge/amd/amdk8 southbridge/broadcom/bcm5785 southbridg
Author: stepan
Date: Fri Apr 9 17:29:13 2010
New Revision: 5397
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5397
Log:
fix the broken nvidia chipset boards,
remove more warnings.
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by: Stefan Reinauer ste...@coresystems.de
Modified:
trunk/src/arch/i386/include/arch/stages.h
trunk/src/mainboard/asus/a8v-e_se/acpi_tables.c
trunk/src/mainboard/asus/a8v-e_se/mptable.c
trunk/src/mainboard/asus/m2v-mx_se/mainboard.c
trunk/src/mainboard/broadcom/blast/mptable.c
trunk/src/mainboard/broadcom/blast/romstage.c
trunk/src/northbridge/amd/amdk8/setup_resource_map.c
trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c
trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.h
Modified: trunk/src/arch/i386/include/arch/stages.h
==
--- trunk/src/arch/i386/include/arch/stages.h Fri Apr 9 16:46:51 2010
(r5396)
+++ trunk/src/arch/i386/include/arch/stages.h Fri Apr 9 17:29:13 2010
(r5397)
@@ -1,5 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __ARCH_STAGES_H
+#define __ARCH_STAGES_H
void cbfs_and_run_core(const char *filename, unsigned int ebp);
void __attribute__((regparm(0))) copy_and_run(unsigned cpu_reset);
void __attribute__((regparm(0))) copy_and_run_ap_code_in_car(unsigned
ret_addr);
-
-
+#endif
Modified: trunk/src/mainboard/asus/a8v-e_se/acpi_tables.c
==
--- trunk/src/mainboard/asus/a8v-e_se/acpi_tables.c Fri Apr 9 16:46:51
2010(r5396)
+++ trunk/src/mainboard/asus/a8v-e_se/acpi_tables.c Fri Apr 9 17:29:13
2010(r5397)
@@ -87,8 +87,6 @@
acpi_srat_t *srat;
acpi_rsdt_t *rsdt;
acpi_mcfg_t *mcfg;
- acpi_hpet_t *hpet;
- acpi_madt_t *madt;
acpi_fadt_t *fadt;
acpi_facs_t *facs;
acpi_header_t *dsdt;
Modified: trunk/src/mainboard/asus/a8v-e_se/mptable.c
==
--- trunk/src/mainboard/asus/a8v-e_se/mptable.c Fri Apr 9 16:46:51 2010
(r5396)
+++ trunk/src/mainboard/asus/a8v-e_se/mptable.c Fri Apr 9 17:29:13 2010
(r5397)
@@ -29,7 +29,6 @@
static const char oem[8] = LNXB;
static const char productid[12] = A8V-E SE;
struct mp_config_table *mc;
- unsigned int conforms = 0;
int bus_isa = 42;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
Modified: trunk/src/mainboard/asus/m2v-mx_se/mainboard.c
==
--- trunk/src/mainboard/asus/m2v-mx_se/mainboard.c Fri Apr 9 16:46:51
2010(r5396)
+++ trunk/src/mainboard/asus/m2v-mx_se/mainboard.c Fri Apr 9 17:29:13
2010(r5397)
@@ -21,8 +21,9 @@
#include device/pci.h
#include device/pci_ids.h
#include boot/tables.h
+#include arch/coreboot_tables.h
#include chip.h
-#include ../../../southbridge/via/k8t890/k8t890.h
+#include southbridge/via/k8t890/k8t890.h
int add_mainboard_resources(struct lb_memory *mem)
{
Modified: trunk/src/mainboard/broadcom/blast/mptable.c
==
--- trunk/src/mainboard/broadcom/blast/mptable.cFri Apr 9 16:46:51
2010(r5396)
+++ trunk/src/mainboard/broadcom/blast/mptable.cFri Apr 9 17:29:13
2010(r5397)
@@ -62,7 +62,6 @@
/*I/O APICs: APIC ID Version State Address*/
{
device_t dev = 0;
- int i;
struct resource *res;
for(i=0; i3; i++) {
dev = dev_find_device(0x1166, 0x0235, dev);
Modified: trunk/src/mainboard/broadcom/blast/romstage.c
==
--- trunk/src/mainboard/broadcom/blast/romstage.c Fri Apr 9 16:46:51
2010(r5396)
+++ trunk/src/mainboard/broadcom/blast/romstage.c Fri Apr 9 17:29:13
2010(r5397)
@@ -50,10 +50,10 @@
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
#define
Re: [coreboot] [commit] r5330 - in trunk: . src/arch/i386
Stefan Reinauer ste...@coresystems.de writes: Ah, the error above may occur if changing significant parts of Kconfig variables, such as tiny bootblock ;) please remove build/ and try again. I always do. :) This is reproducible as follows: $ svn co svn://coreboot.org/coreboot/trunk coreboot [..] Checked out revision 5396. $ cd coreboot $ perl -npi -e 's/(?=select TINY)/#/' src/mainboard/tyan/s2912_fam10/Kconfig add .config $ make oldconfig $ make Relevant .config attached. -- Arne. # # Automatically generated make config: don't edit # coreboot version: 4.0 # Fri Apr 9 17:28:56 2010 # # # General setup # CONFIG_EXPERT=y CONFIG_LOCALVERSION= CONFIG_CBFS_PREFIX=fallback CONFIG_COMPILER_GCC=y # CONFIG_COMPILER_LLVM_CLANG is not set # CONFIG_SCANBUILD_ENABLE is not set # CONFIG_CCACHE is not set # # Mainboard # # CONFIG_VENDOR_ABIT is not set # CONFIG_VENDOR_ADVANTECH is not set # CONFIG_VENDOR_AMD is not set # CONFIG_VENDOR_ARIMA is not set # CONFIG_VENDOR_ARTEC_GROUP is not set # CONFIG_VENDOR_ASI is not set # CONFIG_VENDOR_ASROCK is not set # CONFIG_VENDOR_ASUS is not set # CONFIG_VENDOR_A_TREND is not set # CONFIG_VENDOR_AXUS is not set # CONFIG_VENDOR_AZZA is not set # CONFIG_VENDOR_BCOM is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BROADCOM is not set # CONFIG_VENDOR_COMPAQ is not set # CONFIG_VENDOR_DELL is not set # CONFIG_VENDOR_DIGITAL_LOGIC is not set # CONFIG_VENDOR_EAGLELION is not set # CONFIG_VENDOR_EMULATION is not set # CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_HP is not set # CONFIG_VENDOR_IBM is not set # CONFIG_VENDOR_IEI is not set # CONFIG_VENDOR_INTEL is not set # CONFIG_VENDOR_IWILL is not set # CONFIG_VENDOR_JETWAY is not set # CONFIG_VENDOR_KONTRON is not set # CONFIG_VENDOR_LIPPERT is not set # CONFIG_VENDOR_MITAC is not set # CONFIG_VENDOR_MSI is not set # CONFIG_VENDOR_NEC is not set # CONFIG_VENDOR_NEWISYS is not set # CONFIG_VENDOR_NVIDIA is not set # CONFIG_VENDOR_OLPC is not set # CONFIG_VENDOR_PC_ENGINES is not set # CONFIG_VENDOR_RCA is not set # CONFIG_VENDOR_RODA is not set # CONFIG_VENDOR_SOYO is not set # CONFIG_VENDOR_SUNW is not set # CONFIG_VENDOR_SUPERMICRO is not set # CONFIG_VENDOR_TECHNEXION is not set # CONFIG_VENDOR_TECHNOLOGIC is not set # CONFIG_VENDOR_TELEVIDEO is not set # CONFIG_VENDOR_THOMSON is not set CONFIG_VENDOR_TYAN=y # CONFIG_VENDOR_VIA is not set # CONFIG_VENDOR_WINENT is not set CONFIG_MAINBOARD_VENDOR=Tyan CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 CONFIG_MAINBOARD_DIR=tyan/s2912_fam10 CONFIG_MAINBOARD_PART_NUMBER=S2912 (Fam10) CONFIG_HAVE_OPTION_TABLE=y CONFIG_IRQ_SLOT_COUNT=11 CONFIG_RAMBASE=0x20 CONFIG_HAVE_HIGH_TABLES=y CONFIG_DCACHE_RAM_BASE=0xc4000 CONFIG_DCACHE_RAM_SIZE=0x0c000 CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x04000 CONFIG_APIC_ID_OFFSET=0 CONFIG_HW_MEM_HOLE_SIZEK=0x10 CONFIG_MAX_CPUS=12 CONFIG_MAX_PHYSICAL_CPUS=2 # CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC is not set CONFIG_SB_HT_CHAIN_ON_BUS0=2 CONFIG_HT_CHAIN_END_UNITID_BASE=0x20 CONFIG_HT_CHAIN_UNITID_BASE=0x1 CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2912 CONFIG_MEM_TRAIN_SEQ=2 CONFIG_AMD_UCODE_PATCH_FILE=mc_patch_0195.h CONFIG_RAMTOP=0x100 CONFIG_HEAP_SIZE=0xc CONFIG_ACPI_SSDTX_NUM=0 # CONFIG_SERIAL_CPU_INIT is not set CONFIG_ID_SECTION_OFFSET=0x80 # CONFIG_PCI_64BIT_PREF_MEM is not set CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_LOGICAL_CPUS=y CONFIG_IOAPIC=y CONFIG_SMP=y CONFIG_STACK_SIZE=0x8000 # CONFIG_USE_OPTION_TABLE is not set CONFIG_TTYS0_BAUD=115200 CONFIG_TTYS0_BASE=0x3f8 CONFIG_TTYS0_LCS=3 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 CONFIG_CONSOLE_SERIAL8250=y # CONFIG_CONSOLE_VGA is not set CONFIG_PCI_ROM_RUN=y # CONFIG_USBDEBUG_DIRECT is not set CONFIG_VAR_MTRR_HOLE=y CONFIG_LIFT_BSP_APIC_ID=y # CONFIG_WAIT_BEFORE_CPUS_INIT is not set CONFIG_HT3_SUPPORT=y # CONFIG_K8_REV_F_SUPPORT is not set # CONFIG_BOARD_TYAN_S1846 is not set # CONFIG_BOARD_TYAN_S2735 is not set # CONFIG_BOARD_TYAN_S2850 is not set # CONFIG_BOARD_TYAN_S2875 is not set # CONFIG_BOARD_TYAN_S2880 is not set # CONFIG_BOARD_TYAN_S2881 is not set # CONFIG_BOARD_TYAN_S2882 is not set # CONFIG_BOARD_TYAN_S2885 is not set # CONFIG_BOARD_TYAN_S2891 is not set # CONFIG_BOARD_TYAN_S2892 is not set # CONFIG_BOARD_TYAN_S2895 is not set # CONFIG_BOARD_TYAN_S2912 is not set CONFIG_BOARD_TYAN_S2912_FAM10=y # CONFIG_BOARD_TYAN_S4880 is not set # CONFIG_BOARD_TYAN_S4882 is not set CONFIG_VGA_ROM_RUN=y CONFIG_BOARD_ROMSIZE_KB_1024=y # CONFIG_COREBOOT_ROMSIZE_KB_128 is not set # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set CONFIG_COREBOOT_ROMSIZE_KB_1024=y # CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set # CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set CONFIG_COREBOOT_ROMSIZE_KB=1024 CONFIG_ROM_SIZE=0x10 CONFIG_ARCH_X86=y # CONFIG_AP_IN_SIPI_WAIT is not set CONFIG_ARCH=i386 CONFIG_ROMBASE=0x CONFIG_ROM_IMAGE_SIZE=0x1
[coreboot] [commit] r5398 - in trunk/src/mainboard: asus/a8v-e_se tyan/s2891
Author: stepan
Date: Fri Apr 9 17:39:21 2010
New Revision: 5398
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5398
Log:
zero warning days.
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by: Stefan Reinauer ste...@coresystems.de
Modified:
trunk/src/mainboard/asus/a8v-e_se/acpi_tables.c
trunk/src/mainboard/asus/a8v-e_se/romstage.c
trunk/src/mainboard/tyan/s2891/romstage.c
Modified: trunk/src/mainboard/asus/a8v-e_se/acpi_tables.c
==
--- trunk/src/mainboard/asus/a8v-e_se/acpi_tables.c Fri Apr 9 17:29:13
2010(r5397)
+++ trunk/src/mainboard/asus/a8v-e_se/acpi_tables.c Fri Apr 9 17:39:21
2010(r5398)
@@ -86,6 +86,7 @@
acpi_rsdp_t *rsdp;
acpi_srat_t *srat;
acpi_rsdt_t *rsdt;
+ acpi_madt_t *madt;
acpi_mcfg_t *mcfg;
acpi_fadt_t *fadt;
acpi_facs_t *facs;
Modified: trunk/src/mainboard/asus/a8v-e_se/romstage.c
==
--- trunk/src/mainboard/asus/a8v-e_se/romstage.cFri Apr 9 17:29:13
2010(r5397)
+++ trunk/src/mainboard/asus/a8v-e_se/romstage.cFri Apr 9 17:39:21
2010(r5398)
@@ -117,11 +117,6 @@
#include cpu/amd/model_fxx/fidvid.c
#include northbridge/amd/amdk8/resourcemap.c
-void hard_reset(void)
-{
- print_info(NO HARD RESET. FIX ME!\n);
-}
-
unsigned int get_sbdn(unsigned bus)
{
device_t dev;
Modified: trunk/src/mainboard/tyan/s2891/romstage.c
==
--- trunk/src/mainboard/tyan/s2891/romstage.c Fri Apr 9 17:29:13 2010
(r5397)
+++ trunk/src/mainboard/tyan/s2891/romstage.c Fri Apr 9 17:39:21 2010
(r5398)
@@ -79,8 +79,6 @@
static void sio_setup(void)
{
-
- unsigned value;
uint32_t dword;
uint8_t byte;
@@ -102,9 +100,7 @@
dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4);
dword |= (116);
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
-
#endif
-
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] build service results for r5397
Dear coreboot readers! This is the automatic build system of coreboot. The developer stepan checked in revision 5397 to the coreboot repository. This caused the following changes: Change Log: fix the broken nvidia chipset boards, remove more warnings. Signed-off-by: Stefan Reinauer ste...@coresystems.de Acked-by: Stefan Reinauer ste...@coresystems.de Build Log: Compilation of asus:a8n_e has been fixed Compilation of asus:a8v-e_se is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5397device=a8v-e_sevendor=asusnum=2 Compilation of tyan:s2891 has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Dualbios on GA-MA770-UD3
That could be very helpful for me. This register (LDN 7 reg EF) seems to be very interesting. Bit 0 is chip select, but also bits 2,4,5,6 are used in bios code. Bit 6 probably is some watchdog setting - setting it on with resetting other bits causes reboot in ~ a second. Hm the LDN 7 EF is not documented in old 0.4 version of datasheet. Also there is some moment in bios code about test reg 2F @ LDN F4 - it is toggled in some place and this could be important - may be enabling some undocumented features. Yes no docs again, Another interesting moment is checking for status of RI2 event (LDN 4 reg F1 bit 1) - it's almost first op in bios startup code. AFAICS RI2 event causes switch to chip 1 (Backup) and reboot - but there is no COM2 port on that board. And settings at reg 29 after boot told me that RI2 pin is switched to GPIO mode. So it is probably some debugging feature - if we find the way to set RI2 event then it seems to be an easy way to boot from backup bios. This bit is marked reserved. BTW all info I have on this is from it8718 datasheet, but it seems that the code is same for 8718 and 8720. Hmm the LDN F4 is really some debug feature... Maybe someone should get new datasheet ;) Rudolf Here is a dump of all regs of superio chip - may be it will help: entered cfg 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0 0 0 0 0 0 0 F4 0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 87 20 5 40 3A 0 10 0 40 80 0 0 1 0 0 0 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 60 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 70 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 80 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 90 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 E0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 selected LDN 0x00 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 87 20 5 40 3A 0 10 0 40 80 0 0 1 0 0 0 30 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 60 3 F0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 70 6 2 0 0 2 4 0 0 0 0 0 0 0 0 0 0 80 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 90 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 E0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F0 0 80 0 0 0 0 0 0 0 0 0 0 0 0 0 0 selected LDN 0x01 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 87 20 5 40 3A 0 10 0 40 80 0 0 1 0 0 0 30 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 60 3 F8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 70 4 2 0 0 4 4 0 0 0 0 0 0 0 0 0 0 80 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 90 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 E0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F0 0 50 50 50 0 0 0 0 0 0 0 0 0 0 0 0 selected LDN 0x02 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 87 20 5 40 3A 0 10 0 40 80 0 0 1 0 0 0 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 60 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 70 0 2 0 0 4 4 0 0 0 0 0 0 0 0 0 0 80 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 90 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 E0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F0 0 50 50 50 0 0 0 0 0 0 0 0 0 0 0 0 selected LDN 0x03 0
[coreboot] build service results for r5398
Dear coreboot readers! This is the automatic build system of coreboot. The developer stepan checked in revision 5398 to the coreboot repository. This caused the following changes: Change Log: zero warning days. Signed-off-by: Stefan Reinauer ste...@coresystems.de Acked-by: Stefan Reinauer ste...@coresystems.de Build Log: Compilation of asus:a8v-e_se has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [flashrom] Dualbios on GA-MA770-UD3
Also there is some moment in bios code about test reg 2F @ LDN F4 - it is toggled in some place and this could be important - may be enabling some undocumented features. The test register is only RW when written from LDN F4. Thanks, Rudolf -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Dualbios on GA-MA770-UD3
On 04/09/2010 07:56 PM, Rudolf Marek wrote: That could be very helpful for me. This register (LDN 7 reg EF) seems to be very interesting. Bit 0 is chip select, but also bits 2,4,5,6 are used in bios code. Bit 6 probably is some watchdog setting - setting it on with resetting other bits causes reboot in ~ a second. Hm the LDN 7 EF is not documented in old 0.4 version of datasheet. Also there is some moment in bios code about test reg 2F @ LDN F4 - it is toggled in some place and this could be important - may be enabling some undocumented features. Yes no docs again, Here is code fragment I mentioned - some bit is set then reset: (Not sure now that this code runs at all) seg003:E581 mov al, 7 seg003:E583 mov dx, 2Eh ; '.' seg003:E586 out dx, al seg003:E587 mov al, 0F4h ; '¯' ; LDN F4h ? seg003:E589 inc dx seg003:E58A out dx, al seg003:E58B dec dx seg003:E58C mov al, 2Fh ; '/' seg003:E58E out dx, al seg003:E58F mov al, 4 seg003:E591 inc dx seg003:E592 out dx, al ; write 2F = 4 seg003:E593 dec dx seg003:E594 mov cx, 0Ah seg003:E597 seg003:E597 delay2: ; CODE XREF: seg003:E599j seg003:E597 out 0EBh, al seg003:E599 loopdelay2 seg003:E59B mov al, 2Fh ; '/' seg003:E59D out dx, al seg003:E59E mov al, 0 seg003:E5A0 inc dx seg003:E5A1 out dx, al ; write 2F = 0 seg003:E5A2 mov dx, 2Eh ; '.' seg003:E5A5 mov al, 2 ; sio exit seg003:E5A7 out dx, al seg003:E5A8 out 0EBh, al seg003:E5AA inc dx seg003:E5AB mov al, 2 seg003:E5AD out dx, al Another interesting moment is checking for status of RI2 event (LDN 4 reg F1 bit 1) - it's almost first op in bios startup code. AFAICS RI2 event causes switch to chip 1 (Backup) and reboot - but there is no COM2 port on that board. And settings at reg 29 after boot told me that RI2 pin is switched to GPIO mode. So it is probably some debugging feature - if we find the way to set RI2 event then it seems to be an easy way to boot from backup bios. This bit is marked reserved. Here is info from datasheet that I found. It is Preliminary Specification V0.3 for IT8718F: LDN 04 APC/PME Status Register (PSR) (Index=F1h, Default=00h) ... bitdesc 40: No PS/2 Mouse Event Detected 1: PS/2 Mouse Event Detected 30: No Keyboard Event Detected 1: Keyboard Event Detected 20: No RI2# Event Detected 1: RI2# Event Detected 10: No RI1# Event Detected 1: RI1# Event Detected 00: No CIR event Detected 1: CIR event Detected So it seems that bit 2 is RI2 Event. It's first what is tested in bios code. Here is code fragment - it runs at very early startup - before initializing CPU, HT etc: seg003:447C loc_F447C: ; DATA XREF: seg003:off_F447Ao seg003:447C mov dx, 2Eh ; '.' ; enter SIO cfg mode seg003:447F mov al, 87h ; 'Ç' seg003:4481 out dx, al seg003:4482 mov al, 1 seg003:4484 out dx, al seg003:4485 mov al, 55h ; 'U' seg003:4487 out dx, al seg003:4488 mov al, 55h ; 'U' seg003:448A out dx, al seg003:448B mov cl, 4 seg003:448D mov dx, 2Eh ; '.' seg003:4490 mov al, 7 seg003:4492 out dx, al seg003:4493 out 0EBh, al seg003:4495 inc dx seg003:4496 mov al, cl seg003:4498 out dx, al ; select LDN 4 - EC seg003:4499 out 0EBh, al seg003:449B mov cl, 0F1h ; '¸' seg003:449D mov al, cl seg003:449F mov dx, 2Eh ; '.' seg003:44A2 out dx, al seg003:44A3 out 0EBh, al seg003:44A5 inc dx seg003:44A6 in al, dx ; read F1 - APC/PME Status seg003:44A7 out 0EBh, al seg003:44A9 testal, 4 ; check bit 2 - RI2# Event seg003:44AB jz short sio_exit_0 seg003:44AD mov cl, 7 seg003:44AF mov dx, 2Eh ; '.' seg003:44B2 mov al, 7 seg003:44B4 out dx, al seg003:44B5 out 0EBh, al seg003:44B7 inc dx seg003:44B8 mov al, cl
Re: [coreboot] [commit] r5330 - in trunk: . src/arch/i386
On 4/9/10 5:31 PM, Arne Georg Gleditsch wrote: Stefan Reinauer ste...@coresystems.de writes: Ah, the error above may occur if changing significant parts of Kconfig variables, such as tiny bootblock ;) please remove build/ and try again. I always do. :) This is reproducible as follows: $ svn co svn://coreboot.org/coreboot/trunk coreboot [..] Checked out revision 5396. $ cd coreboot $ perl -npi -e 's/(?=select TINY)/#/' src/mainboard/tyan/s2912_fam10/Kconfig add .config $ make oldconfig $ make Aaah! The Fam10 code is too big to work without tiny bootblock. Sorry I didn't recognize this earlier. Which code is missing in the final binary, do you say? Stefan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [PATCH] VIA C7 CAR fixes / cleanup
See patch
--
coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br.
Tel.: +49 761 7668825 • Fax: +49 761 7664613
Email: i...@coresystems.de • http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg • HRB 7656
Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866
This patch changes C7 CAR code to be a single assembler file instead
of the ugly mixture it was before. It also enables CAR for all C7 boards
(They were broken before)
There's another XIP patch missing from Patrick before C7 actually boots again,
but this wipes a bunch of problems with the current C7 code already.
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Index: src/cpu/via/car/cache_as_ram.lds
===
--- src/cpu/via/car/cache_as_ram.lds(revision 5398)
+++ src/cpu/via/car/cache_as_ram.lds(working copy)
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Carl-Daniel Hailfinger
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-SECTIONS {
- .init . : {
- _init = .;
- *(.init.text);
- *(.init.rodata);
- *(.init.rodata.*);
- . = ALIGN(16);
- _einit = .;
- }
-}
Index: src/cpu/via/car/cache_as_ram_post.c
===
--- src/cpu/via/car/cache_as_ram_post.c (revision 5398)
+++ src/cpu/via/car/cache_as_ram_post.c (working copy)
@@ -1,109 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 VIA Technologies, Inc.
- * (Written by Jason Zhao jasonz...@viatech.com.cn for VIA)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-__asm__ volatile (
- /*
- FIXME : backup stack in CACHE_AS_RAM into mmx and sse and after we get
STACK up, we restore that.
- It is only needed if we want to go back
- */
-
-/* We don't need cache as ram for now on */
-/* disable cache */
-movl%cr0, %eax\n\t
-orl$(0x130),%eax\n\t
-movl%eax, %cr0\n\t
-
-
-/* Set the default memory type and disable fixed and enable variable
MTRRs */
-movl$0x2ff, %ecx\n\t
- //movl$MTRRdefType_MSR, %ecx\n\t
-xorl%edx, %edx\n\t
-/* Enable Variable and Disable Fixed MTRRs */
-movl$0x0800, %eax\n\t
-wrmsr\n\t
-
-/* enable caching for first 1M using variable mtrr */
-movl$0x200, %ecx\n\t
-xorl%edx, %edx\n\t
-movl $(0 | 6), %eax\n\t
- //movl $(0 | MTRR_TYPE_WRBACK), %eax\n\t
-wrmsr\n\t
-
-/*jasonz...@viatech.com.cn, I enable cache for 0-7, 8-9,
e-f;
-if 1M cacheable,then when S3 resume, there is stange color on screen for 2
sec.
-suppose problem of a-df and cache .
-and in x86_setup_fixed_mtrrs()(mtrr.c), 0-256M is set cacheable.*/
-
-movl$0x201, %ecx\n\t
-movl$0x000f, %edx\n\t /* AMD 40 bit 0xff*/
- movl$((~(( 0 + 0x8) - 1)) | 0x800),
%eax\n\t
-wrmsr\n\t
-
-movl$0x202, %ecx\n\t
-xorl%edx, %edx\n\t
-movl $(0x8 | 6), %eax\n\t
-orl $(0 | 6), %eax\n\t
-wrmsr\n\t
-
-movl$0x203, %ecx\n\t
-movl$0x000f, %edx\n\t /* AMD 40 bit 0xff*/
- movl$((~(( 0 + 0x2) - 1)) | 0x800),
%eax\n\t
-wrmsr\n\t
-
-movl$0x204, %ecx\n\t
-xorl%edx, %edx\n\t
-movl $(0xc | 6), %eax\n\t
-
Re: [coreboot] [PATCH] VIA C7 CAR fixes / cleanup
Am 09.04.2010 21:41, schrieb Stefan Reinauer: See patch Boot tested on via/vt8454c, so Acked-by: Patrick Georgi patrick.geo...@coresystems.de -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r5399 - in trunk: . src/arch/i386 src/cpu src/cpu/via/car src/cpu/via/model_c7 src/mainboard/bcom/winnetp680 src/mainboard/jetway/j7f24 src/mainboard/via/epia-cn src/mainboard/via/
Author: stepan Date: Fri Apr 9 22:36:29 2010 New Revision: 5399 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5399 Log: This patch changes C7 CAR code to be a single assembler file instead of the ugly mixture it was before. It also enables CAR for all C7 boards Signed-off-by: Stefan Reinauer ste...@coresystems.de Acked-by: Patrick Georgi patrick.geo...@coresystems.de Deleted: trunk/src/cpu/via/car/cache_as_ram.lds trunk/src/cpu/via/car/cache_as_ram_post.c Modified: trunk/Makefile trunk/src/arch/i386/Makefile.inc trunk/src/cpu/Kconfig trunk/src/cpu/via/car/cache_as_ram.inc trunk/src/cpu/via/model_c7/Kconfig trunk/src/mainboard/bcom/winnetp680/romstage.c trunk/src/mainboard/jetway/j7f24/Kconfig trunk/src/mainboard/jetway/j7f24/romstage.c trunk/src/mainboard/via/epia-cn/Kconfig trunk/src/mainboard/via/epia-cn/romstage.c trunk/src/mainboard/via/epia-m700/Kconfig trunk/src/mainboard/via/epia-m700/romstage.c trunk/src/mainboard/via/pc2500e/Kconfig trunk/src/mainboard/via/pc2500e/romstage.c trunk/src/mainboard/via/vt8454c/Kconfig trunk/src/mainboard/via/vt8454c/romstage.c Modified: trunk/Makefile == --- trunk/Makefile Fri Apr 9 17:39:21 2010(r5398) +++ trunk/Makefile Fri Apr 9 22:36:29 2010(r5399) @@ -274,8 +274,10 @@ CBFS_COMPRESS_FLAG:=l CBFS_PAYLOAD_COMPRESS_FLAG:= +CBFS_PAYLOAD_COMPRESS_NAME:=none ifeq ($(CONFIG_COMPRESSED_PAYLOAD_LZMA),y) CBFS_PAYLOAD_COMPRESS_FLAG:=l +CBFS_PAYLOAD_COMPRESS_NAME:=LZMA endif coreboot: prepare $(obj)/coreboot.rom Modified: trunk/src/arch/i386/Makefile.inc == --- trunk/src/arch/i386/Makefile.incFri Apr 9 17:39:21 2010(r5398) +++ trunk/src/arch/i386/Makefile.incFri Apr 9 22:36:29 2010(r5399) @@ -37,7 +37,7 @@ ifeq ($(CONFIG_PAYLOAD_NONE),y) printf PAYLOAD\e[1;31mnone (as specified by user)\e[0m\n else - printf PAYLOAD$(CONFIG_FALLBACK_PAYLOAD_FILE) $(CBFS_PAYLOAD_COMPRESS_FLAG)\n + printf PAYLOAD$(CONFIG_FALLBACK_PAYLOAD_FILE) (compression: $(CBFS_PAYLOAD_COMPRESS_NAME))\n $(CBFSTOOL) $...@.tmp add-payload $(CONFIG_FALLBACK_PAYLOAD_FILE) $(CONFIG_CBFS_PREFIX)/payload $(CBFS_PAYLOAD_COMPRESS_FLAG) endif ifeq ($(CONFIG_VGA_BIOS),y) @@ -165,11 +165,7 @@ ifeq ($(CONFIG_CPU_INTEL_SOCKET_MFCBGA479),y) crt0s += $(src)/cpu/x86/car/cache_as_ram.inc endif -# should be CONFIG_CPU_VIA_C7, but bcom/winnetp680, jetway/j7f24, via/epia-cn, via/pc2500e don't use CAR yet -ifeq ($(CONFIG_BOARD_VIA_VT8454C),y) -crt0s += $(src)/cpu/via/car/cache_as_ram.inc -endif -ifeq ($(CONFIG_BOARD_VIA_EPIA_M700),y) +ifeq ($(CONFIG_CPU_VIA_C7),y) crt0s += $(src)/cpu/via/car/cache_as_ram.inc endif # who else could use this? @@ -208,7 +204,7 @@ ifeq ($(CONFIG_ROMCC),y) ROMCCFLAGS ?= -mcpu=p2 -O2 -$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/romcc $(OPTION_TABLE_H) $(obj)/build.h +$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/romcc $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h printf ROMCC romstage.inc\n $(ROMCC) -c -S $(ROMCCFLAGS) -D__PRE_RAM__ -I. $(INCLUDES) $ -o $@ else Modified: trunk/src/cpu/Kconfig == --- trunk/src/cpu/Kconfig Fri Apr 9 17:39:21 2010(r5398) +++ trunk/src/cpu/Kconfig Fri Apr 9 22:36:29 2010(r5399) @@ -5,7 +5,7 @@ config USE_DCACHE_RAM bool - default n + default !ROMCC config DCACHE_RAM_BASE hex Modified: trunk/src/cpu/via/car/cache_as_ram.inc == --- trunk/src/cpu/via/car/cache_as_ram.inc Fri Apr 9 17:39:21 2010 (r5398) +++ trunk/src/cpu/via/car/cache_as_ram.inc Fri Apr 9 22:36:29 2010 (r5399) @@ -63,6 +63,20 @@ wrmsr jmp clear_fixed_var_mtrr + +fixed_mtrr_msr: + .long 0x250, 0x258, 0x259 + .long 0x268, 0x269, 0x26A + .long 0x26B, 0x26C, 0x26D + .long 0x26E, 0x26F + +var_mtrr_msr: + .long 0x200, 0x201, 0x202, 0x203 + .long 0x204, 0x205, 0x206, 0x207 + .long 0x208, 0x209, 0x20A, 0x20B + .long 0x20C, 0x20D, 0x20E, 0x20F + .long 0x000 /* NULL, end of table */ + clear_fixed_var_mtrr_out: /* MTRRPhysBase */ movl$0x200, %ecx @@ -163,17 +177,113 @@ /* We need to set ebp ? No need */ movl%esp, %ebp pushl %eax /* bist */ - callstage1_main - /* We will not go back */ + callmain + + /* +* TODO: Backup stack in CACHE_AS_RAM into MMX and SSE and after we +* get STACK up, we
[coreboot] [PATCH] clean up AMD Geode LX CAR code
See patch -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 Drop ASM_CONSOLE_LOGLEVEL from LX car code. We do output in C in copy_and_run / later. Call copy_and_run instead of cbfs_and_run_core because we can choose the coreboot_ram filename in C instead of Assembler. Signed-off-by: Stefan Reinauer ste...@coresystems.de Index: src/cpu/amd/model_lx/cache_as_ram.inc === --- src/cpu/amd/model_lx/cache_as_ram.inc (revision 5398) +++ src/cpu/amd/model_lx/cache_as_ram.inc (working copy) @@ -17,10 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef ASM_CONSOLE_LOGLEVEL -#define ASM_CONSOLE_LOGLEVEL CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -#endif - #defineLX_STACK_BASE CONFIG_DCACHE_RAM_BASE /* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as coreboot normal stack */ #defineLX_STACK_ENDLX_STACK_BASE+(CONFIG_DCACHE_RAM_SIZE-1) @@ -204,13 +200,11 @@ /* clear boot_complete flag */ xorl%ebp, %ebp __main: + post_code(0x11) /* post 11 */ - /* -* Copy data into RAM and clear the BSS. Since these segments -* isn\'t really that big we just copy/clear using bytes, not -* double words. + /* TODO For suspend/resume the cache will have to live between +* CONFIG_RAMBASE and CONFIG_RAMTOP */ - post_code(0x11) /* post 11 */ cld /* clear direction flag */ @@ -220,67 +214,10 @@ */ movl%ebp, %esi pushl %esi - pushl $str_coreboot_ram_name - call cbfs_and_run_core + call copy_and_run .Lhlt: post_code(0xee) /* post fail ee */ hlt jmp .Lhlt -#ifdef __CRT_CONSOLE_TX_STRING - /* Uses esp, ebx, ax, dx */ -crt_console_tx_string: - mov (%ebx), %al - inc %ebx - cmp $0, %al - jne 9f - RETSP -9: -/* Base Address */ -#ifndef CONFIG_TTYS0_BASE -#define CONFIG_TTYS0_BASE 0x3f8 -#endif -/* Data */ -#define TTYS0_RBR (CONFIG_TTYS0_BASE+0x00) - -/* Control */ -#define TTYS0_TBR TTYS0_RBR -#define TTYS0_IER (CONFIG_TTYS0_BASE+0x01) -#define TTYS0_IIR (CONFIG_TTYS0_BASE+0x02) -#define TTYS0_FCR TTYS0_IIR -#define TTYS0_LCR (CONFIG_TTYS0_BASE+0x03) -#define TTYS0_MCR (CONFIG_TTYS0_BASE+0x04) -#define TTYS0_DLL TTYS0_RBR -#define TTYS0_DLM TTYS0_IER - -/* Status */ -#define TTYS0_LSR (CONFIG_TTYS0_BASE+0x05) -#define TTYS0_MSR (CONFIG_TTYS0_BASE+0x06) -#define TTYS0_SCR (CONFIG_TTYS0_BASE+0x07) - - mov %al, %ah -10:mov $TTYS0_LSR, %dx - inb %dx, %al - test$0x20, %al - je 10b - mov $TTYS0_TBR, %dx - mov %ah, %al - outb%al, %dx - - jmp crt_console_tx_string -#endif /* __CRT_CONSOLE_TX_STRING */ - -#if defined(CONSOLE_DEBUG_TX_STRING) (ASM_CONSOLE_LOGLEVEL BIOS_DEBUG) -.section .rom.data -#if CONFIG_COMPRESS -str_copying_to_ram: .string Uncompressing coreboot to ram.\r\n -#else -str_copying_to_ram: .string Copying coreboot to ram.\r\n -#endif -str_pre_main:.string Jumping to coreboot.\r\n -.previous - -#endif /* ASM_CONSOLE_LOGLEVEL BIOS_DEBUG */ -str_coreboot_ram_name: .ascii CONFIG_CBFS_PREFIX - .string /coreboot_ram -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] clean up AMD Geode LX CAR code
Acked-by: Patrick Georgi patrick.geo...@coresystems.de -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r5400 - trunk/src/cpu/amd/model_lx
Author: stepan Date: Fri Apr 9 23:05:36 2010 New Revision: 5400 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5400 Log: Drop ASM_CONSOLE_LOGLEVEL from LX car code. We do output in C in copy_and_run / later. Call copy_and_run instead of cbfs_and_run_core because we can choose the coreboot_ram filename in C instead of Assembler. Signed-off-by: Stefan Reinauer ste...@coresystems.de Acked-by: Patrick Georgi patrick.geo...@coresystems.de Modified: trunk/src/cpu/amd/model_lx/cache_as_ram.inc Modified: trunk/src/cpu/amd/model_lx/cache_as_ram.inc == --- trunk/src/cpu/amd/model_lx/cache_as_ram.inc Fri Apr 9 22:36:29 2010 (r5399) +++ trunk/src/cpu/amd/model_lx/cache_as_ram.inc Fri Apr 9 23:05:36 2010 (r5400) @@ -17,10 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef ASM_CONSOLE_LOGLEVEL -#define ASM_CONSOLE_LOGLEVEL CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -#endif - #defineLX_STACK_BASE CONFIG_DCACHE_RAM_BASE /* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as coreboot normal stack */ #defineLX_STACK_ENDLX_STACK_BASE+(CONFIG_DCACHE_RAM_SIZE-1) @@ -204,13 +200,11 @@ /* clear boot_complete flag */ xorl%ebp, %ebp __main: + post_code(0x11) /* post 11 */ - /* -* Copy data into RAM and clear the BSS. Since these segments -* isn\'t really that big we just copy/clear using bytes, not -* double words. + /* TODO For suspend/resume the cache will have to live between +* CONFIG_RAMBASE and CONFIG_RAMTOP */ - post_code(0x11) /* post 11 */ cld /* clear direction flag */ @@ -220,67 +214,10 @@ */ movl%ebp, %esi pushl %esi - pushl $str_coreboot_ram_name - call cbfs_and_run_core + call copy_and_run .Lhlt: post_code(0xee) /* post fail ee */ hlt jmp .Lhlt -#ifdef __CRT_CONSOLE_TX_STRING - /* Uses esp, ebx, ax, dx */ -crt_console_tx_string: - mov (%ebx), %al - inc %ebx - cmp $0, %al - jne 9f - RETSP -9: -/* Base Address */ -#ifndef CONFIG_TTYS0_BASE -#define CONFIG_TTYS0_BASE 0x3f8 -#endif -/* Data */ -#define TTYS0_RBR (CONFIG_TTYS0_BASE+0x00) - -/* Control */ -#define TTYS0_TBR TTYS0_RBR -#define TTYS0_IER (CONFIG_TTYS0_BASE+0x01) -#define TTYS0_IIR (CONFIG_TTYS0_BASE+0x02) -#define TTYS0_FCR TTYS0_IIR -#define TTYS0_LCR (CONFIG_TTYS0_BASE+0x03) -#define TTYS0_MCR (CONFIG_TTYS0_BASE+0x04) -#define TTYS0_DLL TTYS0_RBR -#define TTYS0_DLM TTYS0_IER - -/* Status */ -#define TTYS0_LSR (CONFIG_TTYS0_BASE+0x05) -#define TTYS0_MSR (CONFIG_TTYS0_BASE+0x06) -#define TTYS0_SCR (CONFIG_TTYS0_BASE+0x07) - - mov %al, %ah -10:mov $TTYS0_LSR, %dx - inb %dx, %al - test$0x20, %al - je 10b - mov $TTYS0_TBR, %dx - mov %ah, %al - outb%al, %dx - - jmp crt_console_tx_string -#endif /* __CRT_CONSOLE_TX_STRING */ - -#if defined(CONSOLE_DEBUG_TX_STRING) (ASM_CONSOLE_LOGLEVEL BIOS_DEBUG) -.section .rom.data -#if CONFIG_COMPRESS -str_copying_to_ram: .string Uncompressing coreboot to ram.\r\n -#else -str_copying_to_ram: .string Copying coreboot to ram.\r\n -#endif -str_pre_main:.string Jumping to coreboot.\r\n -.previous - -#endif /* ASM_CONSOLE_LOGLEVEL BIOS_DEBUG */ -str_coreboot_ram_name: .ascii CONFIG_CBFS_PREFIX - .string /coreboot_ram -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Infrastructure Projects
Hi, I just updated our central upcoming infrastructure changes list. http://www.coreboot.org/Infrastructure_Projects If you can / want to work on any of these issues, step up now :-) It's essential that we drop as many special cases from the code as possible and only let new ones in if there is no better way. Also, please help completing the list. Stefan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [PATCH]CAR and Tiny bootblock for via/vt8454c (and fixes that help other via c7 based systems)
Hi, attached patch does: - move the XIP_ROM_* flags to src/cpu/x86/Kconfig exclusively - set them to span the last 64k, instead of the last 128k by default - fixes via CAR for tiny bootblock - enabled tiny bootblock for via/vt8454c Other C7 based boards should be simple to adapt, too. They will however require some refactoring if ROM mappings must be configured. Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de Index: src/Kconfig === --- src/Kconfig (revision 5399) +++ src/Kconfig (working copy) @@ -116,14 +116,6 @@ int default 36 -config XIP_ROM_BASE - hex - default 0xfffe - -config XIP_ROM_SIZE - hex - default 0x2 - config LOGICAL_CPUS bool default y Index: src/cpu/via/car/cache_as_ram.inc === --- src/cpu/via/car/cache_as_ram.inc(revision 5399) +++ src/cpu/via/car/cache_as_ram.inc(working copy) @@ -139,7 +139,7 @@ xorl$0x5c5c5c5c,%eax rep stosl - movlCONFIG_XIP_ROM_BASE, %esi + movlREAL_XIP_ROM_BASE, %esi movl%esi, %edi movl$(CONFIG_XIP_ROM_SIZE2), %ecx rep lodsl @@ -241,10 +241,10 @@ movl$((~(( 0 + 0x4) - 1)) | 0x800), %eax wrmsr - /* cache CONFIG_XIP_ROM_BASE-SIZE to speedup coreboot code */ + /* cache XIP_ROM_BASE-SIZE to speedup coreboot code */ movl$0x206, %ecx xorl%edx, %edx - movl $CONFIG_XIP_ROM_BASE,%eax + movl $REAL_XIP_ROM_BASE,%eax orl $(0 | 6), %eax wrmsr Index: src/cpu/x86/Kconfig === --- src/cpu/x86/Kconfig (revision 5399) +++ src/cpu/x86/Kconfig (working copy) @@ -25,8 +25,8 @@ config XIP_ROM_BASE hex - default 0xfffe + default 0x config XIP_ROM_SIZE hex - default 0x2 + default 0x1 Index: src/mainboard/via/vt8454c/Kconfig === --- src/mainboard/via/vt8454c/Kconfig (revision 5399) +++ src/mainboard/via/vt8454c/Kconfig (working copy) @@ -12,6 +12,7 @@ select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_512 select USE_DCACHE_RAM + select TINY_BOOTBLOCK config MAINBOARD_DIR string -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r5401 - trunk/src/mainboard/asrock/939a785gmh
Author: oxygene Date: Sat Apr 10 00:25:27 2010 New Revision: 5401 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5401 Log: We don't define LB_CKS_* per board anymore: build_opt_tbl figures them out for us. Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de Acked-by: Patrick Georgi patrick.geo...@coresystems.de Modified: trunk/src/mainboard/asrock/939a785gmh/Kconfig Modified: trunk/src/mainboard/asrock/939a785gmh/Kconfig == --- trunk/src/mainboard/asrock/939a785gmh/Kconfig Fri Apr 9 23:05:36 2010(r5400) +++ trunk/src/mainboard/asrock/939a785gmh/Kconfig Sat Apr 10 00:25:27 2010(r5401) @@ -52,16 +52,6 @@ default 0x0 depends on BOARD_ASROCK_939A785GMH -config LB_CKS_RANGE_END - int - default 122 - depends on BOARD_ASROCK_939A785GMH - -config LB_CKS_LOC - int - default 123 - depends on BOARD_ASROCK_939A785GMH - config MAINBOARD_PART_NUMBER string default 939A785GMH -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
