[coreboot] [PATCH][superiotool] ITE IT8500 EC support
The attached patch adds a register table for the IT8500 embedded controller. Here is a sample of the output: superiotool r5679 Found ITE IT8500 (id=0x8500, rev=0x1) at 0x2e Register dump: idx 20 21 22 23 25 2d 2e 2f 30 val 85 00 01 01 00 00 00 00 01 def 85 00 01 01 00 00 NA NA 00 LDN 0x04 (System Wake-Up Control (SWUC)) idx 30 60 61 62 63 70 71 val 01 00 00 00 00 00 01 def 00 00 00 00 00 00 01 LDN 0x05 (KBC/Mouse Interface) idx 30 60 61 62 63 70 71 val 01 00 00 00 00 0c 01 def 00 00 00 00 00 0c 01 LDN 0x06 (KBC/Keyboard Interface) idx 30 60 61 62 63 70 71 val 01 00 60 00 64 01 01 def 00 00 60 00 64 01 01 LDN 0x0f (Shared Memory/Flash Interface (SMFI)) idx 30 60 61 62 63 70 71 f4 val 01 02 00 00 00 00 00 09 def 00 00 00 00 00 00 00 NA LDN 0x10 (BRAM) idx 30 62 63 70 71 f3 f4 f5 val 01 05 00 08 01 00 3f 3f def 00 00 72 08 01 NA NA NA LDN 0x11 (Power Management I/F Channel 1 (PMC1)) idx 30 60 61 62 63 70 71 val 01 00 62 00 66 00 01 def 00 00 62 00 66 01 01 LDN 0x12 (Power Management I/F Channel 2 (PMC2)) idx 30 60 61 62 63 64 65 70 71 f0 val 01 00 80 00 84 04 00 02 01 00 def 00 00 68 00 6c 00 00 01 01 NA Found SMSC SCH5317 (id=0x85, rev=0x00) at 0x2e No dump available for this Super I/O Signed-off by: Donald Huang (donald.hu...@ite.com.tw) Signed-off by: Yung-chieh Lo (yj...@google.com) Signed-off by: David Hendricks (dhend...@google.com) -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH][superiotool] ITE IT8500 EC support
On 8/10/10 4:26 AM, donald.hu...@ite.com.tw wrote: The attached patch adds a register table for the IT8500 embedded controller. Here is a sample of the output: superiotool r5679 [..] Signed-off by: Donald Huang (donald.hu...@ite.com.tw mailto:donald.hu...@ite.com.tw) Signed-off by: Yung-chieh Lo (yj...@google.com mailto:yj...@google.com) Signed-off by: David Hendricks (dhend...@google.com mailto:dhend...@google.com) Dear Donald, thank you very much for you work. However, it seems the patch didn't arrive on the mailing list. Can you try sending it again? Regards, Stefan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH][superiotool] Quit probe_idregs_* early if chip_found is set
On 8/9/10 11:41 PM, David Hendricks wrote: Some chips do not require enter/exit sequences. This causes them to be detected and printed multiple times in probe_idregs_* functions where a simple series of enter -- probe/print -- exit calls are made. This patch adds a simple check after each set of those calls to make the functions quit after a chip is found. Great catch. Signed-off by: David Hendricks (dhend...@google.com mailto:dhend...@google.com) Acked-by: Stefan Reinauer ste...@coresystems.de -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH][superiotool] ITE IT8500 EC support
Dear Stefan, OK! Please see the attached file. BR, Donald From: Stefan Reinauer [mailto:stefan.reina...@coresystems.de] Sent: Tuesday, August 10, 2010 2:47 PM To: Donald Huang (黃麒豪) Cc: coreboot@coreboot.org; dhend...@google.com; yj...@google.com Subject: Re: [coreboot] [PATCH][superiotool] ITE IT8500 EC support On 8/10/10 4:26 AM, donald.hu...@ite.com.tw wrote: The attached patch adds a register table for the IT8500 embedded controller. Here is a sample of the output: superiotool r5679 [..] Signed-off by: Donald Huang (donald.hu...@ite.com.tw) Signed-off by: Yung-chieh Lo (yj...@google.com) Signed-off by: David Hendricks (dhend...@google.com) Dear Donald, thank you very much for you work. However, it seems the patch didn't arrive on the mailing list. Can you try sending it again? Regards, Stefan it8500_ec.patch Description: it8500_ec.patch -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Coreboot-v4 and protected_stage0?
ljmp $ROM_CODE_SEG, $protected_stage0 Where is the definition of the symbol, protected_stage0? Thank you to read my message. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Coreboot-v4 and protected_stage0?
On 8/10/10 3:24 PM, ali hagigat wrote: ljmp $ROM_CODE_SEG, $protected_stage0 Where is the definition of the symbol, protected_stage0? Thank you to read my message. The file you are looking at, src/arch/i386/init/entry.S is unused. The file was supposed to replace src/cpu/x86/16bit/entry16.inc src/cpu/x86/16bit/reset16.inc src/cpu/x86/32bit/entry32.inc but that was never finished it seems. Look at crt0s in arch/i386/Makefile.inc Stefan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] DL145 G1 with dual dualcore CPU using coreboot ?
On Tue, Aug 10, 2010 at 5:43 AM, Oskar Enoksson e...@lysator.liu.se wrote: Myles Watson wrote: On Mon, Aug 9, 2010 at 8:16 AM, Myles Watson myle...@gmail.com wrote: On Sat, Aug 7, 2010 at 9:57 AM, Oskar Enoksson e...@lysator.liu.se wrote: Ok, I'm able to hotswap the BIOS chip, burn it and hot-remove it without stopping the development server , then moving it to the target server and power it up (although it takes some effort to avoid bending the pins) Great. However I'm not getting any output whatsoever from the target server. Nothing on the serial port, nothing on the VGA output. Have you tested the serial port under Linux? I'm surprised that you don't see anything since the board is so similar. I wouldn't even copy the directory until you see serial output. If you've tested the serial port under Linux, then I would build coreboot images for boards with the same chipsets SuperIO until you find one that gives you some output. Thanks, Myles I'm finally getting output now. The problem was that this server has a IPMI board (HP calls it ILO Integrated Lights Out management). Somehow the server's hardware serial port is initially redirected to this management board and not to the RS232 port. By connecting to the management board through the dedicated IPMI ethernet port and using telnet I'm able to see the output that coreboot believes it's writing to the RS232 port. Good catch. ... and after trying a few different motherboard configurations I got success: an image built from the Tyan S2881 image boots. Even the VGA screen wakes up in the end, displaying the last output from coreboot. Here is the end of the output: coreboot memory table: 0. -0fff: CONFIGURATION TABLES 1. 1000-0009: RAM 2. 000c-3ffe: RAM 3. 3fff-3fff: CONFIGURATION TABLES Wrote coreboot table at: 3fffe000 - 3fffe1a8 checksum 5169 coreboot table: 424 bytes. POST: 0x9e 0. FREE SPACE 4000 1. GDT 3fff0200 0200 2. IRQ TABLE 3fff0400 1000 3. SMP TABLE 3fff1400 1000 4. ACPI 3fff2400 bc00 5. COREBOOT 3fffe000 2000 Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff8 + 38 + cb8a + align - fff8cc00 Check CBFS: follow chain: fff8cc00 + 28 + 633b8 + align - CBFS: Could not find file fallback/payload Boot failed. So you need to add a payload (SeaBIOS, FILO, Grub...) It looks promising. Myles -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] dongle.py!!
update: dongle.py -c /dev/term/1 $(obj)/coreboot.rom EOF What was dongle.py in top makefile? -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] dongle.py!!
On 8/10/10 5:06 PM, ali hagigat wrote: update: dongle.py -c /dev/term/1 $(obj)/coreboot.rom EOF What was dongle.py in top makefile? It's the program controlling this: http://www.coreboot.org/FlexyICE Unless you have one of those you don't need to worry. Stefan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] dongle.py!!
Am 10.08.2010 17:06, schrieb ali hagigat: update: dongle.py -c /dev/term/1 $(obj)/coreboot.rom EOF What was dongle.py in top makefile? dongle.py is a utility to control the Artec FlexyICE dongle (hence the name of the tool). The dongle serves as a PLCC emulator, with cuts down on roundtrip times for developers that use it. See http://www.coreboot.org/Artecgroup_programmable_LPC_dongle Given that you manage to ask only about the less important parts of the tree, I guess I can be happy to assume that you have no issues with the basic operation of the tree. Patrick -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] dongle.py!!
My main questions are not answered! Starting from top makefile, what is first rule that is executed? How this makefile causes other makefiles inside the subdirectories are called? Please mention the line which does this. Thank you. On Tue, Aug 10, 2010 at 7:41 PM, Patrick Georgi patr...@georgi-clan.dewrote: Am 10.08.2010 17:06, schrieb ali hagigat: update: dongle.py -c /dev/term/1 $(obj)/coreboot.rom EOF What was dongle.py in top makefile? dongle.py is a utility to control the Artec FlexyICE dongle (hence the name of the tool). The dongle serves as a PLCC emulator, with cuts down on roundtrip times for developers that use it. See http://www.coreboot.org/Artecgroup_programmable_LPC_dongle Given that you manage to ask only about the less important parts of the tree, I guess I can be happy to assume that you have no issues with the basic operation of the tree. Patrick -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] dongle.py!!
ali hagigat wrote: Starting from top makefile, what is first rule that is executed? I think this depends on which target you are building. Why do you ask? How this makefile causes other makefiles inside the subdirectories are called? Please mention the line which does this. It's not one line. coreboot uses a Makefile scheme which was inspired by the Linux kernel Makefile scheme and rules. By studying the Makefile rules in coreboot you'll see that it's not as simple as you may expect. In any case, a starting point for studying the Makefile rules might be the line starting with: includemakefiles= in the top level Makefile. //Peter -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] dongle.py!!
do a make and watch what gets executed. There's no substitute for observation and interaction with the tool. ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] dongle.py!!
On Tue, Aug 10, 2010 at 8:43 AM, ali hagigat hagigat...@gmail.com wrote: My main questions are not answered! Starting from top makefile, what is first rule that is executed? How this makefile causes other makefiles inside the subdirectories are called? Please mention the line which does this. There's no recursive make. ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] DL145 G1 with dual dualcore CPU using coreboot ?
That IPMI stuff is a huge pain in the neck. You can try to disable it as I did on the Dell. src/mainboard/dell/s1850/romstage.c ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] dongle.py!!
On Tue, Aug 10, 2010 at 9:03 AM, ron minnich rminn...@gmail.com wrote: On Tue, Aug 10, 2010 at 8:43 AM, ali hagigat hagigat...@gmail.com wrote: My main questions are not answered! Starting from top makefile, what is first rule that is executed? How this makefile causes other makefiles inside the subdirectories are called? Please mention the line which does this. There's no recursive make. if only ;-) http://miller.emu.id.au/pmiller/books/rmch/ http://miller.emu.id.au/pmiller/books/rmch/ -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] dongle.py!!
Am 10.08.2010 22:40, schrieb David Hendricks: There's no recursive make. if only ;-) The only recursive make in coreboot is when you use the scanbuild feature. In which case the toplevel Makefile calls itself, wrapped in scan-build. Everything else is iterative inclusion of makefile fragments (manually tail-optimized recursion, if you wish) Our main bottleneck right now is lots and lots of directory accesses, for all the files involved. Our main issue with the dependency graph is that some dependencies are hard to represent sanely in make. Patrick -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH][superiotool] ITE IT8500 EC support
On Mon, Aug 9, 2010 at 11:47 PM, Stefan Reinauer stefan.reina...@coresystems.de wrote: On 8/10/10 4:26 AM, donald.hu...@ite.com.tw wrote: The attached patch adds a register table for the IT8500 embedded controller. Here is a sample of the output: superiotool r5679 [..] Signed-off by: Donald Huang (donald.hu...@ite.com.tw) Signed-off by: Yung-chieh Lo (yj...@google.com) Signed-off by: David Hendricks (dhend...@google.com) Dear Donald, thank you very much for you work. However, it seems the patch didn't arrive on the mailing list. Can you try sending it again? Hey Stefan, I think your mail filters may be preventing the patch from coming thru. Try downloading attachment-0001.obj from http://www.coreboot.org/pipermail/coreboot/2010-August/059616.html . -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r5690 - trunk/util/superiotool
Author: hailfinger
Date: Wed Aug 11 01:34:51 2010
New Revision: 5690
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5690
Log:
Superiotool support for the IT8500 embedded controller.
Signed-off-by: Donald Huang donald.hu...@ite.com.tw
Signed-off-by: Yung-chieh Lo yj...@google.com
Signed-off-by: David Hendricks dhend...@google.com
Acked-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net
Modified:
trunk/util/superiotool/ite.c
Modified: trunk/util/superiotool/ite.c
==
--- trunk/util/superiotool/ite.cTue Aug 10 01:13:13 2010(r5689)
+++ trunk/util/superiotool/ite.cWed Aug 11 01:34:51 2010(r5690)
@@ -29,6 +29,32 @@
static const struct superio_registers reg_table[] = {
{0x8228, IT8228E, {
{EOT}}},
+ {0x8500, IT8500B/E, {
+ {NOLDN, NULL,
+ {0x20,0x21,0x22,0x23,0x25,0x2d,0x2e,0x2f,0x30,EOT},
+ {0x85,0x00,0x01,0x01,0x00,0x00,NANA,NANA,0x00,EOT}},
+ {0x04, System Wake-Up Control (SWUC),
+ {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT},
+ {0x00,0x00,0x00,0x00,0x00,0x00,0x01,EOT}},
+ {0x05, KBC/Mouse Interface,
+ {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT},
+ {0x00,0x00,0x00,0x00,0x00,0x0c,0x01,EOT}},
+ {0x06, KBC/Keyboard Interface,
+ {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT},
+ {0x00,0x00,0x60,0x00,0x64,0x01,0x01,EOT}},
+ {0x0f, Shared Memory/Flash Interface (SMFI),
+ {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0xf4,EOT},
+ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,NANA,EOT}},
+ {0x10, BRAM,
+ {0x30,0x62,0x63,0x70,0x71,0xf3,0xf4,0xf5,EOT},
+ {0x00,0x00,0x72,0x08,0x01,NANA,NANA,NANA,EOT}},
+ {0x11, Power Management I/F Channel 1 (PMC1),
+ {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT},
+ {0x00,0x00,0x62,0x00,0x66,0x01,0x01,EOT}},
+ {0x12, Power Management I/F Channel 2 (PMC2),
+ {0x30,0x60,0x61,0x62,0x63,0x64,0x65,0x70,0x71,0xf0,EOT},
+
{0x00,0x00,0x68,0x00,0x6c,0x00,0x00,0x01,0x01,NANA,EOT}},
+ {EOT}}},
{0x8502, IT8502E/TE/G, {
{NOLDN, NULL,
{0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29,
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH][superiotool] ITE IT8500 EC support
On 10.08.2010 10:10, donald.hu...@ite.com.tw wrote: On 8/10/10 4:26 AM, donald.hu...@ite.com.tw wrote: The attached patch adds a register table for the IT8500 embedded controller. Here is a sample of the output: Signed-off by: Donald Huang (donald.hu...@ite.com.tw) Signed-off by: Yung-chieh Lo (yj...@google.com) Signed-off by: David Hendricks (dhend...@google.com) Acked-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net I changed IT8500 to IT8500B/E because it seems that chip has multiple variants, and I wanted to make sure all of them are listed. Thanks for your patch, committed in r5690. Regards, Carl-Daniel -- http://www.hailfinger.org/ -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] amd rs780 gfx lane reversal patch
Hi, all Amd rs780 feature Lane reversal is tested. Please see the attachment Thanks -- Regards Kerry She kerry@amd.com amd_rs780_gfx_lane_reversal.patch Description: amd_rs780_gfx_lane_reversal.patch -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
