Re: [coreboot] [patch] nvramtool hardware access on NetBSD
* Georgi, Patrick [110208 11:26]: > More general question (shouldn't stop anyone from committing this > patch): Should we move hardware access code to directio and use its API > on all platforms (not just Darwin, and - in theory - win32)? > Though in that case, we might want to import directio to the coreboot > tree. +1 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Help with RX serial interrupts?
Looks like a RX pin multiplexing is wrong, therefore no IRQ is generated? Rudolf PS: I go for a holiday so don't expect much answers from me. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Help with RX serial interrupts?
On 02/08/2011 11:32 PM, Votier, Sean (DS-1) wrote: > Designation: Non-SSA/Finmeccanica > > > Thanks for the reply Alex. I'll do my best to help as much as I can. Though make sure next time you hit the "reply all" or "reply list" button, as your message didn't make it to the list. > No, I'm not totally sure. I've looked through the docs and picked the > values for the registers that seem appropriate. There's the problem right there. There is a big difference between "seems" and "are". I'm working on a K8T800 board, the southbridge containing the IOAPIC is already supported, and yet it still doesn't work. Try to rip off as much data as you can from the mfg BIOS. That's all I can tell you, I'm not an expert in the field. > I looked though the core > boot code to see what was in there but their IRQ scheme it's much more > complicated than I need and it didn't lend itself well to my particular > situation. The problem with IRQ's is that they are a bitch to > troubleshoot, particularly when the signals are all on the silicon so > you can't put a scope on them :( > Coreboot's scheme is fairly straightforward. To my understanding, it sets up the IOAPICs as virtual-wire, compliant with the Intel MP spec (which I read last night :P ). To software, this looks (should look) just like PIC mode. Alex > >Sean > > > -Original Message- > From: coreboot-bounces+svotier=drs-ds@coreboot.org > [mailto:coreboot-bounces+svotier=drs-ds@coreboot.org] On Behalf Of > Alex G. > Sent: Tuesday, February 08, 2011 4:15 PM > To: coreboot@coreboot.org > Subject: Re: [coreboot] Help with RX serial interrupts? > > Are you sure it's not just a bad PIC/APIC config? > > Alex > > On 02/08/2011 10:15 PM, Votier, Sean (DS-1) wrote: >> Designation: Non-SSA/Finmeccanica >> >> Hi all. >> >> I would like to apologise for being a lurker on this list and only >> popping up when I need help. But I need help... >> >> I've run into an issue that has been stumping my for the last couple >> of weeks. >> >> I'm developing bios code for a GE CR-11 Compact PCI board. >> >> The chips I'm working with are: >> >> 1.06 Mhz Pentium M >> >> E7520 Northbridge >> >> 6300ESB Southbridge >> >> I'm initialising the SIU in the Southbridge. I have the port > configured. >> I can see data transmitted and received from and to the serial port >> using a scope on the serial cable and also on my emulator but I can't >> seem to get the receive side to generate an interrupt. Does anyone >> have experience with serial interrupts on this hardware? Can you run >> through the steps involved for a very simple rx interrupt config just >> in case I missed something in the Intel docs. Know of an pitfalls? > > -- > coreboot mailing list: coreboot@coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > > 3.1.1001 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [PATCH] Fix some errata for AMD Family F processors
On 02/08/2011 11:37 PM, Alex G. wrote:
> See patch for detailed description.
>
> Alex
I should really attach the patch first before writing anything. Sorry
about that. Here's the patch.
Alex
Implemented workaround fot erratum 169, obsoleting errattum 131.
Workaround for 131 removed.
Changed erratum 89 workaround to include revision F processors.
Changed workaround for erratum 110 to only include pre-revision_f
processors.
For details, check AMD publications:
#25759 (Errata for Fam F pre-revision F processors)
#33610 (Errata for Fam F revision F and later processor)
Based on work and previous patches by:
Rudolf Marek
Josef Kellermann
Signed-off-by: Alexandru Gagniuc
Index: src/cpu/amd/model_fxx/model_fxx_init.c
===
--- src/cpu/amd/model_fxx/model_fxx_init.c (revision 6336)
+++ src/cpu/amd/model_fxx/model_fxx_init.c (working copy)
@@ -384,24 +384,7 @@
wrmsr_amd(DC_CFG_MSR, msr);
}
- /* I can't touch this msr on early buggy cpus */
- if (!is_cpu_pre_b3()) {
- /* Erratum 89 ... */
- msr = rdmsr(NB_CFG_MSR);
- msr.lo |= 1 << 3;
-
- if (!is_cpu_pre_c0() && is_cpu_pre_d0()) {
- /* D0 later don't need it */
- /* Erratum 86 Disable data masking on C0 and
- * later processor revs.
- * FIXME this is only needed if ECC is enabled.
- */
- msr.hi |= 1 << (36 - 32);
- }
- wrmsr(NB_CFG_MSR, msr);
- }
-
/* Erratum 97 ... */
if (!is_cpu_pre_c0() && is_cpu_pre_d0()) {
msr = rdmsr_amd(DC_CFG_MSR);
@@ -428,35 +411,64 @@
msr.hi |= 1 << (43 - 32);
wrmsr_amd(BU_CFG_MSR, msr);
+ /* Erratum 110 */
+ /* This erratum applies to D0 thru E6 revisions
+ * Revision F and later are unaffected. There are two fixes
+ * depending on processor revision.
+ */
if (is_cpu_d0()) {
/* Erratum 110 ... */
msr = rdmsr_amd(CPU_ID_HYPER_EXT_FEATURES);
msr.hi |= 1;
wrmsr_amd(CPU_ID_HYPER_EXT_FEATURES, msr);
}
-#endif
-#if CONFIG_K8_REV_F_SUPPORT == 0
if (!is_cpu_pre_e0())
-#endif
{
/* Erratum 110 ... */
msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
msr.hi |= 1;
wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
}
+#endif
+
+#if CONFIG_K8_REV_F_SUPPORT == 0
+ /* I can't touch this msr on early buggy cpus */
+ if (!is_cpu_pre_b3())
+#endif
+ {
+ msr = rdmsr(NB_CFG_MSR);
+
+#if CONFIG_K8_REV_F_SUPPORT == 0
+ if (!is_cpu_pre_c0() && is_cpu_pre_d0()) {
+ /* D0 later don't need it */
+ /* Erratum 86 Disable data masking on C0 and
+ * later processor revs.
+ * FIXME this is only needed if ECC is enabled.
+ */
+ msr.hi |= 1 << (36 - 32);
+ }
+#endif
+ /* Erratum 89 ... */
+ /* Erratum 89 is mistakenly labeled as 88 in AMD pub #25759
+ * It is correctly labeled as 89 on page 49 of the document
+ * and in AMD pub#33610
+ */
+ msr.lo |= 1 << 3;
+ /* Erratum 169 */
+ /* This supersedes erratum 131; 131 should not be applied with 169
+ * We also need to set some bits in the northbridge, handled in src/northbridge/amdk8/
+ */
+ msr.hi |= 1;
+
+ wrmsr(NB_CFG_MSR, msr);
+ }
/* Erratum 122 */
msr = rdmsr(HWCR_MSR);
msr.lo |= 1 << 6;
wrmsr(HWCR_MSR, msr);
-#if CONFIG_K8_REV_F_SUPPORT == 1
- /* Erratum 131... */
- msr = rdmsr(NB_CFG_MSR);
- msr.lo |= 1 << 20;
- wrmsr(NB_CFG_MSR, msr);
-#endif
}
Index: src/northbridge/amd/amdk8/coherent_ht.c
===
--- src/northbridge/amd/amdk8/coherent_ht.c (revision 6336)
+++ src/northbridge/amd/amdk8/coherent_ht.c (working copy)
@@ -1662,10 +1662,10 @@
unsigned node;
int needs_reset = 0;
for(node = 0; node < nodes; node++) {
-#if CONFIG_K8_REV_F_SUPPORT == 0
device_t dev;
uint32_t cmd;
dev = NODE_MC(node);
+#if CONFIG_K8_REV_F_SUPPORT == 0
if (is_cpu_pre_c0()) {
/* Errata 66
@@ -1708,6 +1708,20 @@
}
}
#endif
+
+
+#if CONFIG_K8_REV_F_SUPPORT == 0
+ /* I can't touch this msr on early buggy cpus, and cannot apply either 169 or 131 */
+ if (!is_cpu_pre_b3())
+#endif
+ {
+ /* Errata 169 */
+ /* We also need to set some bits in NB_CFG_MSR, which is handled in src/cpu/amd/model_fxx/ */
+ cmd = pci_read_config32(dev, 0x68);
+ cmd &= ~(1 << 22);
+ cmd |= (1 << 21);
+ pci_write_config32(dev, 0x68, cmd);
+ }
}
return needs_reset;
}
--
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[coreboot] [PATCH] Fix some errata for AMD Family F processors
See patch for detailed description. Alex -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Help with RX serial interrupts?
Are you sure it's not just a bad PIC/APIC config? Alex On 02/08/2011 10:15 PM, Votier, Sean (DS-1) wrote: > Designation: Non-SSA/Finmeccanica > > Hi all. > > I would like to apologise for being a lurker on this list and only > popping up when I need help. But I need help……….. > > I’ve run into an issue that has been stumping my for the last couple of > weeks. > > I’m developing bios code for a GE CR-11 Compact PCI board. > > The chips I’m working with are: > > 1.06 Mhz Pentium M > > E7520 Northbridge > > 6300ESB Southbridge > > I’m initialising the SIU in the Southbridge. I have the port configured. > I can see data transmitted and received from and to the serial port > using a scope on the serial cable and also on my emulator but I can’t > seem to get the receive side to generate an interrupt. Does anyone have > experience with serial interrupts on this hardware? Can you run through > the steps involved for a very simple rx interrupt config just in case I > missed something in the Intel docs. Know of an pitfalls? -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Help with RX serial interrupts?
Designation: Non-SSA/Finmeccanica Hi all. I would like to apologise for being a lurker on this list and only popping up when I need help. But I need help... I've run into an issue that has been stumping my for the last couple of weeks. I'm developing bios code for a GE CR-11 Compact PCI board. The chips I'm working with are: 1.06 Mhz Pentium M E7520 Northbridge 6300ESB Southbridge I'm initialising the SIU in the Southbridge. I have the port configured. I can see data transmitted and received from and to the serial port using a scope on the serial cable and also on my emulator but I can't seem to get the receive side to generate an interrupt. Does anyone have experience with serial interrupts on this hardware? Can you run through the steps involved for a very simple rx interrupt config just in case I missed something in the Intel docs. Know of an pitfalls? Thanks in advance for the help. Sean 3.1.1001 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [patch] nvramtool hardware access on NetBSD
r6338. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r6338 - in trunk/util/nvramtool: . accessors
Author: jakllsch
Date: Tue Feb 8 17:07:49 2011
New Revision: 6338
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6338
Log:
Add NetBSD support to nvramtool.
Signed-off-by:
Acked-by: Patrick Georgi
Acked-by: Peter Stuge
Modified:
trunk/util/nvramtool/Makefile
trunk/util/nvramtool/accessors/cmos-hw-unix.c
Modified: trunk/util/nvramtool/Makefile
==
--- trunk/util/nvramtool/Makefile Tue Feb 8 09:37:47 2011(r6337)
+++ trunk/util/nvramtool/Makefile Tue Feb 8 17:07:49 2011(r6338)
@@ -39,6 +39,9 @@
ifeq ($(OS_ARCH), Darwin)
LDFLAGS = -framework DirectIO
endif
+ifeq ($(OS_ARCH), NetBSD)
+LDFLAGS = -l$(shell uname -p)
+endif
all: dep $(PROGRAM)
Modified: trunk/util/nvramtool/accessors/cmos-hw-unix.c
==
--- trunk/util/nvramtool/accessors/cmos-hw-unix.c Tue Feb 8 09:37:47
2011(r6337)
+++ trunk/util/nvramtool/accessors/cmos-hw-unix.c Tue Feb 8 17:07:49
2011(r6338)
@@ -17,6 +17,53 @@
#if (defined(__MACH__) && defined(__APPLE__))
#include
#endif
+#if defined(__NetBSD__)
+#if defined(__i386__) || defined(__x86_64__)
+#include
+
+static inline void outb(uint8_t value, uint16_t port)
+{
+ asm volatile ("outb %b0,%w1": :"a" (value), "Nd" (port));
+}
+
+static inline uint8_t inb(uint16_t port)
+{
+ uint8_t value;
+ asm volatile ("inb %w1,%0":"=a" (value):"Nd" (port));
+ return value;
+}
+
+static inline void outw(uint16_t value, uint16_t port)
+{
+ asm volatile ("outw %w0,%w1": :"a" (value), "Nd" (port));
+}
+
+static inline uint16_t inw(uint16_t port)
+{
+ uint16_t value;
+ asm volatile ("inw %w1,%0":"=a" (value):"Nd" (port));
+ return value;
+}
+
+static inline void outl(uint32_t value, uint16_t port)
+{
+ asm volatile ("outl %0,%w1": :"a" (value), "Nd" (port));
+}
+
+static inline uint32_t inl(uint16_t port)
+{
+ uint32_t value;
+ asm volatile ("inl %1,%0":"=a" (value):"Nd" (port));
+ return value;
+}
+#endif
+#ifdef __x86_64__
+#define iopl x86_64_iopl
+#endif
+#ifdef __i386__
+#define iopl i386_iopl
+#endif
+#endif
#define OUTB outb
#define OUTW outw
#define OUTL outl
--
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Re: [coreboot] [patch] nvramtool hardware access on NetBSD
Jonathan A. Kollasch wrote: > Add NetBSD support to nvramtool. > > Signed-off-by: Acked-by: Peter Stuge -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [patch] nvramtool hardware access on NetBSD
Am Montag, den 07.02.2011, 21:15 + schrieb Jonathan A. Kollasch: > Add NetBSD support to nvramtool. > > Signed-off-by: Acked-by: Patrick Georgi More general question (shouldn't stop anyone from committing this patch): Should we move hardware access code to directio and use its API on all platforms (not just Darwin, and - in theory - win32)? Though in that case, we might want to import directio to the coreboot tree. Patrick -- Patrick Georgi SINA-Development - High Security secunet Security Networks AG - Mergenthalerallee 77 - 65760 Eschborn, Germany Phone +49 201 54 54-3610 - Fax +49 201 54 54-1325 - www.secunet.com Sitz: Kronprinzenstraße 30, 45128 Essen / Amtsgericht Essen HRB 13615 Vorstand: Dr. Rainer Baumgart (Vors.), Thomas Koelzer, Thomas Pleines Aufsichtsratsvorsitzender: Dr. Karsten Ottenberg signature.asc Description: This is a digitally signed message part -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] cmos recovery feature
Am Donnerstag, den 03.02.2011, 16:09 +0100 schrieb Josef Kellermann: > I've added this to my mainboards Makefile.inc: > > cbfs-files-y += cmos.default > cmos.default-name = cmos.default > cmos.default-type = 0xaa > > cmos.default also exists in mainboard dir. > > I've also tried with: > cmos.default-file = cmos.default > > Any idea ? Fixed in r6337. Thanks, Patrick -- Patrick Georgi SINA-Development - High Security secunet Security Networks AG - Mergenthalerallee 77 - 65760 Eschborn, Germany Phone +49 201 54 54-3610 - Fax +49 201 54 54-1325 - www.secunet.com Sitz: Kronprinzenstraße 30, 45128 Essen / Amtsgericht Essen HRB 13615 Vorstand: Dr. Rainer Baumgart (Vors.), Thomas Koelzer, Thomas Pleines Aufsichtsratsvorsitzender: Dr. Karsten Ottenberg signature.asc Description: This is a digitally signed message part -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r6337 - trunk
Author: oxygene Date: Tue Feb 8 09:37:47 2011 New Revision: 6337 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6337 Log: Fix cmos-files-y for relative paths Thanks to Josef Kellermann for reporting the issue. Signed-off-by: Patrick Georgi Acked-by: Patrick Georgi Modified: trunk/Makefile Modified: trunk/Makefile == --- trunk/Makefile Tue Feb 8 03:36:39 2011(r6336) +++ trunk/Makefile Tue Feb 8 09:37:47 2011(r6337) @@ -208,10 +208,10 @@ $$(subst $(top)/,, \ $$(abspath $$(addprefix $(dir $(1)),$$($(type)-y)) \ $(foreach file,$(cbfs-files-y), \ - $(if $(wildcard $(dir $(1))$$($(file)-file)), \ - $(eval tmp-cbfs-file:= $(wildcard $(dir $(1))$$($(file)-file))), \ - $(eval tmp-cbfs-file:= $$($(file)-file))) \ - $(eval cbfs-files += $(tmp-cbfs-file)|$(file)|$$($(file)-type)|$$($(file)-position)) \ + $(if $(wildcard $(dir $(1))$($(file)-file)), \ + $(eval tmp-cbfs-file:= $(wildcard $(dir $(1))$($(file)-file))), \ + $(eval tmp-cbfs-file:= $($(file)-file))) \ + $(eval cbfs-files += $(tmp-cbfs-file)|$(file)|$($(file)-type)|$($(file)-position)) \ $(eval $(file)-name:=) \ $(eval $(file)-type:=) \ $(eval $(file)-position:=)) \ -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
