[coreboot] Dual SPI Flash
Hi list, I noticed an intersting hack on the coreboot wiki: http://www.coreboot.org/Developer_Manual/Tools/Dual_Flash It lists a neat trick to double stack two spi flash modules to make testing/developping/flashing coreboot easier. However there's no schematic or other information available on how to actually build this setup. Could the author possibly supply this extra information? Since not even the resitor values or switch connection is documented. Thanks, Oliver -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Patch set updated for coreboot: 3dea10d Auto-generate bootblock initialisation
Kyösti Mälkki (kyosti.mal...@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/473 -gerrit commit 3dea10d666a76c3f81dca0ba5381709d0f277044 Author: Kyösti Mälkki kyosti.mal...@gmail.com Date: Sun Dec 4 21:35:38 2011 +0200 Auto-generate bootblock initialisation The following chip-specific functions were renamed to include chip name in the function: - bootblock_northbridge_init - bootblock_southbridge_init The following no-operation bootblock.c files were removed: - northbridge/amd/agesa/family10/bootblock.c - northbridge/amd/agesa/family12/bootblock.c - northbridge/amd/agesa/family14/bootblock.c A new init function called from bootblock is declared as: - unsigned long init_mainboard(int bsp_cpu) For BSP CPU bootblock calls init_mainboard(true). For AP CPUs bootblock calls init_mainboard(false). Usually AP CPU has nothing to do here. By default, build toolchain creates and includes an init_mainboard() function in file build/mainboard/x/x/bootblock_autogen.h that executes init functions from any bootblock.c files for all chips listed in mainboard/devtree.cb. Alternatively a mainboard/x/x/bootblock.c file is added in the bootblock build, if a Kconfig option HAS_MAINBOARD_BOOTBLOCK is set. One should copy the auto-generated init_mainboard() to this file, and optionally read various bootstrap signals or status bits from super-io and southbridge component to gain some control over the selection of romstage to boot via the return value. Samples of such (yet not implemented) controls for boot behaviour: - Reset CMOS to defaults on user request (jumper). - Use fallback prefix after power-button 4s override. - Refuse boot after intruder detection. - On remote wakeup, request network boot. Change-Id: Ib1d101cdd68993530c9c7a653ac000a01de52ac2 Signed-off-by: Kyösti Mälkki kyosti.mal...@gmail.com --- src/arch/x86/Kconfig |7 + src/arch/x86/Makefile.inc |9 +- src/arch/x86/include/bootblock_common.h| 17 +- src/arch/x86/init/bootblock_normal.c |8 +++--- src/arch/x86/init/bootblock_simple.c | 10 src/mainboard/hp/dl165_g6_fam10/Kconfig|5 +--- src/mainboard/hp/dl165_g6_fam10/bootblock.c| 10 +++- src/northbridge/amd/agesa/family10/Kconfig |3 -- src/northbridge/amd/agesa/family10/bootblock.c | 29 src/northbridge/amd/agesa/family12/Kconfig |4 --- src/northbridge/amd/agesa/family12/bootblock.c | 29 src/northbridge/amd/agesa/family14/Kconfig |4 --- src/northbridge/amd/agesa/family14/bootblock.c | 29 src/northbridge/amd/amdfam10/Kconfig |4 --- src/northbridge/amd/amdfam10/bootblock.c |2 +- src/northbridge/amd/amdk8/Kconfig |4 --- src/northbridge/amd/amdk8/bootblock.c |2 +- src/southbridge/amd/amd8111/Kconfig|4 --- src/southbridge/amd/amd8111/bootblock.c|2 +- src/southbridge/amd/cimx/sb800/Kconfig |3 -- src/southbridge/amd/cimx/sb800/bootblock.c |2 +- src/southbridge/amd/cimx/sb900/Kconfig |3 -- src/southbridge/amd/cimx/sb900/bootblock.c |2 +- src/southbridge/amd/sb600/Kconfig |3 -- src/southbridge/amd/sb600/bootblock.c |2 +- src/southbridge/amd/sb700/Kconfig |5 src/southbridge/amd/sb700/bootblock.c |2 +- src/southbridge/amd/sb800/Kconfig |5 src/southbridge/amd/sb800/bootblock.c |2 +- src/southbridge/broadcom/bcm5785/Kconfig |4 --- src/southbridge/broadcom/bcm5785/bootblock.c |2 +- src/southbridge/intel/i82371eb/Kconfig |5 src/southbridge/intel/i82371eb/bootblock.c |2 +- src/southbridge/intel/i82801gx/Kconfig |5 src/southbridge/intel/i82801gx/bootblock.c |2 +- src/southbridge/nvidia/ck804/Kconfig |6 ++-- src/southbridge/nvidia/ck804/bootblock.c |2 +- src/southbridge/nvidia/mcp55/Kconfig |6 ++-- src/southbridge/nvidia/mcp55/bootblock.c |2 +- src/southbridge/sis/sis966/Kconfig |7 +++-- src/southbridge/sis/sis966/bootblock.c |2 +- src/southbridge/via/vt8237r/Kconfig|4 --- src/southbridge/via/vt8237r/bootblock.c|2 +- 43 files changed, 54 insertions(+), 208 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index e71d0f3..07ad95f 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -67,8 +67,8 @@ config PC80_SYSTEM bool default y -config BOOTBLOCK_NORTHBRIDGE_INIT - string +config
Re: [coreboot] Asus M2V-MX memory init
Hi guys, Does this have something to do with remapping the RAM shadowed by PCI devices to above 4GB? Anyway, I haven't know yet whether Coreboot remaps RAM shadowed by PCI devices. Regards, Darmawan On 2/22/12, Peter Stuge pe...@stuge.se wrote: David Hillman wrote: It looks like I am missing something to properly initialize memory to get correct SPD info. Maybe SMBUS isn't working properly? I think SMBUS is OK and memory init too. Here's the diff between your two logs with some comments, but there may be more relevant stuff than what I see. Next time when posting logs please make sure that they do not wrap. One good way is to send them as attachments, under all circumstances with text/plain mime type. --- m2v_mx-2g 2012-02-22 04:13:21.309138502 +0100 +++ m2v_mx-4g 2012-02-22 04:13:02.663139149 +0100 @@ -1,4 +1,4 @@ -coreboot-4.0-2000-g91be49b-dirty Mon Feb 20 22:44:53 EST 2012 starting... +coreboot-4.0-2000-g91be49b-dirty Wed Feb 15 22:11:37 EST 2012 starting... now booting... Enabling routing table for node 00 done. Enabling UP settings @@ -47,16 +47,21 @@ sdram_set_spd_registers: paramx :000ceee8 Device error Device error -Device error +Enabling dual channel memory Unbuffered 400MHz 400MHz Interleaved -RAM end at 0x0020 kB +RAM end at 0x0040 kB Ram3 IN TEST WAKEUP 800Initializing memory: done Setting variable MTRR 2, base:0MB, range: 2048MB, type WB +Setting variable MTRR 3, base: 2048MB, range: 1024MB, type WB +Setting variable MTRR 4, base: 3072MB, range: 512MB, type WB +Setting variable MTRR 5, base: 3584MB, range: 256MB, type WB +Setting variable MTRR 6, base: 3840MB, range: 128MB, type WB +Setting variable MTRR 7, base: 3968MB, range: 64MB, type WB DQS Training:RcvrEn:Pass1: 00 CTLRMaxDelay=1d done @@ -68,41 +73,45 @@ TrainDQSPos: MutualCSPassW[48] :000ce828 TrainDQSPos: MutualCSPassW[48] :000ce828 TrainDQSPos: MutualCSPassW[48] :000ce828 +TrainDQSPos: MutualCSPassW[48] :000ce828 +TrainDQSPos: MutualCSPassW[48] :000ce828 +TrainDQSPos: MutualCSPassW[48] :000ce828 +TrainDQSPos: MutualCSPassW[48] :000ce828 done DQS Training:RcvrEn:Pass2: 00 - CTLRMaxDelay=43 + CTLRMaxDelay=34 done DQS SAVE NVRAM: c2000 Writing 113222 of size 4 to nvram pos: 0 -Writing 17161515 of size 4 to nvram pos: 4 +Writing 17151515 of size 4 to nvram pos: 4 Writing 17171615 of size 4 to nvram pos: 8 Writing 15 of size 1 to nvram pos: 12 Writing 202520 of size 4 to nvram pos: 13 -Writing 17171918 of size 4 to nvram pos: 17 -Writing 17191718 of size 4 to nvram pos: 21 +Writing 18171819 of size 4 to nvram pos: 17 +Writing 18181718 of size 4 to nvram pos: 21 Writing 17 of size 1 to nvram pos: 25 -Writing 33 of size 1 to nvram pos: 26 +Writing 32 of size 1 to nvram pos: 26 Writing 0 of size 1 to nvram pos: 27 Writing 0 of size 1 to nvram pos: 28 Writing 0 of size 1 to nvram pos: 29 -Writing 111222 of size 4 to nvram pos: 30 -Writing 0 of size 4 to nvram pos: 34 -Writing 0 of size 4 to nvram pos: 38 -Writing 0 of size 1 to nvram pos: 42 -Writing 0 of size 4 to nvram pos: 43 -Writing 2f2f2f2f of size 4 to nvram pos: 47 -Writing 2f2f2f2f of size 4 to nvram pos: 51 -Writing 0 of size 1 to nvram pos: 55 -Writing 43 of size 1 to nvram pos: 56 +Writing 113222 of size 4 to nvram pos: 30 +Writing 15141615 of size 4 to nvram pos: 34 +Writing 15141515 of size 4 to nvram pos: 38 +Writing 15 of size 1 to nvram pos: 42 +Writing 202520 of size 4 to nvram pos: 43 +Writing 17191818 of size 4 to nvram pos: 47 +Writing 18191716 of size 4 to nvram pos: 51 +Writing 16 of size 1 to nvram pos: 55 +Writing 34 of size 1 to nvram pos: 56 Writing 0 of size 1 to nvram pos: 57 Writing 0 of size 1 to nvram pos: 58 Writing 0 of size 1 to nvram pos: 59 -Writing 741080ab of size 4 to nvram pos: 60 -DQS Training:tsc[00]=5eac6acb -DQS Training:tsc[01]=6087914d -DQS Training:tsc[02]=60879156 -DQS Training:tsc[03]=df309c2e -DQS Training:tsc[04]=f2a194b3 +Writing 7410809b of size 4 to nvram pos: 60 +DQS Training:tsc[00]=8cbdd63c +DQS Training:tsc[01]=8f476e2e +DQS Training:tsc[02]=8f476e37 +DQS Training:tsc[03]=00015b152149 +DQS Training:tsc[04]=00016daed79e Ram4 v_esp=000cef28 testx = 5a5a5a5a @@ -121,7 +130,7 @@ 0x10 Stage: done loading. Jumping to image. -coreboot-4.0-2000-g91be49b-dirty Mon Feb 20 22:44:53 EST 2012 booting... +coreboot-4.0-2000-g91be49b-dirty Wed Feb 15 22:11:37 EST 2012 booting... Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 @@ -147,7 +156,7 @@ PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 -PCI: 00:12.0: enabled 0 +PCI: 00:12.0: enabled 1 Why is 12.0 enabled with 4G? What is 12.0? PCI: 00:13.0: enabled 1 PCI: 00:13.1: enabled 1 PCI: 00:18.1: enabled 1 @@ -177,7 +186,7 @@ PNP: 002e.8: enabled 0
[coreboot] Patch set updated for coreboot: 0e08243 Auto-generate bootblock initialisation
Kyösti Mälkki (kyosti.mal...@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/473 -gerrit commit 0e0824334189ff17f31d211c5488b86206c61035 Author: Kyösti Mälkki kyosti.mal...@gmail.com Date: Thu Feb 23 14:17:53 2012 +0200 Auto-generate bootblock initialisation The following chip-specific functions were renamed to include chip name in the function: - bootblock_northbridge_init - bootblock_southbridge_init The following no-operation bootblock.c files were removed: - northbridge/amd/agesa/family10/bootblock.c - northbridge/amd/agesa/family12/bootblock.c - northbridge/amd/agesa/family14/bootblock.c - northbridge/amd/agesa/family15/bootblock.c A new init function called from bootblock is declared as: - unsigned long init_mainboard(int bsp_cpu) For BSP CPU bootblock calls init_mainboard(true). For AP CPUs bootblock calls init_mainboard(false). Usually AP CPU has nothing to do here. By default, build toolchain creates and includes an init_mainboard() function in file build/mainboard/x/x/bootblock_autogen.h that executes init functions from any bootblock.c files for all chips listed in mainboard/devtree.cb. Alternatively a mainboard/x/x/bootblock.c file is added in the bootblock build, if a Kconfig option HAS_MAINBOARD_BOOTBLOCK is set. One should copy the auto-generated init_mainboard() to this file, and optionally read various bootstrap signals or status bits from super-io and southbridge component to gain some control over the selection of romstage to boot via the return value. Samples of such (yet not implemented) controls for boot behaviour: - Reset CMOS to defaults on user request (jumper). - Use fallback prefix after power-button 4s override. - Refuse boot after intruder detection. - On remote wakeup, request network boot. Change-Id: Ib1d101cdd68993530c9c7a653ac000a01de52ac2 Signed-off-by: Kyösti Mälkki kyosti.mal...@gmail.com --- src/arch/x86/Kconfig |7 + src/arch/x86/Makefile.inc |9 +- src/arch/x86/include/bootblock_common.h| 17 +- src/arch/x86/init/bootblock_normal.c |8 +++--- src/arch/x86/init/bootblock_simple.c | 10 src/mainboard/hp/dl165_g6_fam10/Kconfig|5 +--- src/mainboard/hp/dl165_g6_fam10/bootblock.c| 10 +++- src/northbridge/amd/agesa/family10/Kconfig |3 -- src/northbridge/amd/agesa/family10/bootblock.c | 29 src/northbridge/amd/agesa/family12/Kconfig |4 --- src/northbridge/amd/agesa/family12/bootblock.c | 29 src/northbridge/amd/agesa/family14/Kconfig |4 --- src/northbridge/amd/agesa/family14/bootblock.c | 29 src/northbridge/amd/agesa/family15/Kconfig |3 -- src/northbridge/amd/agesa/family15/bootblock.c | 25 src/northbridge/amd/amdfam10/Kconfig |4 --- src/northbridge/amd/amdfam10/bootblock.c |2 +- src/northbridge/amd/amdk8/Kconfig |4 --- src/northbridge/amd/amdk8/bootblock.c |2 +- src/southbridge/amd/amd8111/Kconfig|4 --- src/southbridge/amd/amd8111/bootblock.c|2 +- src/southbridge/amd/cimx/sb700/Kconfig |3 -- src/southbridge/amd/cimx/sb700/bootblock.c |2 +- src/southbridge/amd/cimx/sb800/Kconfig |3 -- src/southbridge/amd/cimx/sb800/bootblock.c |2 +- src/southbridge/amd/cimx/sb900/Kconfig |3 -- src/southbridge/amd/cimx/sb900/bootblock.c |2 +- src/southbridge/amd/sb600/Kconfig |3 -- src/southbridge/amd/sb600/bootblock.c |2 +- src/southbridge/amd/sb700/Kconfig |5 src/southbridge/amd/sb700/bootblock.c |2 +- src/southbridge/amd/sb800/Kconfig |5 src/southbridge/amd/sb800/bootblock.c |2 +- src/southbridge/broadcom/bcm5785/Kconfig |4 --- src/southbridge/broadcom/bcm5785/bootblock.c |2 +- src/southbridge/intel/i82371eb/Kconfig |5 src/southbridge/intel/i82371eb/bootblock.c |2 +- src/southbridge/intel/i82801gx/Kconfig |5 src/southbridge/intel/i82801gx/bootblock.c |2 +- src/southbridge/nvidia/ck804/Kconfig |6 ++-- src/southbridge/nvidia/ck804/bootblock.c |2 +- src/southbridge/nvidia/mcp55/Kconfig |6 ++-- src/southbridge/nvidia/mcp55/bootblock.c |2 +- src/southbridge/sis/sis966/Kconfig |7 +++-- src/southbridge/sis/sis966/bootblock.c |2 +- src/southbridge/via/vt8237r/Kconfig|4 --- src/southbridge/via/vt8237r/bootblock.c|2 +- 47 files changed, 55
[coreboot] New patch to review for coreboot: aafcf93 Ati video: Apply un-written naming rules
Kyösti Mälkki (kyosti.mal...@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/678 -gerrit commit aafcf93e1a8d5b51ccdf4e7f4bd62de5a5c81f15 Author: Kyösti Mälkki kyosti.mal...@gmail.com Date: Thu Feb 23 13:54:23 2012 +0200 Ati video: Apply un-written naming rules Rename Kconfig to match directory name. Change-Id: Idebc203bbc9a02599dfc3e65be021aa9e1b23d61 Signed-off-by: Kyösti Mälkki kyosti.mal...@gmail.com --- src/drivers/ati/ragexl/Kconfig |2 +- src/drivers/ati/ragexl/Makefile.inc |2 +- src/mainboard/intel/jarrell/Kconfig |2 +- src/mainboard/iwill/dk8s2/Kconfig |2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/drivers/ati/ragexl/Kconfig b/src/drivers/ati/ragexl/Kconfig index 117aa66..86109b1 100644 --- a/src/drivers/ati/ragexl/Kconfig +++ b/src/drivers/ati/ragexl/Kconfig @@ -1,2 +1,2 @@ -config ATI_RAGE_XL +config DRIVERS_ATI_RAGEXL bool diff --git a/src/drivers/ati/ragexl/Makefile.inc b/src/drivers/ati/ragexl/Makefile.inc index 107885e..8b59597 100644 --- a/src/drivers/ati/ragexl/Makefile.inc +++ b/src/drivers/ati/ragexl/Makefile.inc @@ -1 +1 @@ -driver-$(CONFIG_ATI_RAGE_XL) += xlinit.c +driver-$(CONFIG_DRIVERS_ATI_RAGEXL) += xlinit.c diff --git a/src/mainboard/intel/jarrell/Kconfig b/src/mainboard/intel/jarrell/Kconfig index 282ec4b..a3c34f4 100644 --- a/src/mainboard/intel/jarrell/Kconfig +++ b/src/mainboard/intel/jarrell/Kconfig @@ -15,7 +15,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select UDELAY_TSC select USE_WATCHDOG_ON_BOOT - select ATI_RAGE_XL + select DRIVERS_ATI_RAGEXL select BOARD_ROMSIZE_KB_2048 config MAINBOARD_DIR diff --git a/src/mainboard/iwill/dk8s2/Kconfig b/src/mainboard/iwill/dk8s2/Kconfig index f9f1b57..1c35cb2 100644 --- a/src/mainboard/iwill/dk8s2/Kconfig +++ b/src/mainboard/iwill/dk8s2/Kconfig @@ -14,7 +14,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select SB_HT_CHAIN_UNITID_OFFSET_ONLY select WAIT_BEFORE_CPUS_INIT - select ATI_RAGE_XL + select DRIVERS_ATI_RAGEXL select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Dual SPI Flash
Oliver Schinagl wrote: I noticed an intersting hack on the coreboot wiki: http://www.coreboot.org/Developer_Manual/Tools/Dual_Flash It lists a neat trick to double stack two spi flash modules to make testing/developping/flashing coreboot easier. However there's no schematic or other information available on how to actually build this setup. Could the author possibly supply this extra information? Since not even the resitor values or switch connection is documented. I'm not the author but there is documentation at http://stuge.se/m57sli/ for what is called the simple modification. Resistor values are generally not critical and the switch connection should be obvious after study of the flash chip data sheet. //Peter -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
