[coreboot] Trouble with coreboot for Roda RK9 15 and 17
Hello Nico, Could you please help me to solve some problems? Laptop: Roda RK9 15 and 17 With model 13 the coreboot works well, but as for 15 and 17 models we faced with the following problems: 15 - I add vga bios from native BIOS Phoenix and when it is loading the screen is brightened but the text may be distinguised. 17 - I do the same actions, but when it is loading the screen is white and then fades. As for the 13 model there are no problems, everything works well with VGA Bios. Thank you Best regards, Dmitry Bagryanskiy.-- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Motherboard Not on Support MB List - Specs
Hi, I have some info about my motherboard here according to the FAQ page to see if anyone can tell me about the compatibility between my BIOS and coreboot. 1. Gigabyte GA-Z77-HD3 Motherboard Intel(R) Core(TM) i5-3570K CPU @ 3.40GHz 2. lspci -tvnn -[:00]-+-00.0 Intel Corporation Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller [8086:0150] +-01.0-[01]--+-00.0 Advanced Micro Devices, Inc. [AMD/ATI] Caicos [Radeon HD 6450/7450/8450] [1002:6779] |\-00.1 Advanced Micro Devices, Inc. [AMD/ATI] Caicos HDMI Audio [Radeon HD 6400 Series] [1002:aa98] +-14.0 Intel Corporation 7 Series/C210 Series Chipset Family USB xHCI Host Controller [8086:1e31] +-16.0 Intel Corporation 7 Series/C210 Series Chipset Family MEI Controller #1 [8086:1e3a] +-1a.0 Intel Corporation 7 Series/C210 Series Chipset Family USB Enhanced Host Controller #2 [8086:1e2d] +-1b.0 Intel Corporation 7 Series/C210 Series Chipset Family High Definition Audio Controller [8086:1e20] +-1c.0-[02]-- +-1c.2-[03]00.0 Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller [10ec:8168] +-1c.3-[04-05]00.0-[05]-- +-1d.0 Intel Corporation 7 Series/C210 Series Chipset Family USB Enhanced Host Controller #1 [8086:1e26] +-1f.0 Intel Corporation Z77 Express Chipset LPC Controller [8086:1e44] +-1f.2 Intel Corporation 7 Series/C210 Series Chipset Family 4-port SATA Controller [IDE mode] [8086:1e00] +-1f.3 Intel Corporation 7 Series/C210 Series Chipset Family SMBus Controller [8086:1e22] \-1f.5 Intel Corporation 7 Series/C210 Series Chipset Family 2-port SATA Controller [IDE mode] [8086:1e08] 3. superiotool -dV superiotool r6637 Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0x, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0x, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0x, id=0x Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0x, id=0x Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0x, id=0x Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0x, id=0x Probing for ITE Super I/O (init=standard) at 0x25e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x25e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x25e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x25e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x25e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=standard) at 0x2e... Failed. Returned data: id=0x8728, rev=0x1 Probing for ITE Super I/O (init=it8502e) at 0x2e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x2e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x2e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=standard) at 0x4e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x4e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x4e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x4e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... Failed. Returned data: id=0x, rev=0xf Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x164e... Failed. Returned data: port=0xff, port+1=0xff Probing for Nuvoton Super I/O at 0x164e... Failed. Returned data: chip_id=0x Probing for Nuvoton Super I/O (sid=0xfc) at 0x164e... Failed. Returned data: sid=0xff, id=0x, rev=0x00 Probing for Nuvoton Super I/O at 0x2e... Failed. Returned data: chip_id=0x Probing for Nuvoton Super I/O (sid=0xfc) at 0x2e... Failed. Returned data: sid=0xff, id=0x, rev=0x00 Probing for Nuvoton Super I/O at 0x4e... Failed. Returned data: chip_id=0x Probing for Nuvoton Super I/O (sid=0xfc) at 0x4e... Failed. Returned data: sid=0xff, id=0x, rev=0x00 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data:
Re: [coreboot] Plans to give the DSPIF away at FOSDEM WAS: Re: Dual SPI Flash adapter attempt 2.0
On 25.1.2014 12:01, Oliver Schinagl wrote: Nobody interested at all? Well not true :) I thought immediately oh nice I always wanted to design that. I was not in the FOSDEM this year, but if usual suspect have them, I will ask them if they could ship it to me! Anyway thanks for a great tool. Thanks Rudolf -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] coreboot port for macbook2,1
Hallo Vladimir, Peter and Stefan thank you for your emails! You already helped me alot. I don't expect to successfully close this project in a fast run and I'm willing to learn a number of tools. At the moment I am still collecting hardware informations about this computer. I dissembled it completely and documented the chip names of what I thought might be of interest. Please see http://macbook.donderklumpen.de/coreboot/ for what I got. My biggest concern is with the EC. It is a Renesas H8S/2116V. I read about this chip that it makes coreboot impossible on other machines, but I do not know whether this issue is machine specific, or if the chip definitely makes coreboot impossible for this macbook too. Could you comment on this? Also I do not know yet how I could verify whether the EC shares memory with the main system. As for the ability of flashing the EPROM chip, I plan to test it in the near future (at first with an empty brand new chip, then with the soldered one). The EPROM is supported by flashrom and I plan to use a Beaglebone Black to be the programmer. (this page shows Beaglebone Black can flash a chip via SPI also flashrom is not used here: http://www.linux.com/learn/tutorials/746860-how-to-access-chips-over-the-spi-on-beaglebone-black ) I already learned how to use the Beaglebone Black to debug what coreboot outputs to the USB port on a Thinkpad X60. I assume this should work the same for the macbook (the debug port at the macbook seems to exist, but the factory BIOS does not write anything to it). One more question: The macbook atm uses a 32bit EFI which when it was purchased booted a 32bit kernel, and today boots a 64bit linux-libre kernel. Would I need to expect any additional problems from the fact that it is not a traditional BIOS, but some EFI which is to be replaced? My optimistic wish is to replace that EFI with coreboot plus a 64bit GRUB2 payload (same as done on my Thinkpad X60). Or would the payload need to be kept at 32bit? thanks again and with best regards Mono On Wed, Jan 29, 2014 at 10:24:58PM +0100, Stefan Reinauer wrote: * Mono m...@posteo.de [140124 23:20]: Hallo, Would you help me on a coreboot port? I just installed coreboot on a Thinkpad X60 following the wiki. Now I want it on this mid-2007 macbook2,1 too. I read some pages in the wiki and started to collect information about the macbook. it seems it has no superIO chip and I dont know what to think of the ectool output. As I understood by now, not knowing how the ec might interfere with the bios or coreboot is one of the big obstacles, no? I hope that once I would try a coreboot flash, recovery might be possible by an external programmer (which I do not have, yet). the flash chip is the same as on the X60 (I've read the factory bios already) as is the northbridge and southbridge. an usb debug port seems available. I've put the log files here: http://macbook.donderklumpen.de/coreboot/ Any comment about what you think about this and how I should proceed is very much welcome! - Make sure you have the external tools in place to recover from a bad flash. You will not boot successfully on the first attempt. - Keep a copy of the original firmware around - Try to make sure that your USB debug gadget is working before starting - Start with one of the existing i945 based notebooks - find out what EC is used, and if it shares flash with the main system - try to get hold of schematics Regards, Stefan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] coreboot port for macbook2,1
On 03.02.2014 21:43, Mono wrote: Hallo Vladimir, Peter and Stefan thank you for your emails! You already helped me alot. I don't expect to successfully close this project in a fast run and I'm willing to learn a number of tools. At the moment I am still collecting hardware informations about this computer. I dissembled it completely and documented the chip names of what I thought might be of interest. Please see http://macbook.donderklumpen.de/coreboot/ for what I got. That is good example of relevant info collection. My biggest concern is with the EC. It is a Renesas H8S/2116V. I read about this chip that it makes coreboot impossible on other machines, but I do not know whether this issue is machine specific, or if the chip definitely makes coreboot impossible for this macbook too. Could you comment on this? Type of EC doesn't matter. What matters is how it is connected. It may really get in the way or have almost no impact. My guess would be that on your system its influence is minor. X60 has H8 as well but with very different firmware which makes it a completely different chip from coreboot perspective. Also I do not know yet how I could verify whether the EC shares memory with the main system. That flashrom didn't create any ill effects when reading is an indication of separate flash. If you can flash externally you can leave the issue of internal flash for later and if you don't, don't flash. As for the ability of flashing the EPROM chip, I plan to test it in the near future (at first with an empty brand new chip, then with the soldered one). The EPROM is supported by flashrom and I plan to use a Beaglebone Black to be the programmer. (this page shows Beaglebone Black can flash a chip via SPI also flashrom is not used here: http://www.linux.com/learn/tutorials/746860-how-to-access-chips-over-the-spi-on-beaglebone-black ) I already learned how to use the Beaglebone Black to debug what coreboot outputs to the USB port on a Thinkpad X60. I assume this should work the same for the macbook (the debug port at the macbook seems to exist, but the factory BIOS does not write anything to it). Good One more question: The macbook atm uses a 32bit EFI which when it was purchased booted a 32bit kernel, and today boots a 64bit linux-libre kernel. Would I need to expect any additional problems from the fact that it is not a traditional BIOS, but some EFI which is to be replaced? My optimistic wish is to replace that EFI with coreboot plus a 64bit GRUB2 payload (same as done on my Thinkpad X60). Or would the payload need to be kept at 32bit? What Apple ships as firmware is irrelevant. However, decision to omit BIOS comes from higher-level decision of omiting compatibility with 95-era systems. So it's possible you won't be able to boot old OS even with coreboot due to lack of compatibility devices. I'd say it's a minor problem (95-era OS wouldn't work reliably on modern system anyway) thanks again and with best regards Mono On Wed, Jan 29, 2014 at 10:24:58PM +0100, Stefan Reinauer wrote: * Mono m...@posteo.de [140124 23:20]: Hallo, Would you help me on a coreboot port? I just installed coreboot on a Thinkpad X60 following the wiki. Now I want it on this mid-2007 macbook2,1 too. I read some pages in the wiki and started to collect information about the macbook. it seems it has no superIO chip and I dont know what to think of the ectool output. As I understood by now, not knowing how the ec might interfere with the bios or coreboot is one of the big obstacles, no? I hope that once I would try a coreboot flash, recovery might be possible by an external programmer (which I do not have, yet). the flash chip is the same as on the X60 (I've read the factory bios already) as is the northbridge and southbridge. an usb debug port seems available. I've put the log files here: http://macbook.donderklumpen.de/coreboot/ Any comment about what you think about this and how I should proceed is very much welcome! - Make sure you have the external tools in place to recover from a bad flash. You will notg boot successfully on the first attempt. - Keep a copy of the original firmware around - Try to make sure that your USB debug gadget is working before starting - Start with one of the existing i945 based notebooks - find out what EC is used, and if it shares flash with the main system - try to get hold of schematics Regards, Stefan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot signature.asc Description: OpenPGP digital signature -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Motherboard Not on Support MB List - Specs
On 03.02.2014 17:37, lee.changhan wrote: Hi, I have some info about my motherboard here according to the FAQ page to see if anyone can tell me about the compatibility between my BIOS and coreboot. Your motherboard is not compatible with coreboot. 1. Gigabyte GA-Z77-HD3 Motherboard Intel(R) Core(TM) i5-3570K CPU @ 3.40GHz 2. lspci -tvnn -[:00]-+-00.0 Intel Corporation Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller [8086:0150] +-01.0-[01]--+-00.0 Advanced Micro Devices, Inc. [AMD/ATI] Caicos [Radeon HD 6450/7450/8450] [1002:6779] |\-00.1 Advanced Micro Devices, Inc. [AMD/ATI] Caicos HDMI Audio [Radeon HD 6400 Series] [1002:aa98] +-14.0 Intel Corporation 7 Series/C210 Series Chipset Family USB xHCI Host Controller [8086:1e31] +-16.0 Intel Corporation 7 Series/C210 Series Chipset Family MEI Controller #1 [8086:1e3a] +-1a.0 Intel Corporation 7 Series/C210 Series Chipset Family USB Enhanced Host Controller #2 [8086:1e2d] +-1b.0 Intel Corporation 7 Series/C210 Series Chipset Family High Definition Audio Controller [8086:1e20] +-1c.0-[02]-- +-1c.2-[03]00.0 Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller [10ec:8168] +-1c.3-[04-05]00.0-[05]-- +-1d.0 Intel Corporation 7 Series/C210 Series Chipset Family USB Enhanced Host Controller #1 [8086:1e26] +-1f.0 Intel Corporation Z77 Express Chipset LPC Controller [8086:1e44] +-1f.2 Intel Corporation 7 Series/C210 Series Chipset Family 4-port SATA Controller [IDE mode] [8086:1e00] +-1f.3 Intel Corporation 7 Series/C210 Series Chipset Family SMBus Controller [8086:1e22] \-1f.5 Intel Corporation 7 Series/C210 Series Chipset Family 2-port SATA Controller [IDE mode] [8086:1e08] 3. superiotool -dV superiotool r6637 Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0x, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0x, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0x, id=0x Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0x, id=0x Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0x, id=0x Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0x, id=0x Probing for ITE Super I/O (init=standard) at 0x25e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x25e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x25e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x25e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x25e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=standard) at 0x2e... Failed. Returned data: id=0x8728, rev=0x1 Probing for ITE Super I/O (init=it8502e) at 0x2e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x2e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x2e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=standard) at 0x4e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x4e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x4e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x4e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... Failed. Returned data: id=0x, rev=0xf Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x164e... Failed. Returned data: port=0xff, port+1=0xff Probing for Nuvoton Super I/O at 0x164e... Failed. Returned data: chip_id=0x Probing for Nuvoton Super I/O (sid=0xfc) at 0x164e... Failed. Returned data: sid=0xff, id=0x, rev=0x00 Probing for Nuvoton Super I/O at 0x2e... Failed. Returned data: chip_id=0x Probing for Nuvoton Super I/O (sid=0xfc) at 0x2e... Failed. Returned data: sid=0xff, id=0x, rev=0x00 Probing for Nuvoton Super I/O at 0x4e... Failed. Returned data:
[coreboot] Question about status of coreboot on the Samsung XE303CE ARM Chromebook (snow)
Hi everyone, Quick question: what is the status of coreboot + some payload being used with the Samsung XE303CE ARM Chromebook (snow)? The page at [http://www.coreboot.org/Chromebooks] says 'Snow has das U-Boot nativly installed, but a coreboot port is available.', and the page at [http://www.coreboot.org/Supported_Motherboards] has 'Google Snow - Samsung Exynos 5250' under the 'Motherboards supported in coreboot', but I haven't been able to find any blog / example of anyone actually flashing coreboot + some payload and booting their Chromebook like a regular computer. It seems like there is a port available but no one has tried it from start to finish on the ARM Chromebook (where my definition of finish in this context is 'booting with coreboot to stock Debian Linux', for example). I'm very keen on doing this myself, and was hoping to find some example that I could read through or even follow. This whole process of flashing a new BIOS is very new to me, and I'm wary because of the potential to easily brick my device (however I'm not scared off by reflashing or external chip programming if it comes to it, I'd just like to avoid it). Thanks for your time, James -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] coreboot port for macbook2,1
CY8C24794-24LFXI My guess: it's part of keyboard + touchpad Do you already know which port is USBdebug one? Did you already test USB debug with dbgp? Um, there are much more 00's than for the Thinkpad X60. Not sure what this means Different firmware. Most likely less functions are on it (keyboard and touchpad are on USB and handled by another chip). You'll need to make directory ec/apple/h8 for it and no code from lenovo/h8 will be reusable. What about those Block Protect things? Forget them for now, you'll be flashing externally until you have working version anyway signature.asc Description: OpenPGP digital signature -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Motherboard Not on Support MB List - Specs
Okay thanks. It also said on the FAQ it takes years to port to the motherboard. How long does it take programmers with low level C experience to port to a specific motherboard design? Also, is there a priority list of motherboards that coreboot is being port to? On Mon, Feb 3, 2014 at 4:02 PM, Vladimir 'φ-coder/phcoder' Serbinenko phco...@gmail.com wrote: On 03.02.2014 17:37, lee.changhan wrote: Hi, I have some info about my motherboard here according to the FAQ page to see if anyone can tell me about the compatibility between my BIOS and coreboot. Your motherboard is not compatible with coreboot. 1. Gigabyte GA-Z77-HD3 Motherboard Intel(R) Core(TM) i5-3570K CPU @ 3.40GHz 2. lspci -tvnn -[:00]-+-00.0 Intel Corporation Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller [8086:0150] +-01.0-[01]--+-00.0 Advanced Micro Devices, Inc. [AMD/ATI] Caicos [Radeon HD 6450/7450/8450] [1002:6779] |\-00.1 Advanced Micro Devices, Inc. [AMD/ATI] Caicos HDMI Audio [Radeon HD 6400 Series] [1002:aa98] +-14.0 Intel Corporation 7 Series/C210 Series Chipset Family USB xHCI Host Controller [8086:1e31] +-16.0 Intel Corporation 7 Series/C210 Series Chipset Family MEI Controller #1 [8086:1e3a] +-1a.0 Intel Corporation 7 Series/C210 Series Chipset Family USB Enhanced Host Controller #2 [8086:1e2d] +-1b.0 Intel Corporation 7 Series/C210 Series Chipset Family High Definition Audio Controller [8086:1e20] +-1c.0-[02]-- +-1c.2-[03]00.0 Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller [10ec:8168] +-1c.3-[04-05]00.0-[05]-- +-1d.0 Intel Corporation 7 Series/C210 Series Chipset Family USB Enhanced Host Controller #1 [8086:1e26] +-1f.0 Intel Corporation Z77 Express Chipset LPC Controller [8086:1e44] +-1f.2 Intel Corporation 7 Series/C210 Series Chipset Family 4-port SATA Controller [IDE mode] [8086:1e00] +-1f.3 Intel Corporation 7 Series/C210 Series Chipset Family SMBus Controller [8086:1e22] \-1f.5 Intel Corporation 7 Series/C210 Series Chipset Family 2-port SATA Controller [IDE mode] [8086:1e08] 3. superiotool -dV superiotool r6637 Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0x, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0x, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0x, id=0x Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0x, id=0x Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0x, id=0x Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0x, id=0x Probing for ITE Super I/O (init=standard) at 0x25e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x25e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x25e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x25e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x25e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=standard) at 0x2e... Failed. Returned data: id=0x8728, rev=0x1 Probing for ITE Super I/O (init=it8502e) at 0x2e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x2e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x2e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=standard) at 0x4e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x4e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x4e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x4e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... Failed. Returned data: id=0x, rev=0xf Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x164e... Failed. Returned data: port=0xff, port+1=0xff Probing for
[coreboot] coreboot port for the ASRock FM2A88M-HD+
Hi! I am trying to port the ASRock FM2A88M-HD+ board. Should be a good board for my first coreboot port, since the reference code for the chipset and the datasheet for the superio chip are available. And it's quite inexpensive. I gathered some information and created a wiki page for it: http://www.coreboot.org/Board:asrock/fm2a88m-hd%2B Regards Felix -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Question about status of coreboot on the Samsung XE303CE ARM Chromebook (snow)
On Thu, Jan 30, 2014 at 9:53 AM, James MacMahon j...@operand.ca wrote: Hi everyone, Quick question: what is the status of coreboot + some payload being used with the Samsung XE303CE ARM Chromebook (snow)? The page at [http://www.coreboot.org/Chromebooks] says 'Snow has das U-Boot nativly installed, but a coreboot port is available.', and the page at [http://www.coreboot.org/Supported_Motherboards] has 'Google Snow - Samsung Exynos 5250' under the 'Motherboards supported in coreboot', but I haven't been able to find any blog / example of anyone actually flashing coreboot + some payload and booting their Chromebook like a regular computer. Right now it's close, but not quite close enough to be useful. The coreboot code should work, however there are some missing pieces that make it difficult to use in a meaningful manner: - We don't have a generic payload to use with coreboot on this platform. The earlier work was done using Depthcharge which is a small payload specific for booting ChromeOS (with its verified boot mechanism and such). There is some (unfinished?) work to port FILO over, but I don't know what the status is. You could also try using a Linux kernel as a payload, but that has yet to be tried on this particular platform. - To get serial console output, you need a debug board for Chromebooks which is unfortunately not easy to come by. Due to this limitation, if you are really intent on doing coreboot development on ARM it might be better to start with a more readily hackable platform such as the Cubieboard or Beaglebone. It seems like there is a port available but no one has tried it from start to finish on the ARM Chromebook (where my definition of finish in this context is 'booting with coreboot to stock Debian Linux', for example). I'm very keen on doing this myself, and was hoping to find some example that I could read through or even follow. This whole process of flashing a new BIOS is very new to me, and I'm wary because of the potential to easily brick my device (however I'm not scared off by reflashing or external chip programming if it comes to it, I'd just like to avoid it). There are a few wiki pages out there which detail the steps necessary to boot Debian/Ubuntu with the U-Boot firmware that ships with the device. Here is one from debian.org: https://wiki.debian.org/InstallingDebianOn/Samsung/ARMChromebook For most people I would recommend that approach since it's a lot less risky and better tested. -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Unable to start correctly coreboot on Asus f2a85-m REV 1.02
2014-02-01 Rudolf Marek r.ma...@assembler.cz: You should see some output of coreboot. Capture it via (ctrl a l shortcut in minicom) to a file and send it back to list. If is something unclear, please let us know. You need to make it up to next Friday. I will be then long time AFK and I will back in March. Perfect thank you for this whole procedure. This is what I obtain: My rom (with my vga bios): coreboot-4.0-5394-gba6b07e Thu Jan 30 19:48:58 CET 2014 starting... BSP Family_Model: 00610f31 cpu_init_detectedx = agesawrapper_amdinitreset Your rom (with your vga bios): coreboot-4.0-5310-g065289c Tue Jan 21 15:52:56 CET 2014 starting... BSP Family_Model: 00610f31 cpu_init_detectedx = agesawrapper_amdinitreset idwer rom (http://ra.openbios.org/~idwer/f2a85-m/coreboot_1002_990c.rom): coreboot-4.0-4745-g1ce4860-dirty Tue Oct 29 17:29:28 UTC 2013 starting... BSP Family_Model: 00610f31 cpu_init_detectedx = agesawrapper_amdinitreset Obviously this should be the processor that is the problem. Thanks, Best regards, HacKurx -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
