[coreboot] Need Help!!
I need help. They gave me a motherboard "asrock g31m-s rev 1.10" problem. Any operating system tells me it is incompatible with ACPI and ACPI 1.1 supposed to support. The only way to make it work with linux kernel is passing to the "acpi = no" parameter. It came with bios version 1.6 (checksum ok) and the un updating with 2.1 "asrock g31m-s rev 2" since rev 1.10 could not find it anywhere. My question is, will this be a hardware problem, will be solved by installing a ROM open-source, for this I need to add the code to the chipset LE82G31 coreboot project. I am from Cuba. Thanks in advance. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] GSoC-2014- coreboot mainboard test suite
Hi Muhammad, On Sun, Mar 2, 2014 at 1:01 AM, Muhammad Ramshad wrote: > Hi, > > I am Muhammad Ramshad currently pursuing my degree program in University of > Moratuwa in the field of Electronic and Telecommunication Engineering. > I am always interested learning new technologies and knowledge, so i found > that GSoC is really a good platform for me to learn new things. > > When i search through the projects and organizations the coreboot project > grabbed my focus towards it because i am more interested in Digital System > Design and hardware a level development like processor design and ISA > designs. > > at the moment i m not much familiar with coreboot, but i always more > committed towards work and a fast learner, these days i spent my time to > become familiar with coreboot. > > I am interested in writing a proposal for " > > coreboot mainboard test suite > > So i expect your guidance to make this success and hope to contribute even > if my proposal will not selected for GSoC > > Thanks > > regards > > > -- > coreboot mailing list: coreboot@coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot Please ignore the my last email and use this thread. Also, it is customary in open source software to use plain text email. Please check your email settings. Welcome to coreboot and we are glad that you are interested in GSoC. Please take some time to read the GSoC page and join IRC. You will need to become familiar with coreboot and the needs of the test suite if you are going to apply for coreboot GSoC. Building and running coreboot with qemu is the first step, again there are instructions on the website. Please feel free to ask questions as you have them. http://www.coreboot.org/GSoC Regards, Marc -- http://se-eng.com -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] GSoC 2014
Hi Ramshad, On Sun, Mar 2, 2014 at 1:00 AM, Muhammad Ramshad wrote: > Hi, > > I am Muhammad Ramshad currently pursuing my degree program in University of > Moratuwa in the field of Electronic and Telecommunication Engineering. > I am always interested learning new technologies and knowledge, so i found > that GSoC is really a good platform for me to learn new things. > > When i search through the projects and organizations the coreboot project > grabbed my focus towards it because i am more interested in Digital System > Design and hardware a level development like processor design and ISA > designs. > > at the moment i m not much familiar with coreboot, but i always more > committed towards work and a fast learner, these days i spent my time to > become familiar with coreboot. > > I am interested in writing a proposal for " > > coreboot mainboard test suite > > So i expect your guidance to make this success and hope to contribute even > if my proposal will not selected for GSoC > > Thanks > > regards > > Ramshad Welcome to coreboot and we are glad that you are interested in GSoC. Please take some time to read the GSoC page and join IRC. You will need to become familiar with coreboot and the needs of the test suite if you are going to apply for coreboot GSoC. Building and running coreboot with qemu is the first step, again there are instructions on the website. Please feel free to ask questions as you have them. http://www.coreboot.org/GSoC Regards, Marc -- http://se-eng.com -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] F2A85-M coreboot not working
Rostislav Lisovy [mailto:lis...@gmail.com] wrote: ]On Sun, 2014-03-02 at 00:00 -0600, Scott Duplichan wrote: ]> This looks like a divide exception. Finding the source code ]> for the failing divide might help narrow down the problem. I ]> can't recreate your binary exactly so I can't find the failing ]> instruction from the eip value. But based on register values, ]> it looks like it is somewhere around line 334 of file ]> amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c ]> You might be able to use the link map, disassembly, or debug ]> prints to figure out the exact source line that is failing. ] ]I compiled the GDB support and connected to it from the other computer. ]The outcome of the debugging: ] ]_text () at src/arch/x86/lib/c_start.S:89 ]warning: Source file is more recent than executable. ]89 callmain ](gdb) c ]Continuing. ] ]Program received signal SIGFPE, Arithmetic exception. ]0x0022fabf in GfxGmcInitializeSequencerTN (Gfx=0x1660) at ]src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c:334 ]warning: Source file is more recent than executable. ]334 scale_mp0 = (GfxLibGetMaxSclk (GnbLibGetHeader (Gfx)) * 100) / memps0_freq; ] ](gdb) p memps0_freq ]$1 = 0 ] ](gdb) p Gfx ]$2 = (GFX_PLATFORM_CONFIG *) 0x1660 ] ](gdb) l ]329 } ]330 ]331 //scale_mp0 = sclk_max_freq / memps0_freq ]332 //scale_mp1 = sclk_max_freq / memps1_freq ]333 //Multiply it by 100 to avoid dealing with floating point values ]334 scale_mp0 = (GfxLibGetMaxSclk (GnbLibGetHeader (Gfx)) * 100) / memps0_freq; ]335 scale_mp1 = (GfxLibGetMaxSclk (GnbLibGetHeader (Gfx)) * 100) / memps1_freq; ]336 ]337 GnbRegisterReadTN (TYPE_GMM , 0x2774 , &ex1047.Value, 0, GnbLibGetHeader (Gfx)); ]338 GnbRegisterReadTN (TYPE_GMM , 0x2778 , &ex1048.Value, 0, GnbLibGetHeader (Gfx)); ] ](gdb) p memps1_freq ]$5 = 333 It is good to see you have a debugger working. That confirms the problem really is line 334. You dumped memps1_freq, but line 334 divides by memps0_freq. Presumable memps0_freq is zero. If the failing instruction is "div esi", then memps0_freq=0 is confirmed by your original email that shows value 0 in the esi register. Apparently something is going wrong with the code a few lines above that initializes memps0_freq. You could step through that code and try to understand the problem. You could also try forcing a non-zero value such as 333 into memps0_freq to see how much farther execution gets. Thanks, Scott ]Regards; ]Rostislav Lisovy -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] F2A85-M coreboot not working
On Sun, 2014-03-02 at 00:00 -0600, Scott Duplichan wrote: > This looks like a divide exception. Finding the source code > for the failing divide might help narrow down the problem. I > can't recreate your binary exactly so I can't find the failing > instruction from the eip value. But based on register values, > it looks like it is somewhere around line 334 of file > amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c > You might be able to use the link map, disassembly, or debug > prints to figure out the exact source line that is failing. I forgot to add backtrace so here it comes: Program received signal SIGFPE, Arithmetic exception. 0x0022fabf in GfxGmcInitializeSequencerTN (Gfx=0x1660) at src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c:334 warning: Source file is more recent than executable. 334 scale_mp0 = (GfxLibGetMaxSclk (GnbLibGetHeader (Gfx)) * 100) / memps0_freq; (gdb) bt #0 0x0022fabf in GfxGmcInitializeSequencerTN (Gfx=0x1660) at src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c:334 #1 GfxGmcInitTN (Gfx=0x1660) at src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c:534 #2 0x00231898 in GfxMidInterfaceTN (StdHeader=0x100123e3) at src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxMidInitTN.c:183 #3 0x00239f90 in GnbLibDispatchFeatures (ConfigTable=0x2b1a10 , StdHeader=StdHeader@entry=0x100123e3) at src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbLibFeatures.c:99 #4 0x0023a107 in GnbInitAtMid (MidParamsPtr=MidParamsPtr@entry=0x100123e3) at src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtMid.c:92 #5 0x00246d98 in AmdInitMid (MidParams=0x100123e3) at src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitMid.c:159 #6 0x00262629 in agesawrapper_amdinitmid () at src/mainboard/asus/f2a85-m/agesawrapper.c:398 #7 0x00260308 in domain_enable_resources (dev=0x2afab4 <_dev5>) at src/northbridge/amd/agesa/family15tn/northbridge.c:570 #8 0x0026a4f1 in enable_resources (link=0x2af680 ) at src/device/device.c:876 #9 0x0026b64f in dev_enable () at src/device/device.c:1121 #10 0x00264a65 in bs_dev_enable (arg=0x0) at src/lib/hardwaremain.c:163 #11 0x00277749 in bs_walk_state_machine () at src/lib/hardwaremain.c:382 #12 main () at src/lib/hardwaremain.c:479 Thanks; Rostislav Lisovy -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] F2A85-M coreboot not working
On Sun, 2014-03-02 at 00:00 -0600, Scott Duplichan wrote: > This looks like a divide exception. Finding the source code > for the failing divide might help narrow down the problem. I > can't recreate your binary exactly so I can't find the failing > instruction from the eip value. But based on register values, > it looks like it is somewhere around line 334 of file > amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c > You might be able to use the link map, disassembly, or debug > prints to figure out the exact source line that is failing. I compiled the GDB support and connected to it from the other computer. The outcome of the debugging: _text () at src/arch/x86/lib/c_start.S:89 warning: Source file is more recent than executable. 89 callmain (gdb) c Continuing. Program received signal SIGFPE, Arithmetic exception. 0x0022fabf in GfxGmcInitializeSequencerTN (Gfx=0x1660) at src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c:334 warning: Source file is more recent than executable. 334 scale_mp0 = (GfxLibGetMaxSclk (GnbLibGetHeader (Gfx)) * 100) / memps0_freq; (gdb) p memps0_freq $1 = 0 (gdb) p Gfx $2 = (GFX_PLATFORM_CONFIG *) 0x1660 (gdb) l 329 } 330 331 //scale_mp0 = sclk_max_freq / memps0_freq 332 //scale_mp1 = sclk_max_freq / memps1_freq 333 //Multiply it by 100 to avoid dealing with floating point values 334 scale_mp0 = (GfxLibGetMaxSclk (GnbLibGetHeader (Gfx)) * 100) / memps0_freq; 335 scale_mp1 = (GfxLibGetMaxSclk (GnbLibGetHeader (Gfx)) * 100) / memps1_freq; 336 337 GnbRegisterReadTN (TYPE_GMM , 0x2774 , &ex1047.Value, 0, GnbLibGetHeader (Gfx)); 338 GnbRegisterReadTN (TYPE_GMM , 0x2778 , &ex1048.Value, 0, GnbLibGetHeader (Gfx)); (gdb) p memps1_freq $5 = 333 Regards; Rostislav Lisovy -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] GSoC-2014- coreboot mainboard test suite
On Sun, Mar 02, 2014 at 12:12:38PM +0100, Vladimir 'φ-coder/phcoder' Serbinenko wrote: > On 02.03.2014 09:01, Muhammad Ramshad wrote: > > When i search through the projects and organizations the coreboot > > project grabbed my focus towards it because i am more interested in > > Digital System Design and hardware a level development like processor > > design and ISA designs. > And absolutely no idea that HTML messages are not welcome on mailing > list. Use ASCII messages. It will also prevent you from screaming big > letters in the middle of a message. Vladimir, could you please be a bit more welcoming to potential GSOC students, here and on IRC, thanks! Regards, Björn > -- > coreboot mailing list: coreboot@coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot -- pgpjA7b5Fnhto.pgp Description: PGP signature -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] GSoC-2014- coreboot mainboard test suite
On 02.03.2014 09:01, Muhammad Ramshad wrote: > When i search through the projects and organizations the coreboot > project grabbed my focus towards it because i am more interested in > Digital System Design and hardware a level development like processor > design and ISA designs. And absolutely no idea that HTML messages are not welcome on mailing list. Use ASCII messages. It will also prevent you from screaming big letters in the middle of a message. signature.asc Description: OpenPGP digital signature -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] GSoC-2014- coreboot mainboard test suite
Hi, I am Muhammad Ramshad currently pursuing my degree program in University of Moratuwa in the field of Electronic and Telecommunication Engineering. I am always interested learning new technologies and knowledge, so i found that GSoC is really a good platform for me to learn new things. When i search through the projects and organizations the coreboot project grabbed my focus towards it because i am more interested in Digital System Design and hardware a level development like processor design and ISA designs. at the moment i m not much familiar with coreboot, but i always more committed towards work and a fast learner, these days i spent my time to become familiar with coreboot. I am interested in writing a proposal for " coreboot mainboard test suite So i expect your guidance to make this success and hope to contribute even if my proposal will not selected for GSoC Thanks regards -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
