Re: [coreboot] 7042: cannot load payload
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 To clarify, this is a ThinkPad X60. GRUB2 payload (my own grub.elf, which I know is fine), native graphics. Microcode removed. On 11/10/14 04:08, The Gluglug wrote: > I tried with latest master which has 7042 merged. Current commit > here is 0a66991a345f437e957ecc0ddeed70bc304d2a43 > > Is this related? > > coreboot-4.0-7016-g0a66991-7BETC7WW (2.08 ) Sat Oct 11 03:53:37 > BST 2014 starting... > > Mobile Intel(R) 82945GM/GME Express Chipset (G)MCH capable of up to > FSB 800 MHz (G)MCH capable of up to DDR2-667 Setting up static > southbridge registers... GPIOS... done. Disabling Watchdog > reboot... done. Setting up static northbridge registers... done. > Waiting for MCHBAR to come up...ok PM1_CNT: 1c00 SMBus > controller enabled. Setting up RAM controller. This mainboard > supports Dual Channel Operation. DDR II Channel 0 Socket 0: x16DS > DDR II Channel 1 Socket 0: x8DDS Memory will be driven at 667MHz > with CAS=5 clocks tRAS = 15 cycles tRP = 5 cycles tRCD = 5 cycles > Refresh: 7.8us tWR = 5 cycles DIMM 0 side 0 = 512 MB DIMM 0 side 1 > = 512 MB DIMM 2 side 0 = 1024 MB DIMM 2 side 1 = 1024 MB tRFC = 43 > cycles Setting Graphics Frequency... FSB: 667 MHz Voltage: 1.05V > Render: 250MHz Display: 200MHz Setting Memory Frequency... > CLKCFG=0x00010023, CLKCFG=0x00010043, ok Setting mode of operation > for memory channels...Dual Channel Assymetric. Programming Clock > Crossing...MEM=667 FSB=667... ok Setting RAM size... C0DRB = > 0x20202010 C1DRB = 0x60606040 TOLUD = 0x00c0 Setting row > attributes... C0DRA = 0x0033 C1DRA = 0x0033 DIMM0 has 8 banks. > DIMM2 has 8 banks. one dimm per channel config.. Initializing > System Memory IO... Programming Dual Channel RCOMP Table Index: 3 > Programming DLL Timings... Enabling System Memory IO... jedec > enable sequence: bank 0 jedec enable sequence: bank 1 bankaddr from > bank size of rank 0 jedec enable sequence: bank 4 bankaddr from > bank size of rank 1 jedec enable sequence: bank 5 bankaddr from > bank size of rank 4 receive_enable_autoconfig() for channel 0 > find_strobes_low() set_receive_enable() medium=0x3, coarse=0x5 > set_receive_enable() medium=0x1, coarse=0x5 set_receive_enable() > medium=0x1, coarse=0x5 find_strobes_edge() set_receive_enable() > medium=0x1, coarse=0x5 add_quarter_clock() mediumcoarse=15 fine=a1 > [1;63r[63;1H set_receive_enable() medium=0x3, coarse=0x5 > find_preamble() set_receive_enable() medium=0x3, coarse=0x4 > set_receive_enable() medium=0x3, coarse=0x3 add_quarter_clock() > mediumcoarse=0f fine=21 normalize() set_receive_enable() > medium=0x0, coarse=0x4 receive_enable_autoconfig() for channel 1 > find_strobes_low() set_receive_enable() medium=0x3, coarse=0x5 > set_receive_enable() medium=0x1, coarse=0x5 find_strobes_edge() > set_receive_enable() medium=0x1, coarse=0x5 add_quarter_clock() > mediumcoarse=15 fine=b2 set_receive_enable() medium=0x3, > coarse=0x5 find_preamble() set_receive_enable() medium=0x3, > coarse=0x4 set_receive_enable() medium=0x3, coarse=0x3 > add_quarter_clock() mediumcoarse=0f fine=32 normalize() > set_receive_enable() medium=0x0, coarse=0x4 RAM initialization > finished. Setting up Egress Port RCRB Loading port arbitration > table ...ok Wait for VC1 negotiation ...ok Setting up DMI RCRB Wait > for VC1 negotiation ...done.. Internal graphics: enabled Waiting > for DMI hardware...ok Enabling PCI Express x16 Link SLOTSTS: > Disabling PCI Express x16 Link Wait for link to enter detect > state... ok Setting up Root Complex Topology CBMEM: root @ bf7ff000 > 254 entries. Trying CBFS ramstage loader. CBFS: loading stage > fallback/ramstage @ 0x10 (286780 bytes), entry @ 0x10 > coreboot-4.0-7016-g0a66991-7BETC7WW (2.08 ) Sat Oct 11 03:53:37 > BST 2014 booting... BS: Entering BS_PRE_DEVICE state. CBMEM: > recovering 4/254 entries from root @ bf7ff000 Moving GDT to > bf7dc000...ok BS: Exiting BS_PRE_DEVICE state. BS: BS_PRE_DEVICE > times (us): entry 7279 run 2979 exit 0 BS: Entering > BS_DEV_INIT_CHIPS state. BS: Exiting BS_DEV_INIT_CHIPS state. BS: > BS_DEV_INIT_CHIPS times (us): entry 0 run 3324 exit 0 BS: Entering > BS_DEV_ENUMERATE state. Enumerating buses... Show all devs...Before > device enumeration. Root Device: enabled 1 CPU_CLUSTER: 0: enabled > 1 APIC: 00: enabled 1 DOMAIN: : enabled 1 PCI: 00:00.0: enabled > 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 1 PCI: 00:1b.0: > enabled 1 PCI: 00:1c.0: enabled 1 PCI: 00:1c.1: enabled 1 PCI: > 00:1d.0: enabled 1 PCI: 00:1d.1: enabled 1 PCI: 00:1d.2: enabled 1 > PCI: 00:1d.3: enabled 1 PCI: 00:1d.7: enabled 1 PCI: 00:1f.0: > enabled 1 PNP: 00ff.1: enabled 1 PNP: 00ff.2: enabled 1 PNP: > 164e.2: enabled 1 PNP: 164e.3: enabled 1 PNP: 164e.7: enabled 1 > PNP: 164e.19: enabled 1 PNP: 002e.0: enabled 0 PNP: 002e.1: enabled > 1 PNP: 002e.2: enabled 0 PNP: 002e.3: enabled 1 PNP: 002e.7: > enabled 1 PNP: 002e.a: enabled 0 PCI: 00:1f.1: enabled 1 PCI: > 00:1f.2: enabled 1 PCI: 00:1f
[coreboot] 7042: cannot load payload
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 I tried with latest master which has 7042 merged. Current commit here is 0a66991a345f437e957ecc0ddeed70bc304d2a43 Is this related? coreboot-4.0-7016-g0a66991-7BETC7WW (2.08 ) Sat Oct 11 03:53:37 BST 2014 starting... Mobile Intel(R) 82945GM/GME Express Chipset (G)MCH capable of up to FSB 800 MHz (G)MCH capable of up to DDR2-667 Setting up static southbridge registers... GPIOS... done. Disabling Watchdog reboot... done. Setting up static northbridge registers... done. Waiting for MCHBAR to come up...ok PM1_CNT: 1c00 SMBus controller enabled. Setting up RAM controller. This mainboard supports Dual Channel Operation. DDR II Channel 0 Socket 0: x16DS DDR II Channel 1 Socket 0: x8DDS Memory will be driven at 667MHz with CAS=5 clocks tRAS = 15 cycles tRP = 5 cycles tRCD = 5 cycles Refresh: 7.8us tWR = 5 cycles DIMM 0 side 0 = 512 MB DIMM 0 side 1 = 512 MB DIMM 2 side 0 = 1024 MB DIMM 2 side 1 = 1024 MB tRFC = 43 cycles Setting Graphics Frequency... FSB: 667 MHz Voltage: 1.05V Render: 250MHz Display: 200MHz Setting Memory Frequency... CLKCFG=0x00010023, CLKCFG=0x00010043, ok Setting mode of operation for memory channels...Dual Channel Assymetric. Programming Clock Crossing...MEM=667 FSB=667... ok Setting RAM size... C0DRB = 0x20202010 C1DRB = 0x60606040 TOLUD = 0x00c0 Setting row attributes... C0DRA = 0x0033 C1DRA = 0x0033 DIMM0 has 8 banks. DIMM2 has 8 banks. one dimm per channel config.. Initializing System Memory IO... Programming Dual Channel RCOMP Table Index: 3 Programming DLL Timings... Enabling System Memory IO... jedec enable sequence: bank 0 jedec enable sequence: bank 1 bankaddr from bank size of rank 0 jedec enable sequence: bank 4 bankaddr from bank size of rank 1 jedec enable sequence: bank 5 bankaddr from bank size of rank 4 receive_enable_autoconfig() for channel 0 find_strobes_low() set_receive_enable() medium=0x3, coarse=0x5 set_receive_enable() medium=0x1, coarse=0x5 set_receive_enable() medium=0x1, coarse=0x5 find_strobes_edge() set_receive_enable() medium=0x1, coarse=0x5 add_quarter_clock() mediumcoarse=15 fine=a1 [1;63r[63;1H set_receive_enable() medium=0x3, coarse=0x5 find_preamble() set_receive_enable() medium=0x3, coarse=0x4 set_receive_enable() medium=0x3, coarse=0x3 add_quarter_clock() mediumcoarse=0f fine=21 normalize() set_receive_enable() medium=0x0, coarse=0x4 receive_enable_autoconfig() for channel 1 find_strobes_low() set_receive_enable() medium=0x3, coarse=0x5 set_receive_enable() medium=0x1, coarse=0x5 find_strobes_edge() set_receive_enable() medium=0x1, coarse=0x5 add_quarter_clock() mediumcoarse=15 fine=b2 set_receive_enable() medium=0x3, coarse=0x5 find_preamble() set_receive_enable() medium=0x3, coarse=0x4 set_receive_enable() medium=0x3, coarse=0x3 add_quarter_clock() mediumcoarse=0f fine=32 normalize() set_receive_enable() medium=0x0, coarse=0x4 RAM initialization finished. Setting up Egress Port RCRB Loading port arbitration table ...ok Wait for VC1 negotiation ...ok Setting up DMI RCRB Wait for VC1 negotiation ...done.. Internal graphics: enabled Waiting for DMI hardware...ok Enabling PCI Express x16 Link SLOTSTS: Disabling PCI Express x16 Link Wait for link to enter detect state... ok Setting up Root Complex Topology CBMEM: root @ bf7ff000 254 entries. Trying CBFS ramstage loader. CBFS: loading stage fallback/ramstage @ 0x10 (286780 bytes), entry @ 0x10 coreboot-4.0-7016-g0a66991-7BETC7WW (2.08 ) Sat Oct 11 03:53:37 BST 2014 booting... BS: Entering BS_PRE_DEVICE state. CBMEM: recovering 4/254 entries from root @ bf7ff000 Moving GDT to bf7dc000...ok BS: Exiting BS_PRE_DEVICE state. BS: BS_PRE_DEVICE times (us): entry 7279 run 2979 exit 0 BS: Entering BS_DEV_INIT_CHIPS state. BS: Exiting BS_DEV_INIT_CHIPS state. BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 3324 exit 0 BS: Entering BS_DEV_ENUMERATE state. Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 DOMAIN: : enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 1 PCI: 00:1b.0: enabled 1 PCI: 00:1c.0: enabled 1 PCI: 00:1c.1: enabled 1 PCI: 00:1d.0: enabled 1 PCI: 00:1d.1: enabled 1 PCI: 00:1d.2: enabled 1 PCI: 00:1d.3: enabled 1 PCI: 00:1d.7: enabled 1 PCI: 00:1f.0: enabled 1 PNP: 00ff.1: enabled 1 PNP: 00ff.2: enabled 1 PNP: 164e.2: enabled 1 PNP: 164e.3: enabled 1 PNP: 164e.7: enabled 1 PNP: 164e.19: enabled 1 PNP: 002e.0: enabled 0 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 0 PNP: 002e.3: enabled 1 PNP: 002e.7: enabled 1 PNP: 002e.a: enabled 0 PCI: 00:1f.1: enabled 1 PCI: 00:1f.2: enabled 1 PCI: 00:1f.3: enabled 1 I2C: 00:69: enabled 1 I2C: 00:54: enabled 1 I2C: 00:55: enabled 1 I2C: 00:56: enabled 1 I2C: 00:57: enabled 1 I2C: 00:5c: enabled 1 I2C: 00:5d: enabled 1 I2C: 00:5e: enabled 1 I2C: 00:5f: enabled 1 Compare with tree... Root Device: enabled 1
Re: [coreboot] broken boards
On 11.10.2014 03:20, Vladimir 'φ-coder/phcoder' Serbinenko wrote: > On 11.10.2014 03:03, ron minnich wrote: >> Android defaults sometimes surprise me. >> >> When we've had this kind of issue in the past a disassembly diff of >> good vs bad has sometimes led to diagnosis. I think you have a rough >> idea what's broken so start there. Painful but necessary. >> > .car.data is linked at wrong address. > Working: > 4 .car.data 00b4 ff7f ff7f 00012b00 2**5 > CONTENTS > Broken: > 4 .car.data 00ac 00012b00 2**5 > CONTENTS > http://review.coreboot.org/7042 >> Ron >> >> >> > > signature.asc Description: OpenPGP digital signature -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] broken boards
On to boarding maybe we can fix it in Prague -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] broken boards
What intrigues me is that I have been building x86 coreboot with this patch in place for a year. I wonder if we're missing a subsequent patch... -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] broken boards
On 11.10.2014 03:03, ron minnich wrote: > Android defaults sometimes surprise me. > > When we've had this kind of issue in the past a disassembly diff of > good vs bad has sometimes led to diagnosis. I think you have a rough > idea what's broken so start there. Painful but necessary. > .car.data is linked at wrong address. Working: 4 .car.data 00b4 ff7f ff7f 00012b00 2**5 CONTENTS Broken: 4 .car.data 00ac 00012b00 2**5 CONTENTS > Ron > > > signature.asc Description: OpenPGP digital signature -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] broken boards
Android defaults sometimes surprise me. When we've had this kind of issue in the past a disassembly diff of good vs bad has sometimes led to diagnosis. I think you have a rough idea what's broken so start there. Painful but necessary. Ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] broken boards
Sorry. Forgot to cc list On Oct 10, 2014 5:47 PM, "ron minnich" wrote: > > Yep. It's another fun "compare two images" good times. What differs between the good and bad binaries? > > Ndisasm is your friend here. > > I feel your pain:-( > > Ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] List being treated as spam by Google Mail
Hello! Is there anything that can be done from everyone else's end to convince Google Mail to stop trapping nearly everything I'm receiving from the list as spam? All of sudden 85 percent of the list is showing up there with the outlandish claim that people are reporting the list contents as such. After all I do note the footer that Mailman adds that shows the obvious about the list including how to change the settings for my entry, and even to leave the list should I want to do that. - Gregg C Levine gregg.drw...@gmail.com "This signature fought the Time Wars, time and again." -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] broken boards
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 The issue is that on affected machines, it's very hard to know what's happening because serial output doesn't even work. On 11/10/14 01:42, ron minnich wrote: > "It broke" is not a very useful diagnosis. Anyone care to report > what's going on? > > Thanks! > > Ron > -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) iQEcBAEBAgAGBQJUOH1VAAoJEP9Ft0z50c+ULhcH/3+WvN09RZmdGCMbbLxpC53r nKNRGWR4SQNIfmGrUGiWQeMqgeCG3iOzKsogPoaATyEaRB4npzJxw25NRZZTgHdU CGDpFB3yhcJBp0xWKCO4yv5QtjTPDgRq6Kt9fgq+Rg52EiKHiJch5nN2fTJ2hsdH jnptoNFbxUh4T7muqqS3ZPhJTJBujlfooB2+y0746RO/AmBGFn60RcEHngUzvDBW eC2662L1QgmdXRscCMdz10+6WSONWu65HcTuem54yS1QjgLupMu5hzs22bj/6Wcf 3nQOp76XppsFJzijEaxDOFxa1n+x1dWMW//RZAE8WXDtlqhVC1iAdpo/i7yXd6E= =hRFZ -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] broken boards
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 http://review.coreboot.org/#/c/7041/ This reverts a commit that was intended to help for non-x86 targets, related to finding cbmem tables. The commit that 7041 reverts caused X60, X201 and Google/panther (Haswell) not to boot. T60, X60 Tablet and macbook21 are probably also affected. Other boards may also be affected. Can everyone who has a recovery/unbricking method test the latest master -without- 7041 to see whether it fails to boot - the behaviour is: no image on screen, no serial output, machine fails to boot (it doesn't even reach the payload). Then if it does fail, try again with 7041 included and report back. -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) iQEcBAEBAgAGBQJUOHxqAAoJEP9Ft0z50c+Uei8IAMGn0g1wXwA/iMGHY1CYu6sx TDDXL/B7JZ3FxoBEQde/xETR2HoxhqSeoSxvxC58z9n08gx9w1tY2afoM/VYeo57 BEPCYGbBpVo8Sp5JsdEWZ3eWgVEUBEL7vKm4GagpLcnYdQk0o+Mm61x6pm/UJ7lt c+AYhiFsgsqO9aO1HH8qG1uTsJ1W+BK9EPxNBQrJYsZhguJjgTzYogshZ7TnFPje 0qXouMa58rvHouYMw1Cvnv0tnV39wYEVAbyAqhYM7xhktLRtgSe3KCUUAE0DVCES rX/bTF4FPiNMuxZngD8zASFBxHJ6xbSsk2ubJkWIEdIfC24SvyGp9bw3iLuQvlc= =3nVL -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] commit 6b330f2a bricked my x60; a296f9e3 was working.
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 I addded this to the commit message on 7041. Thanks! On 11/10/14 00:38, Matt DeVillier wrote: > same issue here on Google/panther (Haswell), reverting the commit > fixed things > > On 10/10/2014 4:09 PM, The Gluglug wrote: Based on advice from > Alexander I did: git revert 35382a6e > > Made my X60 boot, where without the revert I had the same issue as > Andrew Engelbrecht that the machine > didn't boot; not even serial output worked. > > I pushed the revert commit to gerrit for others to look at: > http://review.coreboot.org/#/c/7041/ > > Thanks to Alexander for the bisect! > > On 10/10/14 21:08, Alexander Couzens wrote: Hi Andrew, on my x201t I got the same problems. I bisect it to cbmem console: Locate the preram console with a symbol instead of a section. (commit 35382a6e, Change-Id: I3257b981e). @Gabe: Do you tested the commit with SeaBios as payload? @Andrew: You can also use a raspberry pi or a beaglebone black. They are a lot faster than a buspirate (30min -> 5min). Best, Alex cfg: http://lynxis.crew.c-base.org/coreboot.config.762d53d41_without_cbmem >> > -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) iQEcBAEBAgAGBQJUOG98AAoJEP9Ft0z50c+UDmwH+wUHiUNK1IcVksyhnuchBMr0 5aafjMD7QXtQ9Rs3FtXRRyCIYRbTIwOBMIx7yz9zRe2xYEfpq9GQ6G8yuUa+GfFA m3t/mwHtCJg34g9rXgqUf1s9fnP0Nb1A6L9ss4zqAvrV1TW4jDxKbSEKm/StCArG H6Y6qjXLhAYf/RVkf7xf9q4v51amJ/hbM72m/MOLbsqKz0yPJoDOKvP+ADFs+5b0 E93wJni/qkuRzHDSP7dsZVxAMb+bKaun9EFd+ZQftNV4Oz1pIr5s3whKhDiKHIuh NMmUY/miuXO07gqdQVjZYSg6xQFBqcNFg8q7qZEk2U+ZoN8bdx/F2zKVKML0ixc= =nGcR -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] commit 6b330f2a bricked my x60; a296f9e3 was working.
same issue here on Google/panther (Haswell), reverting the commit fixed things On 10/10/2014 4:09 PM, The Gluglug wrote: > -BEGIN PGP SIGNED MESSAGE- > Hash: SHA1 > > Based on advice from Alexander I did: > git revert 35382a6e > > Made my X60 boot, where without the revert I had the same issue as > Andrew Engelbrecht that the machine didn't > boot; not even serial output worked. > > I pushed the revert commit to gerrit for others to look at: > http://review.coreboot.org/#/c/7041/ > > Thanks to Alexander for the bisect! > > On 10/10/14 21:08, Alexander Couzens wrote: >> Hi Andrew, >> >> on my x201t I got the same problems. I bisect it to cbmem console: >> Locate the preram console with a symbol instead of a section. >> (commit 35382a6e, Change-Id: I3257b981e). >> >> @Gabe: Do you tested the commit with SeaBios as payload? >> >> @Andrew: You can also use a raspberry pi or a beaglebone black. >> They are a lot faster than a buspirate (30min -> 5min). >> >> Best, Alex >> >> cfg: >> http://lynxis.crew.c-base.org/coreboot.config.762d53d41_without_cbmem >> >> >> >> > -BEGIN PGP SIGNATURE- > Version: GnuPG v1.4.11 (GNU/Linux) > > iQEcBAEBAgAGBQJUOEr5AAoJEP9Ft0z50c+U0MsH/jh1preGRFV5QXyeybJcxC+k > xhJAz+NoLdD57PAPP4y858Z4u+yV/ShWw+VlR+gQbf/1K8goCgV7w66eosWCg3OO > 6OryX7Eq/gNuLe2Z8Ei0fhduYHUhipwZFRlHJ1AF2qKzqoAoIodcm3UAoj/MK6R6 > e7UeHLmgQRe2YsUBD9eDHPxTkYleCoHt9gHGayWZE7tRnCWXglyDUkY96EFdToi8 > CxsEr6FmE6sDIskgWAYeHfgpWq/u0TyYasaP+FkWKrAVt9E7U7SK00/PZtFizUqR > GKtFKnAB1faR8Y+3DgtXXq0+KmtQ392Kmp1goN3BaSB87IF2E4zY9jyQLIXdU6w= > =504N > -END PGP SIGNATURE- > -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [coreboot-gerrit] Patch set updated for coreboot: 3906937 amdfam14: Switch to per-device ACPI
Success. Addresses are slightly different and new XSDT table but both are ok and expected. On 11.10.2014 00:16, Paul Menzel wrote: > Dear Vladimir, > > > Am Mittwoch, den 08.10.2014, 21:29 +0200 schrieb Vladimir Serbinenko: >> Vladimir Serbinenko (phco...@gmail.com) just uploaded a new patch set to >> gerrit, which you can find at http://review.coreboot.org/7031 >> >> -gerrit >> >> commit 390693798eebf2a371b32915a5ee239ba0b3a8bd >> Author: Vladimir Serbinenko >> Date: Wed Oct 8 21:18:31 2014 +0200 >> >> amdfam14: Switch to per-device ACPI >> >> Change-Id: Icc663c28713f2d872bfeb1749303ce92db953bf5 >> Signed-off-by: Vladimir Serbinenko >> --- >> src/mainboard/amd/inagua/acpi_tables.c | 206 >> >> src/mainboard/amd/persimmon/acpi_tables.c | 205 >> >> src/mainboard/amd/south_station/acpi_tables.c | 206 >> >> src/mainboard/amd/union_station/acpi_tables.c | 206 >> >> src/mainboard/asrock/e350m1/acpi_tables.c | 206 >> >> src/mainboard/gizmosphere/gizmo/acpi_tables.c | 206 >> >> src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c| 207 >> - >> src/mainboard/lippert/frontrunner-af/acpi_tables.c | 206 >> >> src/mainboard/lippert/toucan-af/acpi_tables.c | 206 >> >> src/northbridge/amd/agesa/family14/Kconfig | 1 + >> src/northbridge/amd/agesa/family14/northbridge.c | 131 + >> 11 files changed, 132 insertions(+), 1854 deletions(-) > > […] > > please find the acpidump outputs from running on the ASRock E350M1 > attached. > > > Thanks, > > Paul > > > signature.asc Description: OpenPGP digital signature -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] commit 6b330f2a bricked my x60; a296f9e3 was working.
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Based on advice from Alexander I did: git revert 35382a6e Made my X60 boot, where without the revert I had the same issue as Andrew Engelbrecht that the machine didn't boot; not even serial output worked. I pushed the revert commit to gerrit for others to look at: http://review.coreboot.org/#/c/7041/ Thanks to Alexander for the bisect! On 10/10/14 21:08, Alexander Couzens wrote: > Hi Andrew, > > on my x201t I got the same problems. I bisect it to cbmem console: > Locate the preram console with a symbol instead of a section. > (commit 35382a6e, Change-Id: I3257b981e). > > @Gabe: Do you tested the commit with SeaBios as payload? > > @Andrew: You can also use a raspberry pi or a beaglebone black. > They are a lot faster than a buspirate (30min -> 5min). > > Best, Alex > > cfg: > http://lynxis.crew.c-base.org/coreboot.config.762d53d41_without_cbmem > > > > -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) iQEcBAEBAgAGBQJUOEr5AAoJEP9Ft0z50c+U0MsH/jh1preGRFV5QXyeybJcxC+k xhJAz+NoLdD57PAPP4y858Z4u+yV/ShWw+VlR+gQbf/1K8goCgV7w66eosWCg3OO 6OryX7Eq/gNuLe2Z8Ei0fhduYHUhipwZFRlHJ1AF2qKzqoAoIodcm3UAoj/MK6R6 e7UeHLmgQRe2YsUBD9eDHPxTkYleCoHt9gHGayWZE7tRnCWXglyDUkY96EFdToi8 CxsEr6FmE6sDIskgWAYeHfgpWq/u0TyYasaP+FkWKrAVt9E7U7SK00/PZtFizUqR GKtFKnAB1faR8Y+3DgtXXq0+KmtQ392Kmp1goN3BaSB87IF2E4zY9jyQLIXdU6w= =504N -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] commit 6b330f2a bricked my x60; a296f9e3 was working.
Hi Andrew, on my x201t I got the same problems. I bisect it to cbmem console: Locate the preram console with a symbol instead of a section. (commit 35382a6e, Change-Id: I3257b981e). @Gabe: Do you tested the commit with SeaBios as payload? @Andrew: You can also use a raspberry pi or a beaglebone black. They are a lot faster than a buspirate (30min -> 5min). Best, Alex cfg: http://lynxis.crew.c-base.org/coreboot.config.762d53d41_without_cbmem signature.asc Description: PGP signature -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Coreboot FILO payload build fails when USB support enabled
Here is the patch I used to fix build error. diff --git a/drivers/usb.c b/drivers/usb.c index 0da6efa..a959389 100644 --- a/drivers/usb.c +++ b/drivers/usb.c @@ -20,7 +20,7 @@ #include /* Only use this code if libpayload is compiled with USB stack */ -#ifdef CONFIG_USB +#ifdef CONFIG_USB_DISK #include #include #include Please let me know if this is correct and I should submit it On Fri, Oct 10, 2014 at 11:41 PM, Vipin Gahlaut wrote: > Hi, > > We need USB support in Filo. Our Linux kernel and file system is expected > to be on USB thumb driver. We have enabled USB in menuconfig; however build > fails with following errors. > > blockdev.c:(.text+0x18e): undefined reference to `usb_read' > /home/vgahlaut/coreboot-fsp/coreboot/payloads/filo/build/fs/blockdev.o: In > function `devopen': > blockdev.c:(.text+0x91e): undefined reference to `usb_probe' > > We are using latest FILO and Coreboot from git repository. These functions > seems to be defined in drivers/usb.c and usb.c is getting compiled. > > Problem seems to be due to the fact that CONFIG_USB=y in .config is > automatically removed during make and these function are defined in usb.c > under #ifdef CONFIG_USB > > Can you please suggest a solution and let me know why CONFIG_USB is > removed from my .config > -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Coreboot FILO payload build fails when USB support enabled
Hi, We need USB support in Filo. Our Linux kernel and file system is expected to be on USB thumb driver. We have enabled USB in menuconfig; however build fails with following errors. blockdev.c:(.text+0x18e): undefined reference to `usb_read' /home/vgahlaut/coreboot-fsp/coreboot/payloads/filo/build/fs/blockdev.o: In function `devopen': blockdev.c:(.text+0x91e): undefined reference to `usb_probe' We are using latest FILO and Coreboot from git repository. These functions seems to be defined in drivers/usb.c and usb.c is getting compiled. Problem seems to be due to the fact that CONFIG_USB=y in .config is automatically removed during make and these function are defined in usb.c under #ifdef CONFIG_USB Can you please suggest a solution and let me know why CONFIG_USB is removed from my .config -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] commit 6b330f2a bricked my x60; a296f9e3 was working.
a296f9e3d385d2d310aae1cdfd4a20c592de1d20 worked. 6b330f2a2462a72c2d10940b5e06b99f02b20297 bricked it. i'm not getting serial output from my x60, and the disk access light doesn't turn on. other lights flash after pressing the power button. the AC and (Z) lights stay on. there isn't any graphical output. i've attached both my .config files. the payloads for both roms were SeaBIOS. -andrew p.s. i suppose i'll need a bus pirate. i won't have it for a while, so i can't help binary searching for the broken commit right now. thanks for any help. :-) please CC me. > --- a296f9e3d385d2d310aae1cdfd4a20c592de1d20.conf 2014-10-10 > 12:39:13.088043119 -0400 > +++ 6b330f2a2462a72c2d10940b5e06b99f02b20297.conf 2014-10-10 > 12:39:38.072590776 -0400 > @@ -1,4 +1,4 @@ > -# This image was built using git revision > a296f9e3d385d2d310aae1cdfd4a20c592de1d20 > +# This image was built using git revision > 6b330f2a2462a72c2d10940b5e06b99f02b20297 > CONFIG_LOCALVERSION="" > CONFIG_CBFS_PREFIX="fallback" > CONFIG_COMPILER_GCC=y > @@ -124,7 +124,7 @@ > CONFIG_TTYS0_LCS=3 > CONFIG_CONSOLE_CBMEM=y > CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x2 > -CONFIG_CONSOLE_CAR_BUFFER_SIZE=0xc00 > +CONFIG_CONSOLE_PRERAM_BUFFER_SIZE=0xc00 > CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y > CONFIG_POST_DEVICE_NONE=y > CONFIG_POST_IO_PORT=0x80 # This image was built using git revision 6b330f2a2462a72c2d10940b5e06b99f02b20297 CONFIG_LOCALVERSION="" CONFIG_CBFS_PREFIX="fallback" CONFIG_COMPILER_GCC=y CONFIG_USE_OPTION_TABLE=y CONFIG_COMPRESS_RAMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y CONFIG_EARLY_CBMEM_INIT=y CONFIG_DYNAMIC_CBMEM=y CONFIG_VENDOR_LENOVO=y CONFIG_BOARD_SPECIFIC_OPTIONS=y CONFIG_MAINBOARD_DIR="lenovo/x60" CONFIG_MAINBOARD_PART_NUMBER="ThinkPad X60 / X60s / X60t" CONFIG_IRQ_SLOT_COUNT=18 CONFIG_MAINBOARD_VENDOR="Lenovo" CONFIG_MAX_CPUS=2 CONFIG_RAMTOP=0x20 CONFIG_HEAP_SIZE=0x4000 CONFIG_RAMBASE=0x10 CONFIG_VGA_BIOS_ID="8086,27a2" CONFIG_DRIVERS_PS2_KEYBOARD=y CONFIG_VGA_BIOS=y CONFIG_DCACHE_RAM_BASE=0xffdf8000 CONFIG_DCACHE_RAM_SIZE=0x8000 CONFIG_ACPI_SSDTX_NUM=0 CONFIG_VGA_BIOS_FILE="../x60/vga/vga-x60-bios-flashrom.bin" CONFIG_MMCONF_BASE_ADDRESS=0xf000 CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO" CONFIG_UART_FOR_CONSOLE=0 CONFIG_ID_SECTION_OFFSET=0x80 CONFIG_STACK_SIZE=0x1000 CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 CONFIG_CBFS_SIZE=0x20 CONFIG_POST_IO=y CONFIG_POST_DEVICE=y CONFIG_SEABIOS_MALLOC_UPPERMEMORY=y CONFIG_BOARD_LENOVO_X60=y CONFIG_SEABIOS_PS2_TIMEOUT=3000 CONFIG_MAINBOARD_VERSION="1.0" CONFIG_CPU_ADDR_BITS=36 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 CONFIG_BOARD_ROMSIZE_KB_2048=y CONFIG_COREBOOT_ROMSIZE_KB_2048=y CONFIG_COREBOOT_ROMSIZE_KB=2048 CONFIG_ROM_SIZE=0x20 CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad X60" CONFIG_ARCH_X86=y CONFIG_ARCH_BOOTBLOCK_X86_32=y CONFIG_ARCH_ROMSTAGE_X86_32=y CONFIG_ARCH_RAMSTAGE_X86_32=y CONFIG_AP_IN_SIPI_WAIT=y CONFIG_NUM_IPI_STARTS=2 CONFIG_PC80_SYSTEM=y CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/i945/bootblock.c" CONFIG_HAVE_CMOS_DEFAULT=y CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801gx/bootblock.c" CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y CONFIG_HPET_ADDRESS=0xfed0 CONFIG_BOOTBLOCK_SIMPLE=y CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" CONFIG_SOCKET_SPECIFIC_OPTIONS=y CONFIG_XIP_ROM_SIZE=0x1 CONFIG_CPU_INTEL_MODEL_6EX=y CONFIG_CPU_INTEL_MODEL_6FX=y CONFIG_SMM_TSEG_SIZE=0 CONFIG_CPU_INTEL_SOCKET_MFCPGA478=y CONFIG_SSE2=y CONFIG_UDELAY_LAPIC=y CONFIG_LAPIC_MONOTONIC_TIMER=y CONFIG_TSC_SYNC_MFENCE=y CONFIG_LOGICAL_CPUS=y CONFIG_CACHE_AS_RAM=y CONFIG_SMP=y CONFIG_AP_SIPI_VECTOR=0xf000 CONFIG_MMX=y CONFIG_SSE=y CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y CONFIG_CPU_MICROCODE_ADDED_DURING_BUILD=y CONFIG_CPU_MICROCODE_CBFS_GENERATE=y CONFIG_VIDEO_MB=0 CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y CONFIG_NORTHBRIDGE_INTEL_I945=y CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM=y CONFIG_CHANNEL_XOR_RANDOMIZATION=y CONFIG_HPET_MIN_TICKS=0x80 CONFIG_MAX_PIRQ_LINKS=4 CONFIG_EHCI_BAR=0xfef0 CONFIG_SOUTHBRIDGE_INTEL_COMMON=y CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y CONFIG_SOUTHBRIDGE_RICOH_RL5C476=y CONFIG_SUPERIO_NSC_PC87382=y CONFIG_SUPERIO_NSC_PC87392=y CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y CONFIG_H8_DOCK_EARLY_INIT=y CONFIG_EC_LENOVO_PMH7=y CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y CONFIG_PCI=y CONFIG_PCIX_PLUGIN_SUPPORT=y CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_AGP_PLUGIN_SUPPORT=y CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_PCI_BUS_SEGN_BITS=0 CONFIG_SUBSYSTEM_VENDOR_ID=0x CONFIG_SUBSYSTEM_DEVICE_ID=0x CONFIG_DRIVERS_ICS_954309=y CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y CONFIG_DRIVERS_LENOVO_WACOM=y CONFIG_DIGITIZER_AUTODETECT=y CONFIG_DRIVERS_UART=y CONFIG_DRIVERS_UART_8250IO=y CONFIG_HAVE_USBDEBUG=y CONFIG_MMCONF_SUPPORT_DEFAULT=y CONFIG_MMCONF_SUPPORT=y CONFIG_SQUELCH_EARLY_SMP=y CONFIG_CONSOLE_SERIAL=y CONFIG_TTYS0_BASE=0x3f8
