[coreboot] older coreboot (linuxbios) on a Geode GX1 from ak-systems
Dear, I've an older ThinClient from AK-systems apparently with an older linuxbios version installed. I can see the "old" penguin-gif on start. It is this board (see: http://ixbtlabs.com/articles2/ak-winterm-gp/) with NS geode GX1 and a dip32-BIOS chip (winbond w29c020c-90b), and CS5530A. My problem: it only starts from a Win2000-server! Nothing else. I hangs/waits with a blank screen and the linuxbios-penguin-gif... I've the possibilities to flash the chip, but howto "config" a new BIOS for this board? maybe someone has a ready BIOS-file :) I tested coreboot with another board (wyse Sx0, Geode GX2), but with no luck :(. Thx antonio -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] sourcing 128MB flash chips for an X60 with coreboot
Hello I would like to replace the flash chip with something larger, to add a minimal linux distribution and test some security ideas. I selected a few chips based on flashrom support, but I can't find any of them on my usual websites. On ebay, I can't find them in SOIC8 package. Yet IIRC, someone did that with a x60 running coreboot (just can't find the URL at the moment). Hopefully that person is even on the list! Would you have a recommended source to get 2 or 3 of them? ideally: M25P128 possible: MX25L128 05D N25Q128.3E W25Q128.V (because non-volatile write bit chips are produced by Macronix and Winbond) Thanks Charles -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Add Macronix MX25U6435F and MX25L6495F support
Dear sirs, Please help to update the new Macronix SPI Flash support in the ~coreboot/src/driver/spi/macronix.c . Thanks! Alex Lu CONFIDENTIALITY NOTE: This e-mail and any attachments may contain confidential information and/or personal data, which is protected by applicable laws. Please be reminded that duplication, disclosure, distribution, or use of this e-mail (and/or its attachments) or any part thereof is prohibited. If you receive this e-mail in error, please notify us immediately and delete this mail as well as its attachment(s) from your system. In addition, please be informed that collection, processing, and/or use of personal data is prohibited unless expressly permitted by personal data protection laws. Thank you for your attention and cooperation. Macronix International Co., Ltd. = CONFIDENTIALITY NOTE: This e-mail and any attachments may contain confidential information and/or personal data, which is protected by applicable laws. Please be reminded that duplication, disclosure, distribution, or use of this e-mail (and/or its attachments) or any part thereof is prohibited. If you receive this e-mail in error, please notify us immediately and delete this mail as well as its attachment(s) from your system. In addition, please be informed that collection, processing, and/or use of personal data is prohibited unless expressly permitted by personal data protection laws. Thank you for your attention and cooperation. Macronix International Co., Ltd. = macronix_mxic.patch Description: Binary data -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] With Linux as a payload how about ACPI boot flags?
Our current ASrock H81 Pro BTC mainboard have faulty firmware. Using acpidump, ACPI FADT declares that PCIe ASPM Not Supported in Boot Flags bit #4. Despite that the PCIe hardware does support ASPM when flipping the PCI registers manually. Asrock does not seem to understand and/or is not willing to turn this bit to off (=fix the issue) in their AMI based BIOS/firmware. When having Coreboot and Linux as payload how will that affect ACPI (FADT table) boot flags? -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] libpayload and LGPL code
Le 23/09/2014 17:29, Kevin O'Connor a écrit : > On Mon, Sep 22, 2014 at 06:35:30AM +0530, Chauhan, Himanshu wrote: >> On Monday, September 22, 2014, Peter Stuge wrote: >> >>> Paul Menzel wrote: `libpayload: Add Virtio layer and storage device support` >>> .. Some of the files are taken from SeaBIOS and are licensed under the GNU LGPLv3. Is that allowed/wanted to be in libpayload? >>> >>> I for one think it would be good to keep libpayload BSD-licensed. >>> >>> >>> Chauhan, Himanshu wrote: In that case would it make sense to put it in FILO which is GPL? >>> >>> Yes, I think that's a very good idea. >> >> But to my understanding, it would convert FILO from GPLv2 to GPLv3. Isn't >> it? > > The virtio code in SeaBIOS was relicensed to LGPLv3 so that it could > be distributed with SeaBIOS. I would reach out to the authors of that > virtio code to see if they are okay with a different license. Kevin, for my part, I don't care of the license : you can relicense my work as you want. Regards, Laurent signature.asc Description: OpenPGP digital signature -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Will coreboot work on my Haswell ASrock H81 Pro BTC? Nuvoton NCT6776F
1. Asrock, H81 Pro BTC, Intel Celeron G1820/G1840, Intel H81 2. # lspci -tvnn -[:00]-+-00.0 Intel Corporation 4th Gen Core Processor DRAM Controller [8086:0c00] +-01.0-[01]-- +-02.0 Intel Corporation Xeon E3-1200 v3/4th Gen Core Processor Integrated Graphics Controller [8086:0402] +-14.0 Intel Corporation 8 Series/C220 Series Chipset Family USB xHCI [8086:8c31] +-16.0 Intel Corporation 8 Series/C220 Series Chipset Family MEI Controller #1 [8086:8c3a] +-1a.0 Intel Corporation 8 Series/C220 Series Chipset Family USB EHCI #2 [8086:8c2d] +-1c.0-[02]-- +-1c.5-[03]00.0 Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller [10ec:8168] +-1d.0 Intel Corporation 8 Series/C220 Series Chipset Family USB EHCI #1 [8086:8c26] +-1f.0 Intel Corporation C220 Series Chipset Family H81 Express LPC Controller [8086:8c5c] +-1f.2 Intel Corporation 8 Series/C220 Series Chipset Family 6-port SATA Controller 1 [AHCI mode] [8086:8c02] \-1f.3 Intel Corporation 8 Series/C220 Series Chipset Family SMBus Controller [8086:8c22] 3. # superiotool -dV superiotool r6637 Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0x, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0x, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0x1c00, id=0x33c3 Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0x, id=0x Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0x, id=0x Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0x, id=0x Probing for ITE Super I/O (init=standard) at 0x25e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x25e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x25e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x25e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x25e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=standard) at 0x2e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x2e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x2e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x2e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0xc333, rev=0xf Probing for ITE Super I/O (init=standard) at 0x4e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x4e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x4e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x4e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... Failed. Returned data: id=0x, rev=0xf Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x164e... Failed. Returned data: port=0xff, port+1=0xff Probing for Nuvoton Super I/O at 0x164e... Failed. Returned data: chip_id=0x Probing for Nuvoton Super I/O (sid=0xfc) at 0x164e... Failed. Returned data: sid=0xff, id=0x, rev=0x00 Probing for Nuvoton Super I/O at 0x2e... Found Nuvoton NCT6776F (C) (id=0xc333) at 0x2e Register dump: idx 10 11 13 14 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24 25 26 27 28 2a 2b 2c 2d 2e 2f val ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff def ff ff 00 00 ff ff ff ff f0 78 00 00 ff ff c3 33 ff 00 64 00 MM 00 00 c0 00 81 00 00 MM LDN 0x00 (FDC) idx 30 60 61 70 74 f0 f1 f2 f4 f5 val ff ff ff ff ff ff ff ff ff ff def 01 03 f0 06 02 0e 00 ff 00 00 LDN 0x01 (Parallel Port) idx 30 60 61 70 74 f0 val ff ff ff ff ff ff def 01 03 78 07 04 3f LDN 0x02 (UART A) idx 30 60 61 70 f0 f2 val ff ff ff ff ff ff def 01 03 f8 04 00 00 LDN 0x03 (UART B, IR) idx 30 60 61 70 f0 f1 f2 val ff ff ff ff ff ff ff def 01 02 f8 03 00 00 00 LDN 0x05 (Keyboard Controller) idx 30 60 61 62 63 70 72 f0 val ff ff ff ff ff ff ff ff def 00 00 00 00 00 00 00 83 LDN 0x06 (CIR) idx 30 60 61 70 f0 f1 f2 f3 val ff ff ff ff ff ff ff ff def 00 00 00 00 08 09 32 00 LDN 0x07 (GPIO6, GPIO7, GPIO8, GPIO9) idx 30 e0 e1
[coreboot] Could not find a bounce buffer tested in minnowmax
I'm trying to investigate Coreboot and intel FSP in minnowmax board ,followed by "http://review.coreboot.org/gitweb?p=coreboot.git;a=commit;h=e6df041b8bf8e37debc0d6a871080b64eea7a372". But ,the uart log show :Payload being loaded below 1MiB without region being marked as RAM usable. Could not find a bounce buffer... Could not load payload The whole debug log is: POST: 0x4a romstage_main_continue status: 0 hob_list_ptr: 7bb2 FSP Status: 0x0 Baytrail Chip Variant: Bay Trail-I (ISG/embedded) MRC v0.90 1 channels of DDR3 @ 1066MHz POST: 0x4b POST: 0x4c POST: 0x4d CBMEM: root @ 7baff000 254 entries. POST: 0x4e POST: 0x4f Trying CBFS ramstage loader. CBFS: loading stage fallback/ramstage @ 0x10 (270384 bytes), entry @ 0x10 POST: 0x80 POST: 0x39 coreboot-4.0-6880-ga4a44a7 Tue Sep 16 23:46:12 PDT 2014 booting... POST: 0x40 clocks_per_usec: 1333 CBMEM: recovering 3/254 entries from root @ 7baff000 Moving GDT to 7bafc000...ok POST: 0x70 BS: BS_PRE_DEVICE times (us): entry 8070 run 1170 exit 0 POST: 0x71 CPUID: 00030673 Cores: 2 Revision ID: 0c Stepping: B3 msr(17) = 000c90040a38 msr(ce) = 04000a00 BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 12482 exit 0 POST: 0x72 Enumerating buses... enable_dev(Intel BayTrail SoC, 7) CPU_CLUSTER: 0 enabled enable_dev(Intel BayTrail SoC, 6) DOMAIN: enabled PCI: pci_scan_bus for bus 00 POST: 0x24 enable_dev(Intel BayTrail SoC, 2) PCI: 00:00.0 [8086/] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:02.0 [8086/0031] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:03.0: Disabling device: 03.0 Power management CAP offset 0x80. enable_dev(Intel BayTrail SoC, 2) PCI: 00:10.0: Disabling device: 10.0 Power management CAP offset 0x80. enable_dev(Intel BayTrail SoC, 2) PCI: 00:11.0: Disabling device: 11.0 Power management CAP offset 0x80. enable_dev(Intel BayTrail SoC, 2) PCI: 00:12.0 [8086/0f16] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:13.0 [8086/0f23] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:14.0 [8086/0f35] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:15.0 [8086/0f28] enabled PCI: 00:16.0 [8086/0f37] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:17.0: Disabling device: 17.0 Power management CAP offset 0x80. enable_dev(Intel BayTrail SoC, 2) PCI: 00:18.0 [8086/0f40] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:18.1: Disabling device: 18.1 Power management CAP offset 0x80. enable_dev(Intel BayTrail SoC, 2) PCI: 00:18.2: Disabling device: 18.2 Power management CAP offset 0x80. enable_dev(Intel BayTrail SoC, 2) PCI: 00:18.3: Disabling device: 18.3 Power management CAP offset 0x80. enable_dev(Intel BayTrail SoC, 2) PCI: 00:18.4: Disabling device: 18.4 Power management CAP offset 0x80. enable_dev(Intel BayTrail SoC, 2) PCI: 00:18.5: Disabling device: 18.5 Power management CAP offset 0x80. enable_dev(Intel BayTrail SoC, 2) PCI: 00:18.6 [8086/0f46] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:18.7 [8086/0f47] enabled enable_dev(Intel BayTrail SoC, 2) PCI: Static device PCI: 00:1a.0 not found, disabling it. enable_dev(Intel BayTrail SoC, 2) PCI: 00:1b.0: Disabling device: 1b.0 PCI: 00:1b.0 [8086/0f04] disabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:1c.0: Disabling device: 1c.0 Power management CAP offset 0xa0. PCI: 00:1c.0 subordinate bus PCI Express PCI: 00:1c.0 [8086/0f48] disabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:1c.1: Disabling device: 1c.1 Power management CAP offset 0xa0. enable_dev(Intel BayTrail SoC, 2) PCI: 00:1c.2 subordinate bus PCI Express PCI: 00:1c.2 [8086/0f4c] enabled enable_dev(Intel BayTrail SoC, 2) PCI: Static device PCI: 00:1c.3 not found, disabling it. enable_dev(Intel BayTrail SoC, 2) PCI: 00:1d.0: Disabling device: 1d.0 Power management CAP offset 0x70. enable_dev(Intel BayTrail SoC, 2) PCI: 00:1e.0 [8086/0f06] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:1e.1 [8086/0f08] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:1e.2 [8086/0f09] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:1e.3 [8086/0f0a] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:1e.4 [8086/0f0c] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:1e.5 [8086/0f0e] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:1f.0 [8086/0f1c] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:1f.3 [8086/0f12] enabled POST: 0x25 PCI: pci_scan_bus for bus 01 POST: 0x24 PCI: 01:00.0 [10ec/8168] enabled POST: 0x25 PCI: pci_scan_bus returning with max=001 POST: 0x55 PCI: pci_scan_bus returning with max=001 POST: 0x55 done BS: BS_DEV_ENUMERATE times (us): entry 0 run 329939 exit 0 POST: 0x73 found VGA at PCI: 00:02.0 Setting up VGA for PCI: 00:02.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... APIC: 00 missing read_resources Done reading resources. Setting resources... PCI: 00:02.0 10 <- [0x00f000 - 0x00f03f] size 0x0040 gran 0x16 mem P
[coreboot] Coreboot console_init() doesn't work on Rangeley board?
Hi, I am managing to replace BIOS with coreboot on a Rangeley evaluation board, but the serial console cannot display message after coreboot calls console_init() in src/southbridge/intel/fsp_rangeley/romstage.c. The console is connected to UART0 (0x3f8), which has been verified by BIOS. My configuration of coreboot includes: Mainboard: Intel->Mohon Peak CRB, which is the only choice for Rangeley FSP and microcode: downloaded from Intel FSP (https://downloadcenter.intel.com/Detail_Desc.aspx?agr=Y&DwnldID=23676). Payload: U-boot-x86 (should be irrelevant to payload, since coreboot just enters romstage) I have checked that the UART0 registers should have been initialized. The TX FIFO should also work: after out something to 0x3f8, LSR will change. I have also checked some other registers might related to UART. The UART_CONT (0:1f.0-0x80) is in the default state (0x0003). The GPIO Use Select is also in default state: GPIOS_13 is 0. Is there any other register can block the UART output? Besides, actually the coreboot finally run deeply. The post code changes from 47->66->67->69->...>72->73->77... and finally stop at 0xE2. But there's no console display so I cannot know where it stops. Regards, Qingxin -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] coreboot - coreinfo - make menuconfig - fails
Hi All, I wam trying to build coreboot with coreinfo as payload for qemu platform. I am getting the following error whe i try to launch make menuconfig from coreinfo directory. I have synced the latest code from git repository /home/harish/opensource/coreboot/payloads/coreinfo/util/kconfig/lxdialog/dialog.h:22:19: fatal error: fcntl.h: No such file or directory -bash: /home/harish/opensource/coreboot/payloads/coreinfo/util/kconfig/lxdialog/dialog.h:22:19:: No such file or directory harish@ubuntubc-OptiPlex-9010:~/opensource/coreboot/payloads/coreinfo$ #include harish@ubuntubc-OptiPlex-9010:~/opensource/coreboot/payloads/coreinfo$ ^ Any pointers on how to resolve this issue will be of great help Regards Harish -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
