Re: [coreboot] [GSoC 2016] ROM-O-Matic project

[Peter Stuge]

Hi guys,

(I have a server problem but am sortof recovering.)

ron minnich wrote:
> Do we have any record as to how uniform, e.g., the x220 experience
> has been?

This is an important question. It comes down to the mainboard of course.

Judging from the schematics and hardware in the wild there's not too
much variation with ThinkPads; the *only* significant variation in the
(admittedly very) old 60 generation is whether a mainboard has discrete
graphics or not, and even then that only matters for using the correct
option ROM.

There might be a bit more variation with newer generations because
they are more complex, but not too much.


//Peter

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Re: [coreboot] [GSoC 2016] ROM-O-Matic project

[Alexander Couzens]

On Wed, 09 Mar 2016 22:30:44 +
ron minnich  wrote:

> That's great to hear. So it sounds like rom o matic would be handy.
> 
> That said, w.r.t. features. I'm not big on features. coreboot is a
> chance to brick your laptop. That means
> rom o matic should never ever ever give you a bad coreboot image.

> What would be cool would be to have a program they can run that
> creates a string, and the either you paste
> that string into a form or it connects and pastes it in (but what
> about DDOS?) and you get back a URL for an image
> that is known to work. Could the coreboot board status repo be used to
> determine this?
> 
> I think the messy part is that just because you have, say, an "x220",
> doesn't mean coreboot works on it, because PCs
> are never the same, even given the same number. So you need a very
> long signature that can confirm the coreboot
> running on everyone else's "x220" will work on yours.
> 
> Do we have any record as to how uniform, e.g., the x220 experience has
> been? I know the chromebook uniformity is pretty good.
They are uniform, beside the case of the spi. Most x220 have a spi in a
SOIC8, but some have a WSON or mlp8 case.

I had problems with my x220 because I desolered the wson chip and
soldered a SOIC8 which wasn't quite supported by coreboot. I say the
"normal" coreboot user wouldn't do that ;). They only use a clip.

Best,
lynxis
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[coreboot] tpm api merge

[Alexander Couzens]

Hi,

I'm looking at a huge tpm merge commit. +625, -748

So the question how can we merge this? As long we don't have further
testing, it's hard to decide. We won't catch all bugs. May be
chromeos have a tpm testing?

And also reorganize the commit into smaller ones are very hard and I
think it's not the effort worthy. Because merging two apis into one
is a big thing.

The only other way I can imagine merge 
I don't know how easy it is, having 3 apis lying in the tree.
The 2 "old" apis and the new merged one. Extending the new api until
it's working.

Can we freeze the tpm apis for now? It would give zaolin more time to
fix the problems and give the reviewer also more time to look over?!

Best,
lynxis

https://review.coreboot.org/#/c/10542/
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Re: [coreboot] [GSoC 2016] ROM-O-Matic project

[ron minnich]

That's great to hear. So it sounds like rom o matic would be handy.

That said, w.r.t. features. I'm not big on features. coreboot is a chance
to brick your laptop. That means
rom o matic should never ever ever give you a bad coreboot image.

What would be cool would be to have a program they can run that creates a
string, and the either you paste
that string into a form or it connects and pastes it in (but what about
DDOS?) and you get back a URL for an image
that is known to work. Could the coreboot board status repo be used to
determine this?

I think the messy part is that just because you have, say, an "x220",
doesn't mean coreboot works on it, because PCs
are never the same, even given the same number. So you need a very long
signature that can confirm the coreboot
running on everyone else's "x220" will work on yours.

Do we have any record as to how uniform, e.g., the x220 experience has
been? I know the chromebook uniformity is pretty good.

ron

On Wed, Mar 9, 2016 at 2:07 PM Alexander Couzens  wrote:

> On Wed, 09 Mar 2016 20:57:23 +
> ron minnich  wrote:
>
> > I suspect you know far more about writing such a tool than I ever
> > will, but far less about coreboot than you need to know. Your first
> > step should be to get it, build it, and boot it in qemu; bonus points
> > for doing it on real
>
> I know a lot people who don't know or have problems compiling
> coreboot on their own or they don't want to spent hours to compiling the
> toolchain + coreboot. For these people rom-o-matic is a nice thing.
>
> German hacker culture likes coreboot a lot. Last coreboot user
> group meeting a journalist showed up. Someone spent her a x60 and she
> would like to have coreboot on it. But after disassembling the hardware
> down to the board itself, it turns out, she already got coreboot. I
> never looked at the x60 bios booting up :).
>
> There are also the cryptoparty people, they also support coreboot.
> zaolin is doing installation partys at his hackerspace, too. And may
> others do the same.
> --
> Alexander Couzens
>
> mail: lyn...@fe80.eu
> jabber: lyn...@fe80.eu
> mobile: +4915123277221
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>
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Re: [coreboot] [GSoC 2016] ROM-O-Matic project

[Alexander Couzens]

On Wed, 09 Mar 2016 20:57:23 +
ron minnich  wrote:

> I suspect you know far more about writing such a tool than I ever
> will, but far less about coreboot than you need to know. Your first
> step should be to get it, build it, and boot it in qemu; bonus points
> for doing it on real

I know a lot people who don't know or have problems compiling
coreboot on their own or they don't want to spent hours to compiling the
toolchain + coreboot. For these people rom-o-matic is a nice thing.

German hacker culture likes coreboot a lot. Last coreboot user
group meeting a journalist showed up. Someone spent her a x60 and she
would like to have coreboot on it. But after disassembling the hardware
down to the board itself, it turns out, she already got coreboot. I
never looked at the x60 bios booting up :).

There are also the cryptoparty people, they also support coreboot.
zaolin is doing installation partys at his hackerspace, too. And may
others do the same.
-- 
Alexander Couzens

mail: lyn...@fe80.eu
jabber: lyn...@fe80.eu
mobile: +4915123277221
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Re: [coreboot] [GSoC 2016] ROM-O-Matic project

[ron minnich]

On Wed, Mar 9, 2016 at 4:16 AM Yurii Shevtsov  wrote:

> I looked at sites you mentioned. I haven't any configuration feature on
> johnlewis.ie Instead it provides an instruction for running special shell
> script. But I much more liked original Rom-o-matic. I want do develop same
> thing, but with fancier design, if you mind) I have more questions:
>
> How important this project for coreboot community is?
>

well, that's a tough question. Back in 2000 when we first did it, it was
very important. At this point, coreboot is mostly two user communities:
people who use it and don't know and don't care (chromebooks); and people
who are dedicated hackers and know the insides so well they don't need
rom-o-matic. Those who don't know anything and don't care they're using
coreboot probably outnumber knowledgable people by about 10,000 to 1 at
least [based on the 10m+ systems shipped at this point with coreboot, and
my guess that the coreboot hacker community is unlikely to be as many as
1000 people).

The number of people who don't know anything and can use a rom-o-matic is
probably numbered in single digits, because even to use rom-o-matic you
have to be knowledgable enough that you might as well build your own
coreboot. You certainly have to have a path out if something goes wrong,
and at that point you are cracking open your laptop. A failed coreboot
install is not like a failed OS install. It's more like destroying your
mainboard.

I hate to be discouraging but my guess is at present that what john lewis
is doing is probably as much as is needed.


Do I have to fix some bugs or make any other sort of contribution, before
> submitting my proposal?
>

You should show that you know how to build and use coreboot from scratch.
It makes no sense to talk about rom-o-matic otherwise.


> Do you have a proposal template or some special requirments for it?
> What do you think about nodejs, as a backend?
>


I suspect you know far more about writing such a tool than I ever will, but
far less about coreboot than you need to know. Your first step should be to
get it, build it, and boot it in qemu; bonus points for doing it on real
hardware.

I think the choice of node.js is not nearly as important as ensuing you
give people images that won't brick their machine.

ron
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Re: [coreboot] Memtest86 SPD/DMI popups broken

[Ben Gardner]

Yes, lets revert it.
The popups work again after reverting commit 03e81e1
(https://review.coreboot.org/#/c/13900).

The other one (https://review.coreboot.org/#/c/13901/) doesn't make a
difference on my board.
Probably because I have VGA. I suppose that one can stay.

On Wed, Mar 9, 2016 at 1:57 PM, Martin Roth  wrote:
> Do you think we should revert those patches until we can get them fixed?
>
> On Wed, Mar 9, 2016 at 11:56 AM, Ben Gardner  wrote:
>> FYI -
>>
>> I just tried memtest86 with the popup patches that were added to coreboot.
>> I'm seeing issues with clearing the background before drawing the SPD popup.
>>
>> When I hit "c", the "settings" popup shows on both serial and VGA
>> properly. VGA has a black background and serial clears the area.
>>
>> When I select "display SPD data", it doesn't clear the background
>> before drawing the data and doesn't restore what was under when the
>> popup is lowered.
>>
>> Below is the output from the serial port when displaying the SPD data.
>> View in a fixed width font.
>>
>> -
>> Memtest86+ 5.01 coreboot 001| Intel(R) Atom(TM) CPU  E3845  @ 1.91GHz
>> CLK: 1917 MHz  (X64 Mode)   | Pass  0%
>> L1 CSPD Data: Slot 095 MB/s | Test 50% ###
>> L2 Cache: 1024K  22030 MB/s | Test #2  [Address test, own address Parallel]
>> L3 Cac92:13N0be03 04 19 02 02 03s11n01 0820a 001fe600  1965M of 4013M
>> Memory69:78069M3c 69811M18s81 20t08r3c 3ca01r40s83 05   | Time:   0:00:01
>> --00-00-00-00-00-00-00-00-00-84-00-00-00-00-00-00-
>> Core#:00 00M00 00s00l00)00|00C00 00m00 00R0f:01102M00 (DDR3-833) - BCLK:  83
>> State:00 00 00 00 00 00 00 00 00 00 00 00 00 00s00C00 9-9-9-10 @ 64-bit Mode
>> Cores:00100 00 00 00 00 00 00 00 00 00 00 00 00 00 000Errors:  0
>> --00-00 00 00 00 00 00 00 00 00 00 00 00 
>> 00-00-00-
>>   00 00 00 00 00 80 2c 00 00 00 00 00 00 00 c4 b1
>> Memory34P4b 54 46 32 35 36 36 34 48 5a 2d 31 47 36 45
>> --31-45 31 80 2c 00 00 00 00 00 00 00 00 00 00 00
>>   - Sl00 00 00 00 00 00 00 00 00 00 00 00 00 00600ZffG6E1E
>>   - Sl57 50 4e 3a 33 34 32 35 36 20 52 45 56 3a641ZffG6E1E
>>   32 30 34 38 20 4d 42 59 54 45 ff ff ff ff ff ff
>>   ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
>>   ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
>>   ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
>>
>>
>>
>> Wabtec CPU-1900
>> (ESC)exit  (c)configuration  (SP)scroll_lock  (CR)scroll_unlock
>> -
>>
>> And what is shown after returning to the settings menu.
>>
>> -
>> Memtest86+ 5.01 coreboot 001| Intel(R) Atom(TM) CPU  E3845  @ 1.91GHz
>> CLK: 1917 MHz  (X64 Mode)   | Pass  0%
>> L1 CSPD Data: Slot 195 MB/s | Test 88% ##
>> L2 CaNo valid DMI Memory Devices info founding inversions, 1s & 0s Parallel]
>> L3 Cac92:13N0be03 04 19 02 02 03s11n01 0890a 006fe400  2048M of 4013M
>> Memory69:78069M3c 69811M18s81 20t08r3c 3cf01f40f83 05   | Time:   0:05:38
>> --00-00-00-00-00-00-00-00-00-84-00-00-00-00-00-00-
>> Core#:00 00M00 00s00l00)00|00C00 00m00 00R0f:01102M00 (DDR3-833) - BCLK:  83
>> State:00 00  00s00C00 9-9-9-10 @ 64-bit Mode
>> Cores:00100  Settings:   00 00 000Errors:  0
>> --00-00  
>> 00-00-00-
>>   00 00  (1) Test Selection  00 c4 b1
>> Memory34P4b  (2) Address Range   47 36 45
>> --31-45  (3) Error Report Mode   00 00 00
>>   - Sl00 00  (4) Core Selection  00600ZffG6E1E
>>   - Sl57 50  (5) Refresh Screen  3a641ZffG6E1E
>>   32 30  (6) Display DMI Dataff ff ff
>>   ff ff  (7) Display SPD Dataff ff ff
>>   ff ff  ff ff ff
>>   ff ff  (0) Continueff ff ff
>>
>>
>>
>> Wabtec CPU-1900
>> (ESC)exit  (c)configuration  (SP)scroll_lock  (CR)scroll_unlock
>> -
>>
>> Not sure what is going on here.
>> I don't have this issue without the popup patches.
>> I'll look into it a bit more.
>>
>> Ben
>>
>> --
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>> https://www.coreboot.org/mailman/listinfo/coreboot

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Re: [coreboot] Memtest86 SPD/DMI popups broken

[Martin Roth]

Do you think we should revert those patches until we can get them fixed?

On Wed, Mar 9, 2016 at 11:56 AM, Ben Gardner  wrote:
> FYI -
>
> I just tried memtest86 with the popup patches that were added to coreboot.
> I'm seeing issues with clearing the background before drawing the SPD popup.
>
> When I hit "c", the "settings" popup shows on both serial and VGA
> properly. VGA has a black background and serial clears the area.
>
> When I select "display SPD data", it doesn't clear the background
> before drawing the data and doesn't restore what was under when the
> popup is lowered.
>
> Below is the output from the serial port when displaying the SPD data.
> View in a fixed width font.
>
> -
> Memtest86+ 5.01 coreboot 001| Intel(R) Atom(TM) CPU  E3845  @ 1.91GHz
> CLK: 1917 MHz  (X64 Mode)   | Pass  0%
> L1 CSPD Data: Slot 095 MB/s | Test 50% ###
> L2 Cache: 1024K  22030 MB/s | Test #2  [Address test, own address Parallel]
> L3 Cac92:13N0be03 04 19 02 02 03s11n01 0820a 001fe600  1965M of 4013M
> Memory69:78069M3c 69811M18s81 20t08r3c 3ca01r40s83 05   | Time:   0:00:01
> --00-00-00-00-00-00-00-00-00-84-00-00-00-00-00-00-
> Core#:00 00M00 00s00l00)00|00C00 00m00 00R0f:01102M00 (DDR3-833) - BCLK:  83
> State:00 00 00 00 00 00 00 00 00 00 00 00 00 00s00C00 9-9-9-10 @ 64-bit Mode
> Cores:00100 00 00 00 00 00 00 00 00 00 00 00 00 00 000Errors:  0
> --00-00 00 00 00 00 00 00 00 00 00 00 00 00-00-00-
>   00 00 00 00 00 80 2c 00 00 00 00 00 00 00 c4 b1
> Memory34P4b 54 46 32 35 36 36 34 48 5a 2d 31 47 36 45
> --31-45 31 80 2c 00 00 00 00 00 00 00 00 00 00 00
>   - Sl00 00 00 00 00 00 00 00 00 00 00 00 00 00600ZffG6E1E
>   - Sl57 50 4e 3a 33 34 32 35 36 20 52 45 56 3a641ZffG6E1E
>   32 30 34 38 20 4d 42 59 54 45 ff ff ff ff ff ff
>   ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
>   ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
>   ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
>
>
>
> Wabtec CPU-1900
> (ESC)exit  (c)configuration  (SP)scroll_lock  (CR)scroll_unlock
> -
>
> And what is shown after returning to the settings menu.
>
> -
> Memtest86+ 5.01 coreboot 001| Intel(R) Atom(TM) CPU  E3845  @ 1.91GHz
> CLK: 1917 MHz  (X64 Mode)   | Pass  0%
> L1 CSPD Data: Slot 195 MB/s | Test 88% ##
> L2 CaNo valid DMI Memory Devices info founding inversions, 1s & 0s Parallel]
> L3 Cac92:13N0be03 04 19 02 02 03s11n01 0890a 006fe400  2048M of 4013M
> Memory69:78069M3c 69811M18s81 20t08r3c 3cf01f40f83 05   | Time:   0:05:38
> --00-00-00-00-00-00-00-00-00-84-00-00-00-00-00-00-
> Core#:00 00M00 00s00l00)00|00C00 00m00 00R0f:01102M00 (DDR3-833) - BCLK:  83
> State:00 00  00s00C00 9-9-9-10 @ 64-bit Mode
> Cores:00100  Settings:   00 00 000Errors:  0
> --00-00  00-00-00-
>   00 00  (1) Test Selection  00 c4 b1
> Memory34P4b  (2) Address Range   47 36 45
> --31-45  (3) Error Report Mode   00 00 00
>   - Sl00 00  (4) Core Selection  00600ZffG6E1E
>   - Sl57 50  (5) Refresh Screen  3a641ZffG6E1E
>   32 30  (6) Display DMI Dataff ff ff
>   ff ff  (7) Display SPD Dataff ff ff
>   ff ff  ff ff ff
>   ff ff  (0) Continueff ff ff
>
>
>
> Wabtec CPU-1900
> (ESC)exit  (c)configuration  (SP)scroll_lock  (CR)scroll_unlock
> -
>
> Not sure what is going on here.
> I don't have this issue without the popup patches.
> I'll look into it a bit more.
>
> Ben
>
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> https://www.coreboot.org/mailman/listinfo/coreboot

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[coreboot] Memtest86 SPD/DMI popups broken

[Ben Gardner]

FYI -

I just tried memtest86 with the popup patches that were added to coreboot.
I'm seeing issues with clearing the background before drawing the SPD popup.

When I hit "c", the "settings" popup shows on both serial and VGA
properly. VGA has a black background and serial clears the area.

When I select "display SPD data", it doesn't clear the background
before drawing the data and doesn't restore what was under when the
popup is lowered.

Below is the output from the serial port when displaying the SPD data.
View in a fixed width font.

-
Memtest86+ 5.01 coreboot 001| Intel(R) Atom(TM) CPU  E3845  @ 1.91GHz
CLK: 1917 MHz  (X64 Mode)   | Pass  0%
L1 CSPD Data: Slot 095 MB/s | Test 50% ###
L2 Cache: 1024K  22030 MB/s | Test #2  [Address test, own address Parallel]
L3 Cac92:13N0be03 04 19 02 02 03s11n01 0820a 001fe600  1965M of 4013M
Memory69:78069M3c 69811M18s81 20t08r3c 3ca01r40s83 05   | Time:   0:00:01
--00-00-00-00-00-00-00-00-00-84-00-00-00-00-00-00-
Core#:00 00M00 00s00l00)00|00C00 00m00 00R0f:01102M00 (DDR3-833) - BCLK:  83
State:00 00 00 00 00 00 00 00 00 00 00 00 00 00s00C00 9-9-9-10 @ 64-bit Mode
Cores:00100 00 00 00 00 00 00 00 00 00 00 00 00 00 000Errors:  0
--00-00 00 00 00 00 00 00 00 00 00 00 00 00-00-00-
  00 00 00 00 00 80 2c 00 00 00 00 00 00 00 c4 b1
Memory34P4b 54 46 32 35 36 36 34 48 5a 2d 31 47 36 45
--31-45 31 80 2c 00 00 00 00 00 00 00 00 00 00 00
  - Sl00 00 00 00 00 00 00 00 00 00 00 00 00 00600ZffG6E1E
  - Sl57 50 4e 3a 33 34 32 35 36 20 52 45 56 3a641ZffG6E1E
  32 30 34 38 20 4d 42 59 54 45 ff ff ff ff ff ff
  ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
  ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
  ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff



Wabtec CPU-1900
(ESC)exit  (c)configuration  (SP)scroll_lock  (CR)scroll_unlock
-

And what is shown after returning to the settings menu.

-
Memtest86+ 5.01 coreboot 001| Intel(R) Atom(TM) CPU  E3845  @ 1.91GHz
CLK: 1917 MHz  (X64 Mode)   | Pass  0%
L1 CSPD Data: Slot 195 MB/s | Test 88% ##
L2 CaNo valid DMI Memory Devices info founding inversions, 1s & 0s Parallel]
L3 Cac92:13N0be03 04 19 02 02 03s11n01 0890a 006fe400  2048M of 4013M
Memory69:78069M3c 69811M18s81 20t08r3c 3cf01f40f83 05   | Time:   0:05:38
--00-00-00-00-00-00-00-00-00-84-00-00-00-00-00-00-
Core#:00 00M00 00s00l00)00|00C00 00m00 00R0f:01102M00 (DDR3-833) - BCLK:  83
State:00 00  00s00C00 9-9-9-10 @ 64-bit Mode
Cores:00100  Settings:   00 00 000Errors:  0
--00-00  00-00-00-
  00 00  (1) Test Selection  00 c4 b1
Memory34P4b  (2) Address Range   47 36 45
--31-45  (3) Error Report Mode   00 00 00
  - Sl00 00  (4) Core Selection  00600ZffG6E1E
  - Sl57 50  (5) Refresh Screen  3a641ZffG6E1E
  32 30  (6) Display DMI Dataff ff ff
  ff ff  (7) Display SPD Dataff ff ff
  ff ff  ff ff ff
  ff ff  (0) Continueff ff ff



Wabtec CPU-1900
(ESC)exit  (c)configuration  (SP)scroll_lock  (CR)scroll_unlock
-

Not sure what is going on here.
I don't have this issue without the popup patches.
I'll look into it a bit more.

Ben

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Re: [coreboot] Is anyone working on FMAP support in SeaBIOS?

[Ben Gardner]

It turned out to be a lot easier than I expected.

A patch can be found here:
https://www.coreboot.org/pipermail/seabios/2016-March/010551.html


On Wed, Mar 9, 2016 at 10:40 AM, Ben Gardner  wrote:
> Hi All,
>
> Before I get too far investigating adding FMAP support to SeaBIOS, I
> just wanted to check if anyone else is working on this or has done
> this.
>
> The goal is to have SeaBIOS look in an alternate CBFS for bootable img/* 
> items.
>
> The plan is to have SeaBIOS find the FMAP location via the
> BOOT_MEDIA_PARAMS (0x30) CB tag and then scan all available CBFS in
> cbfs_payload_setup().
>
> Thanks,
> Ben

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[coreboot] Is anyone working on FMAP support in SeaBIOS?

[Ben Gardner]

Hi All,

Before I get too far investigating adding FMAP support to SeaBIOS, I
just wanted to check if anyone else is working on this or has done
this.

The goal is to have SeaBIOS look in an alternate CBFS for bootable img/* items.

The plan is to have SeaBIOS find the FMAP location via the
BOOT_MEDIA_PARAMS (0x30) CB tag and then scan all available CBFS in
cbfs_payload_setup().

Thanks,
Ben

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Re: [coreboot] [GSoC 2016] ROM-O-Matic project

[Yurii Shevtsov]

I looked at sites you mentioned. I haven't any configuration feature on
johnlewis.ie Instead it provides an instruction for running special shell
script. But I much more liked original Rom-o-matic. I want do develop same
thing, but with fancier design, if you mind) I have more questions:

How important this project for coreboot community is?
Do I have to fix some bugs or make any other sort of contribution, before
submitting my proposal?
Do you have a proposal template or some special requirments for it?
What do you think about nodejs, as a backend?

Thanks in advance!

2016-03-09 6:24 GMT+02:00 ron minnich :

> yeah, we had something like this in the linuxbios days. I think you don't
> want to build it on demand, but rather have a bunch of pre-built images
> that are known good.
>
> Really, look at johnlewis.ie, that's the best thing I've seen. Have you
> also seen the original Rom-o-matic from the etherboot (now gpxe or ipxe)
> project?
>
> ron
>
> On Tue, Mar 8, 2016 at 7:35 PM Yurii Shevtsov  wrote:
>
>> Hello) I want to be a GSoC 2016 student. I really liked the idea of
>> ROM-O-Matic project. Also it's a nice name. So, as I understood, the end
>> user should get a website with a ROM configurator and a big 'Download'
>> button, right?
>>
>> I'm student of Odessa polytechnic university, computer science. I have a
>> good as for student experience in system and web programming
>> --
>> coreboot mailing list: coreboot@coreboot.org
>> https://www.coreboot.org/mailman/listinfo/coreboot
>
>
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https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Fwd: Aspirant for GSOC 2016 with coreboot for ARM64 qemu port

[Furquan Shaikh]

IIRC, last I checked a while back, qemu did not have support for EL3 i.e.
it started booting directly in EL2 (need to onfirm this). But, I think a
good starting point would be to identify the current status of qemu arm64
support and see if qemu starts booting in EL3. All the coreboot arm64
infrastructure is currently based on the fact that all coreboot stages are
running in EL3. If that assumption is broken by qemu, then we would need to
make appropriate changes in coreboot arm64 infrastructure.

Additionally, it would be good to understand how to work with qemu i.e.
booting Linux on qemu-arm64, debugging with qemu, etc.

Hope that helps.

- furquan

On Tue, Mar 8, 2016 at 7:32 PM, Stefan Reinauer <
stefan.reina...@coreboot.org> wrote:

> I suggest you start looking at the progress made last year and try to
> reproduce it:
>
> http://blogs.coreboot.org/blog/author/namang/
>
>
> On 03/08/2016 06:35 PM, Saket Sinha wrote:
>
>> Hi Stephan,
>>
>> Any update on this.
>>
>>
>> Regards,
>> Saket Sinha
>>
>>
>> On Mon, Mar 7, 2016 at 10:47 AM, Saket Sinha 
>> wrote:
>>
>>> Hi Stefan,
>>>
>>> Thanks for the reply.
>>>
>>> I am interested in working with the ARM64 support in coreboot which
>>> was developed on Qemu last year. I want to carry forward the project
>>> and bring the support over real ARM64 board(I would be having Rasberry
>>> PI3 available with me pretty soon) .
>>>
>>> Let me know how to get started on the same.
>>>
>>>
>>> Regards,
>>> Saket Sinha
>>>
>>>
>>> On Mon, Mar 7, 2016 at 4:10 AM, Stefan Reinauer
>>>  wrote:
>>>
 Hi Saket!

 Welcome to coreboot!

 Please check out our GSoC page at https://www.coreboot.org/GSoC and
 have a
 look at our three sub projects this year: coreboot, flashrom and
 SerialICE.
 If you have specific questions, please don't hesitate to ask.

 Stefan


 On 02/29/2016 11:38 AM, Saket Sinha wrote:

> Hi,
>
> Congratulations to the coreboot team for selection in GSOC 2016.
>
> I am looking forward to participate in GSOC 2016 with coreboot for
> ARM64 qemu port.
>
> I request you to guide me as where to start with to prepare for this
> project.
>
> Regards,
> Saket Sinha
>
>
>
> -- Forwarded message --
> From: Saket Sinha 
> Date: Fri, Feb 12, 2016 at 10:24 AM
> Subject: Aspirant for GSOC 2016 with coreboot for ARM64 qemu port
> To: adur...@chromium.org, coreboot@coreboot.org
> Cc: Patrick Georgi 
>
>
> Hi,
>
> I think this is early for this but I am looking forward to participate
> in GSOC 2016 with coreboot for ARM64 qemu port.
>
> This is to discuss the idea further.
>
> I guess the project was a part of last year GSOC as well so we already
> have some base-work to start with.
>
> I request you to guide me as where to start with to prepare for this
> project.
>
>
> Regards,
> Saket Sinha
>
>
 --
 coreboot mailing list: coreboot@coreboot.org
 https://www.coreboot.org/mailman/listinfo/coreboot

>>>
>
> --
> coreboot mailing list: coreboot@coreboot.org
> https://www.coreboot.org/mailman/listinfo/coreboot
>
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