Re: [coreboot] Coreboot image and seabios payload with debug symbols

2016-05-10 Thread Mayuri Tendulkar 
Hi Zoran

Please find responses:

[1] When you do refer to "Intel system debugger", do you refer to INTEL ITP2 
debugger, with Blue Box XDP 60 pin HW connector 
(http://m.eet.com/media/1073715/JTAG_101_fig5.jpg)?

This is Intel® ITP-XDP3. 
https://software.intel.com/sites/default/files/managed/45/19/10-jtag-debugger.pdf


[2] For which CPU/SoC/platform you would like to use [1]? – This I am currently 
using for Minnowboard Turbot (E3826 dual core)

[3] Seems that you did copy some debug excerpt from some INTEL document... I 
guess, this one is public one. Could you, please, attach this (if?) public 
document to this @ thread for our review, or either pass to us www pointer to 
this document?

This can be found from Intel system debugger use guide.
https://software.intel.com/en-us/node/592929- check section debugging basics

Regards
Mayuri


From: Zoran Stojsavljevic [mailto:zoran.stojsavlje...@gmail.com]
Sent: 10 May 2016 23:15
To: Mayuri Tendulkar 
Cc: coreboot@coreboot.org
Subject: Re: [coreboot] Coreboot image and seabios payload with debug symbols

Hello Mayuri,

Few questions, may I?

[1] When you do refer to "Intel system debugger", do you refer to INTEL ITP2 
debugger, with Blue Box XDP 60 pin HW connector 
(http://m.eet.com/media/1073715/JTAG_101_fig5.jpg)?

[2] For which CPU/SoC/platform you would like to use [1]?

[3] Seems that you did copy some debug excerpt from some INTEL document... I 
guess, this one is public one. Could you, please, attach this (if?) public 
document to this @ thread for our review, or either pass to us www pointer to 
this document?

Thank you,
Zoran
[https://ssl.gstatic.com/ui/v1/icons/mail/images/cleardot.gif]

On Tue, May 10, 2016 at 8:22 AM, Mayuri Tendulkar 
mailto:mayuri.tendul...@aricent.com>> wrote:
Hi

I want to use Intel system debugger to do coreboot source level debugging.

So I need below. Can you please help me in this?
To debug your software using source code you need to load debug information 
that is used to map the program in target memory to the original source files. 
To do this the debugger needs the following:

  *   A program loaded in target memory that has been compiled with debug 
information
  *   The load address of the program in target memory
  *   The program binary file (executable file)
  *   Debug information file for the program binary (also referred to as 
"symbols")
  *   Original program source code
Regards
Mayuri
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[coreboot] ASUS KFSN4-DRE (K8) Automated Test Failure [master]

2016-05-10 Thread Raptor Engineering Automated Coreboot Test Stand 
The ASUS KFSN4-DRE (K8) fails verification for branch master as of commit 
a486af46b2a5d49b05bfc89a876b5c800eadbe69

The following tests failed:
BOOT_FAILURE

Commits since last successful test:
a486af4 soc/qualcomm/ipq40xx: Add coreboot Table entry for serial console
4df1e0a google/gale: Enable Giga Device SPI flash support
8ce14a7 soc/qualcomm/ipq40xx: Return NULL for cbmem_top if DRAM is not 
initialized
9f1e0c5 google/gale: set the correct GPIOs for recovery and dev.
10c3749 soc/qualcomm/ipq40xx: Update memory map to align to ipq40xx

<1 commits skipped>

fa92768 soc/qualcomm/ipq40xx: Add config option for SBL utils path
3bbd901 google/gale: Initial commit for Gale board support
dc17d2d soc/qualcomm/ipq40xx: Update the list of MBNs needed for this SoC
a6935c2 soc/qualcomm/ipq40xx: Initial commit for IPQ40xx SoC support
c84e2fe 3rdparty/blobs: add more Qualcomm stubs

See attached log for details

This message was automatically generated from Raptor Engineering's ASUS 
KFSN4-DRE (K8) test stand
Want to test on your own equipment?  Check out 
https://www.raptorengineeringinc.com/content/REACTS/intro.html

Raptor Engineering also offers coreboot consulting services!  Please visit 
https://www.raptorengineeringinc.com for more information

Please contact Timothy Pearson at Raptor Engineering 
 regarding any issues stemming from this 
notification


1462911850-2-automaster.log.bz2
Description: Binary data
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[coreboot] New Defects reported by Coverity Scan for coreboot

2016-05-10 Thread scan-admin 

Hi,

Please find the latest report on new defect(s) introduced to coreboot found 
with Coverity Scan.

10 new defect(s) introduced to coreboot found with Coverity Scan.
120 defect(s), reported by Coverity Scan earlier, were marked fixed in the 
recent build analyzed by Coverity Scan.

New defect(s) Reported-by: Coverity Scan
Showing 10 of 10 defect(s)


** CID 1355175:  Control flow issues  (STRAY_SEMICOLON)
/src/soc/intel/apollolake/lpc.c: 61 in lpc_init()



*** CID 1355175:  Control flow issues  (STRAY_SEMICOLON)
/src/soc/intel/apollolake/lpc.c: 61 in lpc_init()
55  }
56 
57  scnt = pci_read_config8(dev, REG_SERIRQ_CTL);
58  scnt &= ~(SCNT_EN | SCNT_MODE);
59  if (cfg->serirq_mode == SERIRQ_QUIET)
60  scnt |= SCNT_EN;
>>> CID 1355175:  Control flow issues  (STRAY_SEMICOLON)
>>> An "if" statement with no "then" or "else" is suspicious.
61  else if (cfg->serirq_mode == SERIRQ_CONTINUOUS);
62  scnt |= SCNT_EN | SCNT_MODE;
63  pci_write_config8(dev, REG_SERIRQ_CTL, scnt);
64 }
65 
66 static void soc_lpc_add_io_resources(device_t dev)

** CID 1355174:  Memory - corruptions  (OVERRUN)
/3rdparty/arm-trusted-firmware/plat/rockchip/rk3399/drivers/pmu/pmu.c: 184 in 
cores_pwr_domain_on()



*** CID 1355174:  Memory - corruptions  (OVERRUN)
/3rdparty/arm-trusted-firmware/plat/rockchip/rk3399/drivers/pmu/pmu.c: 184 in 
cores_pwr_domain_on()
178 cpus_power_domain_off(cpu, core_pwr_pd);
179 }
180 }
181 
182 static int cores_pwr_domain_on(unsigned long mpidr, uint64_t entrypoint)
183 {
>>> CID 1355174:  Memory - corruptions  (OVERRUN)
>>> Assigning: "cpu_id" = "plat_core_pos_by_mpidr(mpidr)". The value of 
>>> "cpu_id" is now -1.
184 uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr);
185 
186 assert(cpuson_flags[cpu_id] == 0);
187 cpuson_flags[cpu_id] = PMU_CPU_HOTPLUG;
188 cpuson_entry_point[cpu_id] = entrypoint;
189 dsb();

** CID 1355173:  Memory - illegal accesses  (OVERRUN)
/3rdparty/arm-trusted-firmware/plat/rockchip/rk3399/drivers/pmu/pmu.c: 186 in 
cores_pwr_domain_on()



*** CID 1355173:  Memory - illegal accesses  (OVERRUN)
/3rdparty/arm-trusted-firmware/plat/rockchip/rk3399/drivers/pmu/pmu.c: 186 in 
cores_pwr_domain_on()
180 }
181 
182 static int cores_pwr_domain_on(unsigned long mpidr, uint64_t entrypoint)
183 {
184 uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr);
185 
>>> CID 1355173:  Memory - illegal accesses  (OVERRUN)
>>> Overrunning array "cpuson_flags" of 6 4-byte elements at element index 
>>> 4294967295 (byte offset 17179869180) using index "cpu_id" (which evaluates 
>>> to 4294967295).
186 assert(cpuson_flags[cpu_id] == 0);
187 cpuson_flags[cpu_id] = PMU_CPU_HOTPLUG;
188 cpuson_entry_point[cpu_id] = entrypoint;
189 dsb();
190 
191 cpus_power_domain_on(cpu_id);

** CID 1355172:  Memory - corruptions  (OVERRUN)
/3rdparty/arm-trusted-firmware/plat/rockchip/rk3399/drivers/pmu/pmu.c: 188 in 
cores_pwr_domain_on()



*** CID 1355172:  Memory - corruptions  (OVERRUN)
/3rdparty/arm-trusted-firmware/plat/rockchip/rk3399/drivers/pmu/pmu.c: 188 in 
cores_pwr_domain_on()
182 static int cores_pwr_domain_on(unsigned long mpidr, uint64_t entrypoint)
183 {
184 uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr);
185 
186 assert(cpuson_flags[cpu_id] == 0);
187 cpuson_flags[cpu_id] = PMU_CPU_HOTPLUG;
>>> CID 1355172:  Memory - corruptions  (OVERRUN)
>>> Overrunning array "cpuson_entry_point" of 6 8-byte elements at element 
>>> index 4294967295 (byte offset 34359738360) using index "cpu_id" (which 
>>> evaluates to 4294967295).
188 cpuson_entry_point[cpu_id] = entrypoint;
189 dsb();
190 
191 cpus_power_domain_on(cpu_id);
192 
193 return 0;

** CID 1355171:  Integer handling issues  (NO_EFFECT)
/src/soc/rockchip/common/spi.c: 126 in rockchip_spi_init()



*** CID 1355171:  Integer handling issues  (NO_EFFECT)
/src/soc/rockchip/common/spi.c: 126 in rockchip_spi_init()
120 assert(clk_div * hz == SPI_SRCCLK_HZ && !(clk_div & 1));
121 write32(®s->baudr, clk_div);
122 }
123 
124 void rockchip_spi_init(unsigned int bus, unsigned int speed_hz)
125 {
>>> CID 1355171:  Inte

Re: [coreboot] Coreboot image and seabios payload with debug symbols

2016-05-10 Thread Zoran Stojsavljevic 
Hello Mayuri,

Few questions, may I?

[1] When you do refer to *"**Intel system debugger",* do you refer to INTEL
ITP2 debugger, with Blue Box XDP 60 pin HW connector (
http://m.eet.com/media/1073715/JTAG_101_fig5.jpg)?

[2] For which CPU/SoC/platform you would like to use [1]?

[3] Seems that you did copy some debug excerpt from some INTEL document...
I guess, this one is public one. Could you, please, attach this (if?)
public document to this @ thread for our review, or either pass to us www
pointer to this document?

Thank you,
Zoran

On Tue, May 10, 2016 at 8:22 AM, Mayuri Tendulkar <
mayuri.tendul...@aricent.com> wrote:

> Hi
>
>
>
> I want to use Intel system debugger to do coreboot source level debugging.
>
>
>
> So I need below. Can you please help me in this?
>
> To debug your software using source code you need to load debug
> information that is used to map the program in target memory to the
> original source files. To do this the debugger needs the following:
>
>- A program loaded in target memory that has been compiled with debug
>information
>- The load address of the program in target memory
>- The program binary file (executable file)
>- Debug information file for the program binary (also referred to as
>"symbols")
>- Original program source code
>
> Regards
>
> Mayuri
> "DISCLAIMER: This message is proprietary to Aricent and is intended solely
> for the use of the individual to whom it is addressed. It may contain
> privileged or confidential information and should not be circulated or used
> for any purpose other than for what it is intended. If you have received
> this message in error, please notify the originator immediately. If you are
> not the intended recipient, you are notified that you are strictly
> prohibited from using, copying, altering, or disclosing the contents of
> this message. Aricent accepts no responsibility for loss or damage arising
> from the use of the information transmitted by this email including damage
> from virus."
>
> --
> coreboot mailing list: coreboot@coreboot.org
> https://www.coreboot.org/mailman/listinfo/coreboot
>
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