Re: [coreboot] Where to get ME image/flash descriptors for the x220?

[taii...@gmx.com]

Uhh thanks but that's kinda missing the point of this - that I don't 
want binaries from random people on the internet.


I need to know how to extract it from the bios update files, not the 
bios already on the EEPROM.


On 03/06/2017 11:35 PM, Matt DeVillier wrote:

I have the IFD and ME from an x220 that I recently flashed with coreboot
for a customer, extracted from their stock firmware, and verified working
with the coreboot ROM I subsequently flashed.  Can zip and send via email,
or whatever you prefer

On Mon, Mar 6, 2017 at 10:23 PM, taii...@gmx.com  wrote:


On 03/05/2017 05:20 AM, Arthur Heymans wrote:

"taii...@gmx.com"  writes:

Well I managed to download the latest BIOS from the lenovo site, which

includes an ME update now the issue is that I can't seem to figure out
how to extract it from the .FL1 and .FL2 files.

Those might have a length too long to fit a flash so you need to trim

those down before using ifdtool on those (If they contain and ifd of
course)
so depending on size of rom
dd if=FL1(or 2)file of=vendor_bios.rom bs=1 count=xM

and then ifdtool -x vendor_bios.rom


It didn't work :( after that still "no flash descriptor found in this
image"

These are the files and the flash chip on the board is 8M
8523776 '$01CB000.FL1'
8523776 '$01CB000.FL2'
8523776 '$01CB100.FL2'
All of them have different hashes, but I do not know what makes them
different (maybe it is for various board revisions?)



I would also like to know as to how I can re-flash the EC firmware if

that could potentially cause problems, I of course do not know if it
has DMA.

Only existing tool to flash EC is using vendor tool.

EC are only accessed trough port mapped IO (or on newer ones also via
memory mapped IO). EC itself does not have DMA afaik.



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Re: [coreboot] Where to get ME image/flash descriptors for the x220?

[Matt DeVillier]

I have the IFD and ME from an x220 that I recently flashed with coreboot
for a customer, extracted from their stock firmware, and verified working
with the coreboot ROM I subsequently flashed.  Can zip and send via email,
or whatever you prefer

On Mon, Mar 6, 2017 at 10:23 PM, taii...@gmx.com  wrote:

> On 03/05/2017 05:20 AM, Arthur Heymans wrote:
>
> "taii...@gmx.com"  writes:
>>
>> Well I managed to download the latest BIOS from the lenovo site, which
>>> includes an ME update now the issue is that I can't seem to figure out
>>> how to extract it from the .FL1 and .FL2 files.
>>>
>>> Those might have a length too long to fit a flash so you need to trim
>> those down before using ifdtool on those (If they contain and ifd of
>> course)
>> so depending on size of rom
>> dd if=FL1(or 2)file of=vendor_bios.rom bs=1 count=xM
>>
>> and then ifdtool -x vendor_bios.rom
>>
> It didn't work :( after that still "no flash descriptor found in this
> image"
>
> These are the files and the flash chip on the board is 8M
> 8523776 '$01CB000.FL1'
> 8523776 '$01CB000.FL2'
> 8523776 '$01CB100.FL2'
> All of them have different hashes, but I do not know what makes them
> different (maybe it is for various board revisions?)
>
>
>> I would also like to know as to how I can re-flash the EC firmware if
>>> that could potentially cause problems, I of course do not know if it
>>> has DMA.
>>>
>>> Only existing tool to flash EC is using vendor tool.
>> EC are only accessed trough port mapped IO (or on newer ones also via
>> memory mapped IO). EC itself does not have DMA afaik.
>>
>>
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> https://www.coreboot.org/mailman/listinfo/coreboot
>
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Re: [coreboot] Where to get ME image/flash descriptors for the x220?

[taii...@gmx.com]

On 03/05/2017 05:20 AM, Arthur Heymans wrote:


"taii...@gmx.com"  writes:


Well I managed to download the latest BIOS from the lenovo site, which
includes an ME update now the issue is that I can't seem to figure out
how to extract it from the .FL1 and .FL2 files.


Those might have a length too long to fit a flash so you need to trim
those down before using ifdtool on those (If they contain and ifd of
course)
so depending on size of rom
dd if=FL1(or 2)file of=vendor_bios.rom bs=1 count=xM

and then ifdtool -x vendor_bios.rom

It didn't work :( after that still "no flash descriptor found in this image"

These are the files and the flash chip on the board is 8M
8523776 '$01CB000.FL1'
8523776 '$01CB000.FL2'
8523776 '$01CB100.FL2'
All of them have different hashes, but I do not know what makes them 
different (maybe it is for various board revisions?)





I would also like to know as to how I can re-flash the EC firmware if
that could potentially cause problems, I of course do not know if it
has DMA.


Only existing tool to flash EC is using vendor tool.
EC are only accessed trough port mapped IO (or on newer ones also via
memory mapped IO). EC itself does not have DMA afaik.



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Re: [coreboot] Anyone using the free VBIOS implemention for AMD GPUs?

[taii...@gmx.com]

I have a 5450 (listed as tested working by him) and I am willing to test 
this if you can find me the location (on the card) of the BIOS EEPROM 
just in case anything goes wrong.


I am not sure what other cards are compatible, although the author says 
that anything AtomBIOS probably is (but I am not sure which cards use 
AtomBIOS)


He also says that the other outputs (non-VGA) are initialized by the 
linux kernel but not before that (I suggest using a kexec boot system 
such as petietboot so that you have video output during the boot process)


On 03/06/2017 07:42 PM, i1w5d7gf38...@tutanota.com wrote:

Is someone here using the free VBIOS implementation for AMD PCIe GPUs? Does 
digital Video output also work on some cards or just VGA(D-sub)?

https://sourceforge.net/p/openradeonbios/wiki/Home







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[coreboot] Anyone using the free VBIOS implemention for AMD GPUs?

[i1w5d7gf38keg]

Is someone here using the free VBIOS implementation for AMD PCIe GPUs? Does 
digital Video output also work on some cards or just VGA(D-sub)?

https://sourceforge.net/p/openradeonbios/wiki/Home


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Re: [coreboot] ASUS KGPE-D16 Automated Test Failure [master]

[Timothy Pearson]

-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1

On 03/06/2017 02:40 PM, Raptor Engineering Automated Coreboot Test Stand
wrote:
> The ASUS KGPE-D16 fails verification for branch master as of commit 
> da1d802ec447cf61c568698632aff3578ac5531a
> 
> The following tests failed:
> BOOT_FAILURE
> 
> Commits since last successful test:
> da1d802 soc/intel/skylake: Clean up CPU code
> e074d62 soc/intel/skylake: Use intel/common/xhci driver
> c2fd0a2 intelblocks/msr: Move intel x86 MSR definition into common location
> a554b0c soc/intel/common/block: Add Intel XHCI driver support
> 9a0245a soc/intel/common: Make infrastructure ready for Intel common code
> c2c8397 soc/intel/skylake: Clean up XHCI code
> 79fc33a soc/intel/apollolake: Move XDCI in its own file
> 
> See attached log for details
> 
> This message was automatically generated from Raptor Engineering's ASUS 
> KGPE-D16 test stand
> Want to test on your own equipment?  Check out 
> https://www.raptorengineering.com/content/REACTS/intro.html
> 
> Raptor Engineering also offers coreboot consulting services!  Please visit 
> https://www.raptorengineering.com for more information
> 
> Please contact Timothy Pearson at Raptor Engineering 
>  regarding any issues stemming from this 
> notification
> 

Something seems to have happened to the D16 on the test stand.  Please
ignore for now.

Thanks!

- -- 
Timothy Pearson
Raptor Engineering
+1 (415) 727-8645 (direct line)
+1 (512) 690-0200 (switchboard)
https://www.raptorengineering.com
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[coreboot] ASUS KGPE-D16 Automated Test Failure [master]

[Raptor Engineering Automated Coreboot Test Stand]

The ASUS KGPE-D16 fails verification for branch master as of commit 
da1d802ec447cf61c568698632aff3578ac5531a

The following tests failed:
BOOT_FAILURE

Commits since last successful test:
da1d802 soc/intel/skylake: Clean up CPU code
e074d62 soc/intel/skylake: Use intel/common/xhci driver
c2fd0a2 intelblocks/msr: Move intel x86 MSR definition into common location
a554b0c soc/intel/common/block: Add Intel XHCI driver support
9a0245a soc/intel/common: Make infrastructure ready for Intel common code
c2c8397 soc/intel/skylake: Clean up XHCI code
79fc33a soc/intel/apollolake: Move XDCI in its own file

See attached log for details

This message was automatically generated from Raptor Engineering's ASUS 
KGPE-D16 test stand
Want to test on your own equipment?  Check out 
https://www.raptorengineering.com/content/REACTS/intro.html

Raptor Engineering also offers coreboot consulting services!  Please visit 
https://www.raptorengineering.com for more information

Please contact Timothy Pearson at Raptor Engineering 
 regarding any issues stemming from this 
notification


1488832816-3-automaster.log.bz2
Description: application/bzip2
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Re: [coreboot] kfsn4-dre: Tested RAM configurations?

[Arthur Heymans]

Hi

Coreboot has not merged K8 and fam10 support so you have to compile for
one or the other. (Fam10 being more modern and having a higher amount of
maximum cores per cpu package)

Daniel Kulesz via coreboot  writes:

> Hi all,
>
> the Wiki page for the kfsn4-dre is somewhat incomplete. It mentions that
>
> "K8 processors currently require specific RAM configurations to work 
> correctly. "
>
I don't have this particular board but K8 raminit code is a bit
unflexible with respect to using different dimms and will very quickly
disable a dimm if they are unmatched.

-- 
Arthur Heymans

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[coreboot] kfsn4-dre: Tested RAM configurations?

[Daniel Kulesz via coreboot]

Hi all,

the Wiki page for the kfsn4-dre is somewhat incomplete. It mentions that

"K8 processors currently require specific RAM configurations to work correctly. 
"

However, it is not stated which specific RAM configurations have been tested 
successfully so far.

Furthermore, vendor manual and HCL mention that the board supports only RAM 
modules of maximum 4 GB each. Is this a chipset limitation? If no, is someone 
running this board successfully with 8GB sticks? I would welcome a HCL list of 
tested configurations like the one for the KGPE-D16.

Cheers, Daniel

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[coreboot] How to build coreboot i386 on macOS Sierra?

[Utku Gültopu]

Hello,

I am trying to build coreboot i386 on macOS Sierra but I am getting a
compilation error. The error is:

  Compiling IASL out/src/fw/acpi-dsdt.hex
clang: error: no input files
make[2]: *** [out/src/fw/acpi-dsdt.hex] Error 1
make[1]: *** [build] Error 2
make: *** [payloads/external/SeaBIOS/seabios/out/bios.bin.elf] Error 2

The full steps to reproduce are as follows:

1. git clone https://review.coreboot.org/coreboot.git
2. cd coreboot
3. git checkout tags/4.5
4. git checkout -b 4.5
5. find . -name '.gitignore' -delete
6. git add .
7. git commit -m ‘Remove .gitignore to track changes’
8. make crossgcc-i386
9. git add .
  10. git commit -m ‘Build i386 toolchain’
  11. make nconfig
1. Mainboard -> Mainboard model -> QEMU x86 i440fx/piix4 (aka emu -M pc)
  12. git add .
  13. git commit -m ‘Create configuration file’
  14. make

Output of `make crossgcc-i386` (the command at step 8)
===

user@host:~/src/coreboot$ make crossgcc-i386
Submodule 'arm-trusted-firmware'
(https://review.coreboot.org/arm-trusted-firmware.git) registered for
path '3rdparty/arm-trusted-firmware'
Submodule '3rdparty/blobs' (https://review.coreboot.org/blobs.git)
registered for path '3rdparty/blobs'
Submodule '3rdparty/chromeec'
(https://review.coreboot.org/chrome-ec.git) registered for path
'3rdparty/chromeec'
Submodule 'vboot' (https://review.coreboot.org/vboot.git) registered
for path '3rdparty/vboot'
Submodule 'util/nvidia-cbootimage'
(https://review.coreboot.org/nvidia-cbootimage.git) registered for
path 'util/nvidia/cbootimage'
Cloning into '/Users/user/src/coreboot/3rdparty/arm-trusted-firmware'...
Skipping submodule '3rdparty/blobs'
Cloning into '/Users/user/src/coreboot/3rdparty/chromeec'...
Cloning into '/Users/user/src/coreboot/3rdparty/vboot'...
Cloning into '/Users/user/src/coreboot/util/nvidia/cbootimage'...
Welcome to the coreboot cross toolchain builder v1.43 (August 31st, 2016)

Target architecture is now i386-elf

warning: Building GCC 5.3 with a different major version (4.2).
 Bootstrapping (-b) is recommended.

Downloading tarballs ...
 * gmp-6.1.0.tar.xz (downloading from
http://ftpmirror.gnu.org/gmp/gmp-6.1.0.tar.xz) ..100%
 * mpfr-3.1.4.tar.xz (downloading from
http://ftpmirror.gnu.org/mpfr/mpfr-3.1.4.tar.xz) ..100%
 * mpc-1.0.3.tar.gz (downloading from
http://ftpmirror.gnu.org/mpc/mpc-1.0.3.tar.gz) ..100%
 * libelf-0.8.13.tar.gz (downloading from
http://www.mr511.de/software/libelf-0.8.13.tar.gz) ..100%
 * binutils-2.26.1.tar.bz2 (downloading from
http://ftpmirror.gnu.org/binutils/binutils-2.26.1.tar.bz2) ..100%
 * gcc-5.3.0.tar.bz2 (downloading from
http://ftpmirror.gnu.org/gcc/gcc-5.3.0/gcc-5.3.0.tar.bz2) ..100%
Downloaded tarballs ... ok
Unpacking and patching ...
 * gmp-6.1.0.tar.xz
 * mpfr-3.1.4.tar.xz
 * mpc-1.0.3.tar.gz
 * libelf-0.8.13.tar.gz
 * binutils-2.26.1.tar.bz2
   o binutils-2.26.1_aarch.patch
   o binutils-2.26.1_no-bfd-doc.patch
   o binutils-2.26.1_riscv.patch
 * gcc-5.3.0.tar.bz2
   o gcc-5.3.0_elf_biarch.patch
   o gcc-5.3.0_gnat.patch
   o gcc-5.3.0_libgcc.patch
   o gcc-5.3.0_nds32.patch
   o gcc-5.3.0_riscv.patch
Unpacked and patched ... ok
Building packages ...
Building GMP 6.1.0 ... ok
Building MPFR 3.1.4 ... ok
Building MPC 1.0.3 ... ok
Building LIBELF 0.8.13 ... ok
Building BINUTILS 2.26.1 ... ok
Building GCC 5.3.0 ... ok
Packages built ... ok
Cleaning up temporary files... ok

You can now run your i386-elf cross GCC toolchain from
/Users/user/src/coreboot/util/crossgcc/xgcc.
Welcome to the coreboot cross toolchain builder v1.43 (August 31st, 2016)

Downloading tarballs ...
 * acpica-unix2-20160831.tar.gz (downloading from
https://acpica.org/sites/acpica/files/acpica-unix2-20160831.tar.gz)
..100%
Downloaded tarballs ... ok
Unpacking and patching ...
 * acpica-unix2-20160831.tar.gz
   o acpica-unix2-20160831_iasl.patch
Unpacked and patched ... ok
Building packages ...
Building IASL 20160831 ... ok
Packages built ... ok
Cleaning up temporary files... ok

You can now run your IASL ACPI compiler toolchain from
/Users/user/src/coreboot/util/crossgcc/xgcc.

Content of '.config' file (the output of step 11)
==

#
# Automatically generated file; DO NOT EDIT.
# coreboot configuration
#

#
# General setup
#
CONFIG_LOCALVERSION=""
CONFIG_CBFS_PREFIX="fallback"
CONFIG_COMPILER_GCC=y
# CONFIG_COMPILER_LLVM_CLANG is not set
# CONFIG_ANY_TOOLCHAIN is not set
# CONFIG_CCACHE is not set
# CONFIG_FMD_GENPARSER is not set
# CONFIG_SCONFIG_GENPARSER is not set
# CONFIG_USE_OPTION_TABLE is not set
# CONFIG_UNCOMPRESSED_RAMSTAGE is not set
CONFIG_COMPRESS_RAMSTAGE=y
CONFIG_INCLUDE_CONFIG_FILE=y
# CONFIG_NO_XIP_EARLY_STAGES is not set
CONFIG_EARLY_CBMEM_INIT=y
# CONFIG_EARLY_CBMEM_LIST is not set
# CONFIG_COLLECT_TIMESTAMPS is not set
# CONFIG_USE_BLOBS is not set
# CONFIG_COVERAGE is not set
# CONFIG_RELOCATABLE_MODULES is not set
# CONFIG_RELOCATABLE_RAMSTAGE 

Re: [coreboot] Inteal Leafhill : Linux SATA driver fails when used with coreboot+grub

[Gailu Singh]

Hi,

For multiple Intel SOCs I see sata initialization in sata.c file but that
seems to be missing for apollolake. Could that be a reason?

./soc/intel/skylake/sata.c
./soc/intel/broadwell/sata.c
./soc/intel/baytrail/sata.c
./soc/intel/braswell/sata.c

Thanks

On Mon, Mar 6, 2017 at 12:28 AM, Gailu Singh  wrote:

> Hi Again,
>
> I tried to find out the details for following error
>
> ata1: SATA link down (SStatus 4 SControl 300)
>
> As per status register description
>
> SStatus 4 : Phy in offline mode as a result of the interface being
> disabled or running in a BIST loopback mode
>
> Is there any chance that coreboot/grub/Linux is putting SATA in to BIST
> loopback mode?
>
> I am trying to understand who is responsible for SATA Linux status 4 and
> possible candidates are
> a) coreboot
> b) grub
> c) Linux
>
> Looking forward to your expert advice
>
>
> Thanks
>
> On Fri, Mar 3, 2017 at 9:29 PM, Gailu Singh  wrote:
>
>> Hi Experts,
>>
>> I am trying to boot Linux 4.1 with coreboot and grub but SATA drive fails
>> with error  "ata1: SATA link down (SStatus 4 SControl 300)". It is
>> interesting that GRUB2 can use the SATA drive without issue and able to
>> load kernel from SATA disk.
>>
>> If I use same SATA Drive with Coreboot+UEFI payload then Linux driver
>> just works fine and I am able to boot linux.
>>
>> Any Idea What might be going wrong with Linux Driver. Does it expect
>> something from BIOS/Coreboot that is not fulfilled
>>
>> Linux boot logs:
>> -
>> Initializing cgroup subsys cpuset
>> Initializing cgroup subsys cpu
>> Initializing cgroup subsys cpuacct
>> Linux version 4.1.21-WR8.0.0.11_standard (vgahlaut@ubuntu) (gcc version
>> 5.2.0 (Wind River Linux 5.2.0-8.0-intel-apollolake-i-64) ) #1 SMP
>> PREEMPT Mon Feb 6 18:38:46 PST 2017
>> Command line: BOOT_IMAGE=(ahci0,msdos1)/boot/bzImage root=/dev/sda1
>> rootdelay=10 console=ttyS2,115200
>> KERNEL supported cpus:
>>   Intel GenuineIntel
>>   AMD AuthenticAMD
>>   Centaur CentaurHauls
>> e820: BIOS-provided physical RAM map:
>> BIOS-e820: [mem 0x-0x0fff] type 16
>> BIOS-e820: [mem 0x1000-0x0009] usable
>> BIOS-e820: [mem 0x000a-0x000f] reserved
>> BIOS-e820: [mem 0x0010-0x0fff] usable
>> BIOS-e820: [mem 0x1000-0x12150fff] reserved
>> BIOS-e820: [mem 0x12151000-0x7a64] usable
>> BIOS-e820: [mem 0x7a65-0x7aff] type 16
>> BIOS-e820: [mem 0x7b00-0x7fff] reserved
>> BIOS-e820: [mem 0xd000-0x] reserved
>> BIOS-e820: [mem 0x0001-0x00017fff] usable
>> NX (Execute Disable) protection: active
>> SMBIOS 2.7 present.
>> e820: last_pfn = 0x18 max_arch_pfn = 0x4
>> PAT configuration [0-7]: WB  WC  UC- UC  WB  WC  UC- UC
>> e820: last_pfn = 0x7a650 max_arch_pfn = 0x4
>> Scanning 1 areas for low memory corruption
>> Using GB pages for direct mapping
>> init_memory_mapping: [mem 0x-0x000f]
>> init_memory_mapping: [mem 0x17fe0-0x17fff]
>> init_memory_mapping: [mem 0x16000-0x17fdf]
>> init_memory_mapping: [mem 0x0010-0x0fff]
>> init_memory_mapping: [mem 0x12151000-0x7a64]
>> init_memory_mapping: [mem 0x1-0x15fff]
>> ACPI: Early table checksum verification disabled
>> ACPI: RSDP 0x000F 24 (v02 CORE  )
>> ACPI: XSDT 0x7A6690E0 5C (v01 CORE   COREBOOT  CORE
>> )
>> ACPI: FACP 0x7A66BA60 00010C (v05 CORE   COREBOOT  CORE
>> 0001)
>> ACPI BIOS Warning (bug): 32/64X length mismatch in FADT/Pm1aEventBlock:
>> 32/16 (20150410/tbfadt-623)
>> ACPI BIOS Warning (bug): Invalid length for FADT/Pm1aEventBlock: 16,
>> using default 32 (20150410/tbfadt-704)
>> ACPI: DSDT 0x7A669280 0027D8 (v05 COREv4 COREBOOT 20110725 INTL
>> 20160831)
>> ACPI: FACS 0x7A669240 40
>> ACPI: FACS 0x7A669240 40
>> ACPI: SSDT 0x7A66BB70 000774 (v02 CORE   COREBOOT 002A CORE
>> 002A)
>> ACPI: MCFG 0x7A66C2F0 3C (v01 CORE   COREBOOT  CORE
>> )
>> ACPI: TCPA 0x7A66C330 32 (v02 CORE   COREBOOT  CORE
>> )
>> ACPI: TPM2 0x7A66C370 34 (v04 CORE   COREBOOT  CORE
>> )
>> ACPI: APIC 0x7A66C3B0 6C (v01 CORE   COREBOOT  CORE
>> )
>> ACPI: HPET 0x7A66C420 38 (v01 CORE   COREBOOT  CORE
>> )
>> Zone ranges:
>>   DMA  [mem 0x1000-0x00ff]
>>   DMA32[mem 0x0100-0x]
>>   Normal   [mem 0x0001-0x00017fff]
>> Movable zone start for each node
>> Early memory node ranges
>>   node   0: [mem 0x1000-0x0009]
>>   node   0: [mem 0x0010-0x0fff]
>>   node   0: [mem