Re: [coreboot] Asus M2N-E

[Martin A]

Ok Timothy,


Thanks a lot for your help, really appreciate.


I tried try with a dual core Athlon 64 X2 and the boot log is an exact copy of 
the Opteron's.

So it has something to do with the mainboard.


Hope Uwe Hermann see this.


Martin.


De : Timothy Pearson 
Envoyé : mardi 23 mai 2017 19:56
À : Martin A
Cc : coreboot@coreboot.org
Objet : Re: [coreboot] Asus M2N-E

-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1

On 05/23/2017 03:37 AM, Martin A wrote:
>
>
> Sorry, here is the "not so perfect" boot log.
>
> Many weirds points, no ?
>
> Thank you very much
>
>
> Martin
>
>
> ---
>
> BSP overran lower stack boundary.  Undefined behaviour may result!



This is probably the issue right here.  This means a coreboot developer
(preferably with access to this hardware) needs to take a look at the
stack allocation for the 0xf Opteron chips to see why coreboot is
overrunning the stack space.

- --
Timothy Pearson
Raptor Engineering
+1 (415) 727-8645 (direct line)
+1 (512) 690-0200 (switchboard)
https://www.raptorengineering.com
Raptor Engineering::Home Page
www.raptorengineering.com
Let Raptor Engineering handle your next high-performance digital design! We 
offer consulting services in: Embedded systems design; Boot firmware 
development (e.g ...


-BEGIN PGP SIGNATURE-
Version: GnuPG v1
Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/

iQEcBAEBAgAGBQJZJHfKAAoJEK+E3vEXDOFbEl8H/1ZRYw1tQABpk/uhhuHY0R5G
97B6BaRW0PIJXUg0ekGCYfPEqXgtiSsr1K77VMY8wpov1aNkaGEMjRw300he4Dk2
sPqjUqwaHB57+qw1W9YYbYsDf3JGZEizNd9WapixHS1pXhEGDoR/g6NPL6LFyZMr
+RGjPnLIBq5yksGGnF4UMa9/VWmdBXzUDcrFAKYB1ptQe42sIvtE8KvMRtXZmYqr
bvS5WAksOPjZhmNntDPxopQE0HaxUyMZJINVALBVj+Hq20gFOWCwnNuB8m78zDPl
47ncYoHV82UKGEzklWlF1ohEKUAIKdI0NrbBqXxbk0zJabaYoEkIu3gVEKlgFKc=
=r7in
-END PGP SIGNATURE-
-- 
coreboot mailing list: coreboot@coreboot.org
https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Asus M2N-E

[Timothy Pearson]

-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1

On 05/23/2017 03:37 AM, Martin A wrote:
> 
> 
> Sorry, here is the "not so perfect" boot log.
> 
> Many weirds points, no ?
> 
> Thank you very much
> 
> 
> Martin
> 
> 
> ---
> 
> BSP overran lower stack boundary.  Undefined behaviour may result!



This is probably the issue right here.  This means a coreboot developer
(preferably with access to this hardware) needs to take a look at the
stack allocation for the 0xf Opteron chips to see why coreboot is
overrunning the stack space.

- -- 
Timothy Pearson
Raptor Engineering
+1 (415) 727-8645 (direct line)
+1 (512) 690-0200 (switchboard)
https://www.raptorengineering.com
-BEGIN PGP SIGNATURE-
Version: GnuPG v1
Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/

iQEcBAEBAgAGBQJZJHfKAAoJEK+E3vEXDOFbEl8H/1ZRYw1tQABpk/uhhuHY0R5G
97B6BaRW0PIJXUg0ekGCYfPEqXgtiSsr1K77VMY8wpov1aNkaGEMjRw300he4Dk2
sPqjUqwaHB57+qw1W9YYbYsDf3JGZEizNd9WapixHS1pXhEGDoR/g6NPL6LFyZMr
+RGjPnLIBq5yksGGnF4UMa9/VWmdBXzUDcrFAKYB1ptQe42sIvtE8KvMRtXZmYqr
bvS5WAksOPjZhmNntDPxopQE0HaxUyMZJINVALBVj+Hq20gFOWCwnNuB8m78zDPl
47ncYoHV82UKGEzklWlF1ohEKUAIKdI0NrbBqXxbk0zJabaYoEkIu3gVEKlgFKc=
=r7in
-END PGP SIGNATURE-

-- 
coreboot mailing list: coreboot@coreboot.org
https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] CONFIG_CBFS_SIZE vs CONFIG_ROM_SIZE

[Patrick Georgi via coreboot]

We always add an FMAP now (think of it of a vendor neutral flash partition
table), which resides outside CBFS.

2017-05-23 9:49 GMT-07:00 Gailu Singh :

> Hi Experts,
>
> If we use CBFS_SIZE to be same as ROM_SIZE on our apollolake board grub
> fails to load grub.cfg located in CBFS. Based on experiments we found that
> grub.cfg is loaded correctly if we keep minimum difference of 64KB between
> CBFS_SIZE and ROM_SIZE if we reduce it to less that 64KB problem happens.
>
> Can someone please explain the behavior and if it is expected behavior or
> a bug?
>
> --
> coreboot mailing list: coreboot@coreboot.org
> https://mail.coreboot.org/mailman/listinfo/coreboot
>



-- 
Google Germany GmbH, ABC-Str. 19, 20354 Hamburg
Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft:
Hamburg
Geschäftsführer: Matthew Scott Sucherman, Paul Terence Manicle
-- 
coreboot mailing list: coreboot@coreboot.org
https://mail.coreboot.org/mailman/listinfo/coreboot

[coreboot] CONFIG_CBFS_SIZE vs CONFIG_ROM_SIZE

[Gailu Singh]

Hi Experts,

If we use CBFS_SIZE to be same as ROM_SIZE on our apollolake board grub
fails to load grub.cfg located in CBFS. Based on experiments we found that
grub.cfg is loaded correctly if we keep minimum difference of 64KB between
CBFS_SIZE and ROM_SIZE if we reduce it to less that 64KB problem happens.

Can someone please explain the behavior and if it is expected behavior or a
bug?
-- 
coreboot mailing list: coreboot@coreboot.org
https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Easier accessibility for coreboot/flashrom wikipedias? What do you think?

[Denis 'GNUtoo' Carikli]

On Fri, 19 May 2017 11:20:27 +0300
qma ster  wrote:

> Dear coreboot/flashrom mailing list members,
Hi,

> As you may have noticed it is not that easy or straightforward to
> gain the edit rights for coreboot/flashrom wikipedias so the people
> are mass migrating to the unofficial wikis.
Having already an account, I cound't notice it.
Having good quality and extensive documentation is really important, so
fixing that is important.

> My proposal is to give the edit rights to all the subscribers of the
> coreboot/flashrom mailing lists, or at least to all those who have
> been the subscribers for at least a day / a week / or a month.
Having a human review the subscription would probably be a better
idea, if done correctly:
- Humans could review if the request seems legit.
- The subscribers could have that human as a reference, to ask questions
  if needed.
- The reviewers could help the subscriber if they whish.
However to work correctly:
- The review process would need to be fast for both the reviewer and the
  subscriber. An idea would not to have to go trough something that
  looks like a job interview, as it was mentioned, but rather explain
  why the subscriber wants wiki access. It should then be explained
  what kind of description is expected.
- It would be nice if a welcome page is created on the user account
  space, like on wikipedia. This would permit to refer to some general
  guidelines for the wikis. For instance, some of my edits on the
  flashrom wiki were reverted or moved to my user page, because I
  didn't properly understand what level of anti-bricking safety was
  required[1].
  There are also lot of tutorials on the Internet which uses improper
  voltages (like 5V instead of 3.3V) for the flash chip, and as I was
  told, it accidentally works probably because the wire setup is so bad
  that the voltage drops on the wires, due to the resistance.
  Good guidelines/explanation pages would probably be sufficent to
  avoid such issues in the flashrom wiki.

References:
---
[1] I explained how to reflash the option rom of an old nvidia GPU by
explaining how to bypass the read-only safety in flashrom, and
making several writes attempt to flash the (sgabios) image.
Since the method used always succedded for me, I thought that it
was fine at the time of writing.

Denis.


pgp9GAX5Bwd_E.pgp
Description: OpenPGP digital signature
-- 
coreboot mailing list: coreboot@coreboot.org
https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Current, BLOB free laptop available Europe?

[Peter Stuge]

Hi Tiberiu,

Tiberiu wrote:
> We also offer an installation service of libreboot (fully free coreboot
> distro). Upon request, we can install libreboot also on other laptops

I'd like to encourage you (all vendors, really) to both emphasize and
engage with coreboot directly.

I know that I would really like for coreboot proper to be immediately
usable for you.


//Peter

-- 
coreboot mailing list: coreboot@coreboot.org
https://mail.coreboot.org/mailman/listinfo/coreboot

[coreboot] New Defects reported by Coverity Scan for coreboot

[scan-admin]

Hi,

Please find the latest report on new defect(s) introduced to coreboot found 
with Coverity Scan.

1 new defect(s) introduced to coreboot found with Coverity Scan.
1 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent 
build analyzed by Coverity Scan.

New defect(s) Reported-by: Coverity Scan
Showing 1 of 1 defect(s)


** CID 1375565:  Control flow issues  (DEADCODE)
/src/drivers/spi/spi_flash.c: 303 in spi_flash_generic_probe()



*** CID 1375565:  Control flow issues  (DEADCODE)
/src/drivers/spi/spi_flash.c: 303 in spi_flash_generic_probe()
297 for (i = 0; i < sizeof(idcode); i++)
298 printk(BIOS_SPEW, "%02x ", idcode[i]);
299 printk(BIOS_SPEW, "\n");
300 }
301 
302 /* count the number of continuation bytes */
>>> CID 1375565:  Control flow issues  (DEADCODE)
>>> Execution cannot reach the expression "*idp == 127" inside this 
>>> statement: "for ((shift = 0) , (idp = i...".
303 for (shift = 0, idp = idcode; shift < IDCODE_CONT_LEN && *idp 
== 0x7f;
304  ++shift, ++idp)
305 continue;
306 
307 printk(BIOS_INFO, "Manufacturer: %02x\n", *idp);
308 



To view the defects in Coverity Scan visit, 
https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V05UPxvVjWch-2Bd2MGckcRbLuoVetFLSjdonCi1EjfHRqWGQvojmmkYaBE-2BPJiTQvQ-3D-3D_q4bX76XMySz3BXBlWr5fXXJ4cvAsgEXEqC7dBPM7O5bVeAcn-2Fh6tOA63b8ypNiIWQjS5VHYifBDyeOXkdVtEFrMAZJVdo4xbUPBTyR3-2ByaBjOxK5iXd6htSUPwWLEjQsw1NLRbfiKYVSwNz7Ps-2FLN7ZrdjdTPbspPSuhcPIORi6AYBJcmQtDW6xxzr6vJvYfKFVJKsRIn-2FEY5s9MtmShHz-2FtXMyrjdScAtVOx-2F6z0ac-3D

To manage Coverity Scan email notifications for "coreboot@coreboot.org", click 
https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V05UPxvVjWch-2Bd2MGckcRbVDbis712qZDP-2FA8y06Nq4e-2BpBzwOa5gzBZa9dWpDbzfofODnVj1enK2UkK0-2BgCCqyeem8IVKvTxSaOFkteZFcnohwvb2rnYNjswGryEWCURnUk6WHU42sbOmtOjD-2Bx5c-3D_q4bX76XMySz3BXBlWr5fXXJ4cvAsgEXEqC7dBPM7O5bVeAcn-2Fh6tOA63b8ypNiIWycZmEBMeJ-2F8GJgKyYqLn-2FUTrQnu2QqLn89kkfoP0g3e1tKltZCLAg3wXS-2FusBRql9eEUn7tb7rKIEnqqWIxDpQuccVBWHqjWGcBuKg0wWygPnZzOzba58sOZNeZ8GglL0P3n0JyjzVbfTVM8knvpFVl4WrS7HtO-2Fp2NympUzth0-3D


-- 
coreboot mailing list: coreboot@coreboot.org
https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Intel me problems

[Nico Huber]

On 23.05.2017 00:58, Alejandro Flores wrote:
> Ok, so the image John uploaded of a known good me is exactly the same as
> the one I have been using that fails.  The shasums match exactly.  So I
> thought maybe somehow it is getting corrupted when coreboot creates the
> rom.  I used the unhuffme tool to examine both the raw me image and the
> coreboot.rom file I am currently using.  Both are identical except the full
> rom has 4 extra lines regarding the location of flash regions at the top.

If the ME image is known good, how about your firmware descriptor? the
first 4KiB on the flash. Did you verify that they are still the same as
in the original?

You can compare two binaries simply with `cmp`. It'll tell you the
position of the first mismatching byte. If that is below 4096, better
write back the descriptor from the original image. You can use flash-
rom's layout option for that (see `man flashrom`).

Nico

> 
> The output of unhuffme is here:
> https://pastebin.com/zRsh6TqA
> 
> I downloaded the latest version of intelmetool to check out the live
> running me but it says my hardware is not compatible.  I'm stumped at this
> point. If the me image is good why does the checksum fail on boot?


-- 
coreboot mailing list: coreboot@coreboot.org
https://mail.coreboot.org/mailman/listinfo/coreboot

[coreboot] Intel Rangeley: System is hanging after post code 0x92.

[Dhanasekar Jaganathan]

Hi All,

I am trying to boot Intel Atom Rangeley Sever CPU (Mohon Peak) with
coreboot BIOS.

After Postcode 0x92, system is not booting.

I have pasted the debug message below,
*coreboot-4.5-1596-gb86ccbb Thu Apr 20 14:55:30 UTC 2017 romstage
starting...*
*POST: 0x41*
*POST: 0x42*
*Setting up static southbridge registers... done.*
*Disabling Watchdog timer... done.*
*RTC Failure detected.  Resetting Date to 04/20/2017*
*RTC Init*
*RTC: Clear requested zeroing cmos*
*POST: 0x46*
*POST: 0x47*
*Starting the Intel FSP (early_init)*
*Configure Default UPD Data*
*PcdEnableIQAT 1*
*PcdEnableLan 1*
*PcdEnableLan 1*
*PcdEnableLan 1*
*PcdEnableLan 1*
*PcdEnableUsb20 1*
*PcdEnableSata2 1*
*PcdEnableSata3 1*
*PcdPcieRootPort1DeEmphasis: 0x00 (default)*
*PcdPcieRootPort2DeEmphasis: 0x00 (default)*
*PcdPcieRootPort3DeEmphasis: 0x00 (default)*
*PcdPcieRootPort4DeEmphasis: 0x00 (default)*
*CBFS: 'Master Header Locator' located CBFS at [100:7fffc0)*
*CBFS: Locating 'mrc.cache'*
*CBFS: Checking offset 0*
*CBFS: File @ offset 0 size 20*
*CBFS:  Unmatched 'cbfs master header' at 0*
*CBFS: Checking offset 80*
*CBFS: File @ offset 80 size 5e84*
*CBFS:  Unmatched 'fallback/romstage' at 80*
*CBFS: Checking offset 5f80*
*CBFS: File @ offset 5f80 size 227*
*CBFS:  Unmatched 'config' at 5f80*
*CBFS: Checking offset 6200*
*CBFS: File @ offset 6200 size 23a*
*CBFS:  Unmatched 'revision' at 6200*
*CBFS: Checking offset 6480*
*CBFS: File @ offset 6480 size 528*
*CBFS:  Unmatched 'cmos_layout.bin' at 6480*
*CBFS: Checking offset 6a00*
*CBFS: File @ offset 6a00 size 1f96*
*CBFS:  Unmatched 'fallback/dsdt.aml' at 6a00*
*CBFS: Checking offset 8a00*
*CBFS: File @ offset 8a00 size 7498*
*CBFS:  Unmatched '' at 8a00*
*CBFS: Checking offset fec0*
*CBFS: File @ offset fec0 size 1*
*CBFS: Found @ offset fec0 size 1*
*find_current_mrc_cache_local: No valid fast boot cache found.*
*FSP MRC cache not present.*
*POST: 0x92*

Is there any setting I need to do in "make menuconfig"?. Actually, It
should go to RAM Stage, but it is not.

Please provide suggestion.

Thanks,

Dhanasekar
-- 
coreboot mailing list: coreboot@coreboot.org
https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Current, BLOB free laptop available Europe?

[Tiberiu]

Hi,

On 23.05.2017 11:39, PeerCorps Trust Fund wrote:
> Vikings in Germany has this:
> https://store.vikings.net/libre-friendly-hardware/x200-ryf-certfied
> 
> I suppose these don't necessarily count as "new" as in right from the
> factory floor, but depending on your use case it might be worth a look.
> It is FSF certified.

Like our friends Vikings, Technoethical is also based in Europe
(Romania) and ships worldwide.

Our shop has the largest catalog of laptops with fully free BIOS. We've
been selling laptops with fully free BIOS for almost one year now.

https://libreboot.org/suppliers.html#technoethical
https://technoethical.com/laptops

We also offer an installation service of libreboot (fully free coreboot
distro). Upon request, we can install libreboot also on other laptops
besides those listed on our website.

Thank GNU,
--
Tiberiu
Technoethical

-- 
coreboot mailing list: coreboot@coreboot.org
https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Current, BLOB free laptop available Europe?

[Martin A]

Hi Paul,


Did you have look here:

https://www.fsf.org/resources/hw/endorsement/respects-your-freedom


Martin


De : coreboot  de la part de Paul Menzel 

Envoyé : mardi 23 mai 2017 08:54
À : coreboot@coreboot.org
Objet : [coreboot] Current, BLOB free laptop available Europe?

Dear coreboot folks,


I am looking for a new portable device available in Europe.

Is it true, that the Acer Chromebook R 13 [1], is the only current BLOB
free device? The device currently costs 400 €. Is MediaTek “a good
citizen”, that means, do they provide datasheets and work on drivers?

The Samsung Chromebook Plus/Pro with RK3399 [2] are only available in
the USA, right?


Thanks,

Paul


[1] https://www.acer.com/ac/en/US/content/series/acerchromebookr13
Acer Chromebook R 13 | Laptops - One Chromebook, many 
...
www.acer.com
Acer Laptops Acer Chromebook R 13: One Chromebook, many options. Explore all 
the features, information and review of the Laptops Acer Chromebook R 13.


[2] 
https://chromeunboxed.com/samsung-chromebook-pros-processor-rk3399-gets-benchmarked-and-it-is-fast/
Samsung Chromebook Pro's Processor (RK3399) Gets 
...
chromeunboxed.com
Full disclosure, this is not the Samsung Chromebook Pro getting benchmarked, 
though as you’ll see shortly, we can do a bit of math and get a pretty good 
idea of ...

-- 
coreboot mailing list: coreboot@coreboot.org
https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Current, BLOB free laptop available Europe?

[PeerCorps Trust Fund]

Hi Paul,

Vikings in Germany has this: 
https://store.vikings.net/libre-friendly-hardware/x200-ryf-certfied

I suppose these don't necessarily count as "new" as in right from the factory 
floor, but depending on your use case it might be worth a look. It is FSF certified.

Mike

On 05/23/2017 09:54 AM, Paul Menzel wrote:

Dear coreboot folks,


I am looking for a new portable device available in Europe.

Is it true, that the Acer Chromebook R 13 [1], is the only current BLOB
free device? The device currently costs 400 €. Is MediaTek “a good
citizen”, that means, do they provide datasheets and work on drivers?

The Samsung Chromebook Plus/Pro with RK3399 [2] are only available in
the USA, right?


Thanks,

Paul


[1] https://www.acer.com/ac/en/US/content/series/acerchromebookr13
[2] 
https://chromeunboxed.com/samsung-chromebook-pros-processor-rk3399-gets-benchmarked-and-it-is-fast/





--
coreboot mailing list: coreboot@coreboot.org
https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Asus M2N-E

[Martin A]

Sorry, here is the "not so perfect" boot log.

Many weirds points, no ?

Thank you very much


Martin


---

BSP overran lower stack boundary.  Undefined behaviour may result!
I2C: 01:50 missing read_resources
I2C: 01:51 missing read_resources
I2C: 01:52 missing read_resources
I2C: 01:53 missing read_resources
skipping PNP: 002e.3@62 fixed resource, size=0!
SeaBIOS (version rel-1.10.2-0-g5f4c7b1)
BUILD: gcc: (coreboot toolchain v1.44 March 3rd, 2017) 6.3.0 binutils: (GNU 
Binutils) 2.28
SeaBIOS (version rel-1.10.2-0-g5f4c7b1)
BUILD: gcc: (coreboot toolchain v1.44 March 3rd, 2017) 6.3.0 binutils: (GNU 
Binutils) 2.28
Found coreboot cbmem console @ bffde000
Found mainboard ASUS M2N-E
Relocating init from 0x000e3940 to 0xbff87d80 (size 49632)
Found CBFS header at 0xfff80138
multiboot: eax=0, ebx=0
Found 24 PCI devices (max PCI bus is 05)
Copying SMBIOS entry point from 0xbffd4000 to 0x000f7140
Skipping MPTABLE copy due to large size (660 bytes)
CPU Mhz=1000
Scan for VGA option rom
Running option rom at c000:0003
Turning on vga text mode console
SeaBIOS (version rel-1.10.2-0-g5f4c7b1)
EHCI init on dev 00:02.1 (regs=0xf414a020)
OHCI init on dev 00:02.0 (regs=0xf4145000)
ATA controller 1 at 1f0/3f4/0 (irq 14 dev 20)
ATA controller 2 at 170/374/0 (irq 15 dev 20)
ATA controller 3 at 3000/3038/0 (irq 0 dev 28)
ATA controller 4 at 3008/303c/0 (irq 0 dev 28)
ATA controller 5 at 3010/3040/0 (irq 0 dev 29)
ATA controller 6 at 3018/3044/0 (irq 0 dev 29)
ATA controller 7 at 3020/3048/0 (irq 0 dev 2a)
ATA controller 8 at 3028/304c/0 (irq 0 dev 2a)
Got ps2 nak (status=51)
Found 1 lpt ports
Found 1 serial ports
USB keyboard initialized
ata7-0: ST9250311CS ATA-8 Hard-Disk (232 GiBytes)
Searching bootorder for: /pci@i0cf8/*@5,2/drive@1/disk@0
All threads complete.
Scan for option roms

Press ESC for boot menu.

Searching bootorder for: HALT
drive 0x000f7010: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=488397168
Space available for UMB: cf800-ef000, f6960-f7010
Returned 253952 bytes of ZoneHigh
e820 map has 6 items:
  0:  - 0009fc00 = 1 RAM
  1: 0009fc00 - 000a = 2 RESERVED
  2: 000f - 0010 = 2 RESERVED
  3: 0010 - bffd2000 = 1 RAM
  4: bffd2000 - c000 = 2 RESERVED
  5: 0001 - 00014000 = 1 RAM
enter handle_19:
  NULL
Booting from Hard Disk...
Booting from :7c00

--- on screen ---
Grub Menu -> Ubuntu, with Linux 4.8.0-52-generic (recovery mode)
-

pnp call arg1=0
pnp call arg1=5
---



De : Timothy Pearson 
Envoyé : lundi 22 mai 2017 18:10
À : Martin A
Cc : coreboot@coreboot.org
Objet : Re: [coreboot] Asus M2N-E: Waiting for 1 CPUS to stop

-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1

On 05/21/2017 09:46 AM, Martin A wrote:
>
>
> Thank you very much Timothy !
>
> debug level @ WARNING and it boots well -> a nice bootlog in a 1 or 2
> seconds, so fast !!
>
>
> But Seabios do not boot well:
>
> Ubuntu 16.04 internal SATA Drive -> PnPBIOS dev_node_info funstions not
> avilable an this system
>
> Windows 7 x64 USB drive -> Non ACPI Bios
>
>
> Any tips/advice

I'm not directly familiar with this system; without a full boot log I'd
just be guessing. :-)

Perhaps someone else on this list has experience with this mainboard and
recognizes these issues?

- --
Timothy Pearson
Raptor Engineering
+1 (415) 727-8645 (direct line)
+1 (512) 690-0200 (switchboard)
https://www.raptorengineering.com
Raptor Engineering::Home Page
www.raptorengineering.com
Let Raptor Engineering handle your next high-performance digital design! We 
offer consulting services in: Embedded systems design; Boot firmware 
development (e.g ...


-BEGIN PGP SIGNATURE-
Version: GnuPG v1
Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/

iQEcBAEBAgAGBQJZIw1dAAoJEK+E3vEXDOFbP3UH/iq/A0ReMOo8vA9xc2Yxw26l
foGQ01st8f/rpqlR/hY3lG4yo2F0lhF4To8JMNCjystC9BQshRPI4E/GJERjXjiH
EufAY0NOV4DShp3Bo43ICpDx9XgEAkTcGBG0OklxMmvpC85nBRvdXe+8yDpLE7Gv
2GKoQH1Y1RbkwQ/8ynae0V63SEYVNbDCqI+5Z0PnZ4vs8auRLlp5GKyfsHGSjKlV
CA5cJxOiEPkkjO4nWUqmUq0E8bg5F+Ax14ynsyVQxJLEOA39l4HzjClhwqHcepZt
8vGuFuaoNAW38VDhPauzM0yPrb8muN5np5bfJIDZuvbwCkgpI4MAEhaZKO2Ila4=
=KfyS
-END PGP SIGNATURE-
-- 
coreboot mailing list: coreboot@coreboot.org
https://mail.coreboot.org/mailman/listinfo/coreboot

[coreboot] Current, BLOB free laptop available Europe?

[Paul Menzel]

Dear coreboot folks,


I am looking for a new portable device available in Europe.

Is it true, that the Acer Chromebook R 13 [1], is the only current BLOB
free device? The device currently costs 400 €. Is MediaTek “a good
citizen”, that means, do they provide datasheets and work on drivers?

The Samsung Chromebook Plus/Pro with RK3399 [2] are only available in
the USA, right?


Thanks,

Paul


[1] https://www.acer.com/ac/en/US/content/series/acerchromebookr13
[2] 
https://chromeunboxed.com/samsung-chromebook-pros-processor-rk3399-gets-benchmarked-and-it-is-fast/

signature.asc
Description: This is a digitally signed message part
-- 
coreboot mailing list: coreboot@coreboot.org
https://mail.coreboot.org/mailman/listinfo/coreboot

[coreboot] REG : coreboot with UEFI payload

[nagaraj a]

Hi All,

I'm trying to compiling coreboot with UEFI payload, however I couldn't able
to get proper out file and below is the error. Pls let us know, If I am
missing any configuration or compilation procedure?

 To instrumentation I’m trying to run coreboot UEFI payload in QEMU and
will then proceed for actual H/W



Thanks,

Nagaraj A
-- 
coreboot mailing list: coreboot@coreboot.org
https://mail.coreboot.org/mailman/listinfo/coreboot