Re: [coreboot] ast2400 / ast2500

[Tirumalesh]

Thanks for the information.

As I understand correctly, the main support is for x86 only. So if we want to 
run coreboot as the only firmware, we have to do it our self.

Thanks,
Tirumalesh

On Fri, Oct 20, 2017 at 6:42 PM, taii...@gmx.com  wrote:

> On 10/20/2017 03:04 PM, Tirumalesh wrote: > Thanks for the reply, it is 
> somewhat strange though. > > It means no server board runs fully with 
> coreboot as firmware for both c86 and BMC. > > If this is not the case, what 
> kind of bmc is used by all the supported boards, all of them are using 
> different firmware for bmc and x86? As tim said the KGPE-D16 and KCMA-D8 have 
> a fully open source libre init process on coreboot and support the libre 
> OpenBMC for the AST BMC chip There aren't any other coreboot boards that 
> support a BMC, and the only other device that has both fully open source 
> firmware/init and an open source BMC off the shelf is the TALOS 2. Coreboot 
> itself couldn't be ran on a BMC chip, well I suppose one could port it but 
> there really wouldn't be a point to that as that isn't what it was designed 
> for. PS welcome to the list :D-- 
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Re: [coreboot] ast2400 / ast2500

[taii...@gmx.com]

On 10/20/2017 03:04 PM, Tirumalesh wrote:


Thanks for the reply, it is somewhat strange though.

It means no server board runs fully with coreboot as firmware for both c86 and 
BMC.

If this is not the case, what kind of bmc is used by all the supported boards, 
all of them are using different firmware for bmc and x86?
As tim said the KGPE-D16 and KCMA-D8 have a fully open source libre init 
process on coreboot and support the libre OpenBMC for the AST BMC chip


There aren't any other coreboot boards that support a BMC, and the only 
other device that has both fully open source firmware/init and an open 
source BMC off the shelf is the TALOS 2.


Coreboot itself couldn't be ran on a BMC chip, well I suppose one could 
port it but there really wouldn't be a point to that as that isn't what 
it was designed for.



PS welcome to the list :D

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Re: [coreboot] ast2400 / ast2500

[Tirumalesh]

I am trying to see if coreboot can be main firmware on bmc.

Does coreboot supports any BMC chips in general?

Thanks,
Tirumalesh

On Fri, Oct 20, 2017 at 11:42 AM, David Hendricks 
<[david.hendri...@gmail.com]("mailto:david.hendri...@gmail.com;)> wrote:

> On Fri, Oct 20, 2017 at 7:46 AM, Tirumalesh 
> <[tirumal...@chalamarla.com]("mailto:tirumal...@chalamarla.com;)> wrote:
>
>> Hi,
>>
>> Could some one please let me know, if corebott supports either 
>> AST2400/AST2500 (ASpeed BMC)
>> If yes, how to test it with QEMU?
>
> What kind of support are you looking for? There is some support for 
> interfacing with it in coreboot running on the host: 
> [https://review.coreboot.org/cgit/coreboot.git/tree/src/drivers/aspeed]("https://review.coreboot.org/cgit/coreboot.git/tree/src/drivers/aspeed;)
>
> I believe this was added as part of the Asus KGPE-D16 OpenBMC porting effort: 
> [https://www.raptorengineering.com/coreboot/kgpe-d16-bmc-port-status.php]("https://www.raptorengineering.com/coreboot/kgpe-d16-bmc-port-status.php;)-- 
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Re: [coreboot] ast2400 / ast2500

[Tirumalesh]

Thanks for the reply, it is somewhat strange though.

It means no server board runs fully with coreboot as firmware for both c86 and 
BMC.

If this is not the case, what kind of bmc is used by all the supported boards, 
all of them are using different firmware for bmc and x86?

Thanks,
Tirumalesh

On Fri, Oct 20, 2017 at 11:47 AM, Timothy Pearson 
 wrote:

> -BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 10/20/2017 01:42 PM, David 
> Hendricks wrote: > > > On Fri, Oct 20, 2017 at 7:46 AM, Tirumalesh > wrote: > 
> > Hi, > > Could some one please let me know, if corebott supports either > 
> AST2400/AST2500 (ASpeed BMC) > If yes, how to test it with QEMU? > > > What 
> kind of support are you looking for? There is some support for > interfacing 
> with it in coreboot running on the > host: 
> https://review.coreboot.org/cgit/coreboot.git/tree/src/drivers/aspeed >  > > 
> I believe this was added as part of the Asus KGPE-D16 OpenBMC porting > 
> effort: 
> https://www.raptorengineering.com/coreboot/kgpe-d16-bmc-port-status.php >  
> While somewhat similar in terms of interfaces / functionality, that board 
> uses the AST2050 which is a much less powerful chip. The AST2400 doesn't see 
> much use on x86 coreboot-supported platforms as far as I am aware; SuperMicro 
> likes to use it but it doesn't look like any of those boards are supported 
> (there are no reports for any of those boards in the board status repository 
> [1]). [1] https://www.coreboot.org/Supported_Motherboards - -- Timothy 
> Pearson Raptor Engineering +1 (415) 727-8645 (direct line) +1 (512) 690-0200 
> (switchboard) https://www.raptorengineering.com -BEGIN PGP SIGNATURE- 
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> https://mail.coreboot.org/mailman/listinfo/coreboot @chalamarla.com> 
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Re: [coreboot] ast2400 / ast2500

[Timothy Pearson]

-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1

On 10/20/2017 01:42 PM, David Hendricks wrote:
> 
> 
> On Fri, Oct 20, 2017 at 7:46 AM, Tirumalesh  > wrote:
> 
> Hi,
> 
> Could some one please let me know, if corebott supports either
> AST2400/AST2500 (ASpeed BMC)
> If yes, how to test it with QEMU?
> 
> 
> What kind of support are you looking for? There is some support for
> interfacing with it in coreboot running on the
> host: https://review.coreboot.org/cgit/coreboot.git/tree/src/drivers/aspeed
> 
> 
> I believe this was added as part of the Asus KGPE-D16 OpenBMC porting
> effort: 
> https://www.raptorengineering.com/coreboot/kgpe-d16-bmc-port-status.php
> 

While somewhat similar in terms of interfaces / functionality, that
board uses the AST2050 which is a much less powerful chip.

The AST2400 doesn't see much use on x86 coreboot-supported platforms as
far as I am aware; SuperMicro likes to use it but it doesn't look like
any of those boards are supported (there are no reports for any of those
boards in the board status repository [1]).

[1] https://www.coreboot.org/Supported_Motherboards

- -- 
Timothy Pearson
Raptor Engineering
+1 (415) 727-8645 (direct line)
+1 (512) 690-0200 (switchboard)
https://www.raptorengineering.com
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Re: [coreboot] ast2400 / ast2500

[David Hendricks]

On Fri, Oct 20, 2017 at 7:46 AM, Tirumalesh 
wrote:

> Hi,
>
> Could some one please let me know, if corebott supports either
> AST2400/AST2500 (ASpeed BMC)
> If yes, how to test it with QEMU?
>

What kind of support are you looking for? There is some support for
interfacing with it in coreboot running on the host:
https://review.coreboot.org/cgit/coreboot.git/tree/src/drivers/aspeed

I believe this was added as part of the Asus KGPE-D16 OpenBMC porting
effort: https://www.raptorengineering.com/coreboot/kgpe-d16-
bmc-port-status.php
-- 
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[coreboot] New Defects reported by Coverity Scan for coreboot

[scan-admin]

Hi,

Please find the latest report on new defect(s) introduced to coreboot found 
with Coverity Scan.

3 new defect(s) introduced to coreboot found with Coverity Scan.


New defect(s) Reported-by: Coverity Scan
Showing 3 of 3 defect(s)


** CID 1381814:(BUFFER_SIZE)
/src/soc/intel/cannonlake/chip.c: 253 in platform_fsp_silicon_init_params_cb()
/src/soc/intel/cannonlake/chip.c: 255 in platform_fsp_silicon_init_params_cb()



*** CID 1381814:(BUFFER_SIZE)
/src/soc/intel/cannonlake/chip.c: 253 in platform_fsp_silicon_init_params_cb()
247 
248 /* PCI Express */
249 for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) {
250 if (config->PcieClkSrcUsage[i] == 0)
251 config->PcieClkSrcUsage[i] = PCIE_CLK_NOTUSED;
252 }
>>> CID 1381814:(BUFFER_SIZE)
>>> You might overrun the 16 byte destination string 
>>> "params->PcieClkSrcUsage" by writing the maximum 24 bytes from 
>>> "config->PcieClkSrcUsage".
253 memcpy(params->PcieClkSrcUsage, config->PcieClkSrcUsage,
254sizeof(config->PcieClkSrcUsage));
255 memcpy(params->PcieClkSrcClkReq, config->PcieClkSrcClkReq,
256sizeof(config->PcieClkSrcClkReq));
257 
258 /* eMMC and SD */
/src/soc/intel/cannonlake/chip.c: 255 in platform_fsp_silicon_init_params_cb()
249 for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) {
250 if (config->PcieClkSrcUsage[i] == 0)
251 config->PcieClkSrcUsage[i] = PCIE_CLK_NOTUSED;
252 }
253 memcpy(params->PcieClkSrcUsage, config->PcieClkSrcUsage,
254sizeof(config->PcieClkSrcUsage));
>>> CID 1381814:(BUFFER_SIZE)
>>> You might overrun the 16 byte destination string 
>>> "params->PcieClkSrcClkReq" by writing the maximum 24 bytes from 
>>> "config->PcieClkSrcClkReq".
255 memcpy(params->PcieClkSrcClkReq, config->PcieClkSrcClkReq,
256sizeof(config->PcieClkSrcClkReq));
257 
258 /* eMMC and SD */
259 params->ScsEmmcEnabled = config->ScsEmmcEnabled;
260 params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;

** CID 1381813:  Memory - corruptions  (OVERRUN)
/src/soc/intel/cannonlake/chip.c: 253 in platform_fsp_silicon_init_params_cb()



*** CID 1381813:  Memory - corruptions  (OVERRUN)
/src/soc/intel/cannonlake/chip.c: 253 in platform_fsp_silicon_init_params_cb()
247 
248 /* PCI Express */
249 for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) {
250 if (config->PcieClkSrcUsage[i] == 0)
251 config->PcieClkSrcUsage[i] = PCIE_CLK_NOTUSED;
252 }
>>> CID 1381813:  Memory - corruptions  (OVERRUN)
>>> Overrunning array "params->PcieClkSrcUsage" of 16 bytes by passing it 
>>> to a function which accesses it at byte offset 23 using argument "24UL". 
>>> [Note: The source code implementation of the function has been overridden 
>>> by a builtin model.]
253 memcpy(params->PcieClkSrcUsage, config->PcieClkSrcUsage,
254sizeof(config->PcieClkSrcUsage));
255 memcpy(params->PcieClkSrcClkReq, config->PcieClkSrcClkReq,
256sizeof(config->PcieClkSrcClkReq));
257 
258 /* eMMC and SD */

** CID 1381812:  Memory - corruptions  (OVERRUN)
/src/soc/intel/cannonlake/chip.c: 255 in platform_fsp_silicon_init_params_cb()



*** CID 1381812:  Memory - corruptions  (OVERRUN)
/src/soc/intel/cannonlake/chip.c: 255 in platform_fsp_silicon_init_params_cb()
249 for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) {
250 if (config->PcieClkSrcUsage[i] == 0)
251 config->PcieClkSrcUsage[i] = PCIE_CLK_NOTUSED;
252 }
253 memcpy(params->PcieClkSrcUsage, config->PcieClkSrcUsage,
254sizeof(config->PcieClkSrcUsage));
>>> CID 1381812:  Memory - corruptions  (OVERRUN)
>>> Overrunning array "params->PcieClkSrcClkReq" of 16 bytes by passing it 
>>> to a function which accesses it at byte offset 23 using argument "24UL". 
>>> [Note: The source code implementation of the function has been overridden 
>>> by a builtin model.]
255 memcpy(params->PcieClkSrcClkReq, config->PcieClkSrcClkReq,
256sizeof(config->PcieClkSrcClkReq));
257 
258 /* eMMC and SD */
259 params->ScsEmmcEnabled = config->ScsEmmcEnabled;
260 params->ScsEmmcHs400Enabled = 

[coreboot] ast2400 / ast2500

[Tirumalesh]

Hi,

Could some one please let me know, if corebott supports either AST2400/AST2500 
(ASpeed BMC)
If yes, how to test it with QEMU?

Thanks for the help,
Tirumalesh.-- 
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