[coreboot] Article in March Linux Journal on LinuxBoot
Hello! I just finished reading the article on LinuxBoot in the March issue of Linux Journal. And I am working on the one on a customized embedded Linux build, which is in the same issue. (There wasn't a February issue, or even ones for December last year or a January this year.) It does make a good point on the subject of how to properly boot Linux without a proprietary or even closed source BIOS used. And I remember reading Eric's article from the beginning of the Century and it did not go into enough detail. Ron and company that was a well written article. To be honest when I joined the original list for LinuxBIOS I had a plan to apply that to running a system for the purposes of running an emulator called Hercules, who rather effectively emulates the IBM mainframe. Sadly it was never realized. I believe given what was described in the article that I am a lot closer. - Gregg C Levine gregg.drw...@gmail.com "This signature fought the Time Wars, time and again." -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Coreboot events 2018
>When will the conference program be known? Also interested in this item. 90% I'll attend the event, at least for one or possible two days! Zoran ___ On Mon, Apr 23, 2018 at 9:34 PM, Alexey Borovikov wrote: > Thank! > When will it be possible to find out what reports and practices will be at > the conference? > When will the conference program be known? > Very interesting reports on Intel FSP and the prospects for its receipt in > the source code for the Intel Atom (Bay trail) family. > > From: Zaolin > Sent: Sunday, April 22, 2018 3:05 PM > To: Alexey Borovikov ; coreboot@coreboot.org > Subject: Re: [coreboot] Coreboot events 2018 > > > Last year I organized the European Coreboot Conference 2017 - > ecc2017.coreboot.org . > > and this year I am the organizer of the Open Source Firmware Conference 2018 > - www.osfc.io . > > So feel free to join us ;) > > > On 22.04.2018 13:36, Alexey Borovikov wrote: > > I want to visit in 2018 a conference on Coreboot. For the purpose of > planning a business trip, please inform future events and venue? > > > > > -- > coreboot mailing list: coreboot@coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Coreboot events 2018
Thank! When will it be possible to find out what reports and practices will be at the conference? When will the conference program be known? Very interesting reports on Intel FSP and the prospects for its receipt in the source code for the Intel Atom (Bay trail) family. From: Zaolin Sent: Sunday, April 22, 2018 3:05 PM To: Alexey Borovikov ; coreboot@coreboot.org Subject: Re: [coreboot] Coreboot events 2018 Last year I organized the European Coreboot Conference 2017 - ecc2017.coreboot.org . and this year I am the organizer of the Open Source Firmware Conference 2018 - www.osfc.io . So feel free to join us ;) On 22.04.2018 13:36, Alexey Borovikov wrote: I want to visit in 2018 a conference on Coreboot. For the purpose of planning a business trip, please inform future events and venue? -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Thinkpad X230, Coreboot 4.7 + SeaBIOS 1.11.0 flashing, memtest86+ 5.01, fancontrol and WoL
Martin Kepplinger writes: >> In short: enable Wake On Lan on AC power in Lenovo BIOS, disconnect AC >> and battery, insert live Ethernet cable, connect AC, Ethernet port >> should go live (LEDs). Connect your external programmer _but leave >> VCC/3.3V line disconnected_ (i.e. connect all the data lines and the >> ground, but not the VCC). The Ethernet port is on the same power line >> as >> MX chips, hence flashing with RPi/BBB with VCC disconnected will work >> as >> with older models. > > I've flashed 4 or 5 of these, and on 1 or 2 the WoL powering would > simply not work. > flashrom with spispeed 128 always did. Always set an SPI speed. I tried exactly that, but my RPi 3 B+ is unable to feed the chips anyway. With 1A USB power supply RPi's power LED goes out when attaching to the mainboard (but, curiously, the RPi still responds over ssh), flashrom doesn't work. And even when running on 2A Samsung USB power supply with which the RPi feels ok when connected to the mainboard flashrom still can't detect the chip. Also the RPi voltage regulator is very poor, it gives 3.6V instead of 3.3V without a load and 2.9V when connected to the mainboard =/. So it's too high at the moment you attach it and too low to drive the chips. I prefer the WoL method. Cheers, Jan -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Thinkpad X230, Coreboot 4.7 + SeaBIOS 1.11.0 flashing, memtest86+ 5.01, fancontrol and WoL
Duncan writes: > The wiki page says many things. I've edited the page for clarity about > that and removed the odd Buspirate-specific instructions (I am not sure > why BusPirate users can't just look at Flashrom wiki etc). > > In general don't use external power for in-system-programming (ISP) on > the X230 (or any other recent Intel laptop) - the boards in question > really weren't designed to have flash powered that way. >> ... > > Do NOT power system flash externally as well as with the WoL feature - > this can only do bad things to the board. This last paragraph is unclear. You want to say that I should only power using the WoL feature, not external power, on all the models, right? >> The only difference with older models is that you have to cut >> coreboot.rom into 8M and 4M pieces and flash them separately. (You can >> flash the top 4M only, but then, apparently, you wouldn't be able to >> reflash the ME region internally). > > There isn't actually a difference to older models, except that they've > split system flash over two flash chips. The BIOS region (the area we > may install Coreboot on) on the X230 is actually 7MiB, not 4MiB. It's > just that the 4MiB can be used on its own for Coreboot, without having > to touch the 8MiB flash chip. If you look at the flash descriptor, > you'll see that the BIOS region is described as 7MiB, that is, leading > from the last 3MiB of the 8MiB flash chip to the end of the 4MiB flash > chip. Yes, I noticed that. I seems that between x220 and x230 ME region got a few KB too fat for 8M and Lenovo had to add a whole new 4M SIP chip just for those several KB. > If you want to make use of the whole 7MiB (without changing the size of > other regions per se), either: > 1. Flash internally > 2. Build a Coreboot image using the flash descriptor and other Intel > blobs dumped from your system, and then split the image e.g. using dd so > that you can change flash contents of both the 8MiB and 4MiB flash chips. But I dump after every reboot and I see ME writing to the flash. It looks as if it logs something there in some binary format (it incrementally writes to higher addresses on every dump). To flash internally with a full ME running seems as a bad idea. > Alternatively, you could replace the two flash chips with a single 16MiB > flash chip (as I understand it, this is the largest size supported by > the SPI controller), which is easier to use, and you'll have more space > for payloads (some payloads like a Linux payload can be very large, and > Linux payloads are very flexible and may be fun to play with). That's nice to know. >> # Wake on LAN issue/question >> >> After flashing coreboot I expected "Wake on Lan on AC connect" to stop >> working since it was configured in vendor BIOS, but it still works. Why? >> What code enables it? Can I disable it? How? >> >> Also, does WoL need the GBE/ME blobs to work? It is kinda useful that it >> still works with coreboot since and I can now reflash with impunity >> using the same WoL method if I brick the ROM. But I want to know if I >> would be able to clean the ME region and wipe the GBE region (and use >> USB Ethernet instead) and still use the WoL trick for flashing. > > One thing to note is that the GbE "blob" isn't really a blob as one > would think. It is configuration data (which is arguably not possible to > copyright) and thus should be possible to generate. It's not executable > as far as I understand. > > I'd honestly not recommend using USB ethernet - the onboard NIC performs > well and is reliable. > > There are no issues with using the WoL feature and "cleaning" the ME > region. Some users have reported "cleaning" the ME region makes suspend > cease to work, but I've not experienced this. It may be kernel/OS > version or they may have installed their dump that is corrupted in some > way. It seems like something fairly difficult to debug. > > It's possible that they are encountering issues with the ME not working > with their dumped firmware image. In general, it is best to flash back a > "factory fresh" firmware image (perhaps, in this case, "cleaned" with > the ME Cleaner program). It is not clear to me why this is, but this is > what some users have reported - as far as I understand, the ME itself > may hold some sort of persistent state. Spooky. It does hold some state, as I noted above. Spooky indeed. https://www.troopers.de/downloads/troopers17/TR17_ME11_Static.pdf is for ME11 and Thinkpad x230 is ME8, but the slide #11 there lists "FLOG" "Flash Log" ME region. So it does log something in ME11. I couldn't find much descriptive research on ME < 11. I'd like to read something that describes what the BUP stage does in ME8, but http://blog.ptsecurity.com/2017/08/disabling-intel-me.html describes what ME11 BUP does, and I'm confused: >>> Stage 1 >>> During the initial stage, the sfs internal diagnostic file system >>> (SUSRAM FS, a file system located in non-volatile memory) is >>> created
[coreboot] [RFC] Building the documentation with Sphinx
Hello coreboot community, recently, I tried to use Hugo view some documentation in HTML form, but I couldn't get it to work properly (some pages 404'd when they shouldn't). So I decided to look into using Sphinx[1] again. I configured[2] Sphinx and the recommonmark Markdown parser for our Documentation directory. The result can be viewed here: https://neuschaefer.github.io/coreboot/ Advantages of this approach: - The "readthedocs" theme, which I used has a useful navigation sidebar and allows full navigation without JavaScript (the search box does need JavaScript, because the search is performed on the client side.) - The top-level table of contents (i.e. the navbar) is generated from a markdown file[3] rather than a special configuration file[4]. - The necessary packages (sphinx-doc, python-recommonmark, python-sphinx-rtd-theme) are available in Debian; but so is Hugo. Disadvantages: - recommonmark does not support tables[5]. This is a limitation of the CommonMark[6] dialect of Markdown. We'd have to use HTML tables (...) instead. - If we decide to switch https://coreboot.org/Documentation to Sphinx, that would mean some work for the admins, like any other change in infrastructure. Possible migration path: - Merge Sphinx support - Look how well it works, and decide whether it's worth keeping, or drop it - Switch https://coreboot.org/Documentation (or https://doc.coreboot.org/?) to Sphinx - Remove hugo support Overall, I like this setup, and I'd like https://coreboot.org/Documentation to switch to it, but it has a few limitations. I'd like to hear your opinions! Thanks, Jonathan Neuschäfer [1]: http://www.sphinx-doc.org/en/stable/ [2]: https://review.coreboot.org/#/c/coreboot/+/25787/ [3]: https://review.coreboot.org/#/c/coreboot/+/25787/1/Documentation/index.md [4]: https://review.coreboot.org/cgit/coreboot.git/tree/util/hugo/config.toml#n30 [5]: https://github.com/rtfd/recommonmark/issues/3 [6]: http://commonmark.org/ signature.asc Description: PGP signature -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH 0/5] coreboot table bus and framebuffer driver
On Wed, Mar 14, 2018 at 09:22:04PM +, Julius Werner wrote: > [resend in plain text] > > > It would be great to get some of the google developers to ack these, as > > this touches their code... > > From the coreboot point of view I guess we're fine with it since it claims > to maintain all of the existing functionality. It's just changing the > kernel-level plumbing for these drivers and I don't really have the > expertise to comment on whether this is better or worse than the old code > (maybe Dmitry or Guenter will?). It seems a little odd to me to call this a > "bus", but if we think that's the most fitting abstraction the kernel has > for it, I'm okay with that. All I care about is that it will work (in all > combinations... e.g. regardless of probe order and even if some parts are > compiled as modules and loaded/unloaded at runtime). Thanks for the response, patches are all now queued up. greg k-h -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Thinkpad X230, Coreboot 4.7 + SeaBIOS 1.11.0 flashing, memtest86+ 5.01, fancontrol and WoL
Am 22.04.2018 21:09 schrieb Jan Malakhovski: Hi. # Primary TOC * Thinkpad X230 seems to be a fairly common target for coreboot, but I though that another recent success report wouldn't hurt. * Flashing with "WoL on AC" trick (missing on the wiki). * Failure report on using Debian's memtest86+ and success report on using coreboot's memtest86+. * The laptop also overheats while running memtest86+ with coreboot (but not vendor BIOS) which, I think, is a bug/missing feature in coreboot. * There's also a Wake on LAN issue/question. # The Success Report I flashed Thinkpad X230 with Coreboot tagged 4.7 (fd470f7163709c1022ee6185134a2387812774ec) with a config that has the following diff from the default 4.7 X230 config (made by `cat configs/builder/config.lenovo_x230 > .config ; make menuconfig` followed by ): --- config.x230.v4.7.def +++ config.x230.v4.7.my @@ -11,7 +11,7 @@ CONFIG_CBFS_PREFIX="fallback" CONFIG_COMPILER_GCC=y # CONFIG_COMPILER_LLVM_CLANG is not set -# CONFIG_ANY_TOOLCHAIN is not set +CONFIG_ANY_TOOLCHAIN=y # CONFIG_CCACHE is not set # CONFIG_FMD_GENPARSER is not set # CONFIG_UTIL_GENPARSER is not set @@ -112,6 +112,7 @@ CONFIG_MAX_CPUS=8 CONFIG_CACHE_ROM_SIZE_OVERRIDE=0x0 CONFIG_CBFS_SIZE=0x10 +CONFIG_PAYLOAD_CONFIGFILE="" CONFIG_VGA_BIOS_ID="8086,0166" CONFIG_ONBOARD_VGA_IS_PRIMARY=y CONFIG_DIMM_SPD_SIZE=256 @@ -136,8 +137,8 @@ CONFIG_FMDFILE="" CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 # CONFIG_DRIVERS_UART_8250IO is not set -CONFIG_IFD_BIN_PATH="site-local/descriptor.bin" -CONFIG_ME_BIN_PATH="site-local/me.bin" +CONFIG_IFD_BIN_PATH="site-local/flashregion_0_flashdescriptor.bin" +CONFIG_ME_BIN_PATH="site-local/flashregion_2_intel_me.bin" # CONFIG_BOARD_LENOVO_G505S is not set # CONFIG_BOARD_LENOVO_L520 is not set # CONFIG_BOARD_LENOVO_R400 is not set @@ -338,6 +339,7 @@ # CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y +CONFIG_SEABIOS_PS2_TIMEOUT=3000 CONFIG_H8_BEEP_ON_DEATH=y CONFIG_H8_FLASH_LEDS_ON_DEATH=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set @@ -348,9 +350,9 @@ # Intel Firmware # # CONFIG_EM100 is not set -# CONFIG_CHECK_ME is not set +CONFIG_CHECK_ME=y # CONFIG_USE_ME_CLEANER is not set -CONFIG_GBE_BIN_PATH="site-local/gbe.bin" +CONFIG_GBE_BIN_PATH="site-local/flashregion_3_gbe.bin" # CONFIG_HAVE_EC_BIN is not set # CONFIG_MAINBOARD_HAS_CHROMEOS is not set # CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set @@ -621,17 +623,31 @@ # # Payload # -CONFIG_PAYLOAD_NONE=y +# CONFIG_PAYLOAD_NONE is not set # CONFIG_PAYLOAD_ELF is not set # CONFIG_PAYLOAD_BAYOU is not set # CONFIG_PAYLOAD_FILO is not set # CONFIG_PAYLOAD_GRUB2 is not set -# CONFIG_PAYLOAD_SEABIOS is not set +CONFIG_PAYLOAD_SEABIOS=y # CONFIG_PAYLOAD_UBOOT is not set # CONFIG_PAYLOAD_LINUX is not set # CONFIG_PAYLOAD_TIANOCORE is not set +CONFIG_PAYLOAD_FILE="payloads/external/SeaBIOS/seabios/out/bios.bin.elf" +CONFIG_SEABIOS_STABLE=y +# CONFIG_SEABIOS_MASTER is not set +# CONFIG_SEABIOS_REVISION is not set +# CONFIG_SEABIOS_THREAD_OPTIONROMS is not set +CONFIG_SEABIOS_VGA_COREBOOT=y +CONFIG_SEABIOS_BOOTORDER_FILE="" +CONFIG_PAYLOAD_VGABIOS_FILE="payloads/external/SeaBIOS/seabios/out/vgabios.bin" +CONFIG_SEABIOS_DEBUG_LEVEL=-1 + +# +# Using default SeaBIOS log level +# CONFIG_PAYLOAD_OPTIONS="" # CONFIG_PXE is not set +CONFIG_COMPRESSED_PAYLOAD_LZMA=y # CONFIG_PAYLOAD_IS_FLAT_BINARY is not set You should probably ignore CONFIG_ANY_TOOLCHAIN=y since I simply built gcc 6.3 with coreboot patches via nix package manager and then built coreboot using that, so I'm using exactly the same compiler, only packaged via nix (because it was simpler for me this way). # Flashing with "WoL on AC" trick A couple of words on reading/flashing X230's SPI Neither Raspberry Pi 3 B+, nor Beagle Bone Black can supply enough power to feed the MX chips to the board, so the wiki https://www.coreboot.org/Board:lenovo/x230 both recommends an external power supply and warns against using it at the same time (as it can brick the board). But there's a much simpler and safer method described in https://www.bios-mods.com/forum/Thread-REQUEST-Lenovo-Thinkpad-X230-Whitelist-removal?pid=91134#pid91134 and https://www.bios-mods.com/forum/Thread-REQUEST-Lenovo-Thinkpad-X230-Whitelist-removal?pid=91787#pid91787 that doesn't require an external power supply. In short: enable Wake On Lan on AC power in Lenovo BIOS, disconnect AC and battery, insert live Ethernet cable, connect AC, Ethernet port should go live (LEDs). Connect your external programmer _but leave VCC/3.3V line disconnected_ (i.e. connect all the data lines and the ground, but not the VCC). The Ethernet port is on the same power line as MX chips, hence flashing with RPi/BBB with VCC disconnected will work as with older models. I've flashed 4 or 5 of these, and on 1 or 2 the WoL powering would simply not work. flashrom with spispeed 128 always did. Always set an SPI speed. The only difference with older models is that you have to cut
Re: [coreboot] Thinkpad X230, Coreboot 4.7 + SeaBIOS 1.11.0 flashing, memtest86+ 5.01, fancontrol and WoL
Hi Jan, Jan Malakhovski: > Hi. > > # Primary TOC > > * Thinkpad X230 seems to be a fairly common target for coreboot, but I > though that another recent success report wouldn't hurt. > > * Flashing with "WoL on AC" trick (missing on the wiki). > > * Failure report on using Debian's memtest86+ and success report on > using coreboot's memtest86+. > > * The laptop also overheats while running memtest86+ with coreboot (but > not vendor BIOS) which, I think, is a bug/missing feature in coreboot. > > * There's also a Wake on LAN issue/question. > > # The Success Report > > I flashed Thinkpad X230 with Coreboot tagged 4.7 > (fd470f7163709c1022ee6185134a2387812774ec) with a config that has the > following diff from the default 4.7 X230 config (made by `cat > configs/builder/config.lenovo_x230 > .config ; make menuconfig` followed > by ): > > --- config.x230.v4.7.def > +++ config.x230.v4.7.my > @@ -11,7 +11,7 @@ > CONFIG_CBFS_PREFIX="fallback" > CONFIG_COMPILER_GCC=y > # CONFIG_COMPILER_LLVM_CLANG is not set > -# CONFIG_ANY_TOOLCHAIN is not set > +CONFIG_ANY_TOOLCHAIN=y > # CONFIG_CCACHE is not set > # CONFIG_FMD_GENPARSER is not set > # CONFIG_UTIL_GENPARSER is not set > @@ -112,6 +112,7 @@ > CONFIG_MAX_CPUS=8 > CONFIG_CACHE_ROM_SIZE_OVERRIDE=0x0 > CONFIG_CBFS_SIZE=0x10 > +CONFIG_PAYLOAD_CONFIGFILE="" > CONFIG_VGA_BIOS_ID="8086,0166" > CONFIG_ONBOARD_VGA_IS_PRIMARY=y > CONFIG_DIMM_SPD_SIZE=256 > @@ -136,8 +137,8 @@ > CONFIG_FMDFILE="" > CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 > # CONFIG_DRIVERS_UART_8250IO is not set > -CONFIG_IFD_BIN_PATH="site-local/descriptor.bin" > -CONFIG_ME_BIN_PATH="site-local/me.bin" > +CONFIG_IFD_BIN_PATH="site-local/flashregion_0_flashdescriptor.bin" > +CONFIG_ME_BIN_PATH="site-local/flashregion_2_intel_me.bin" > # CONFIG_BOARD_LENOVO_G505S is not set > # CONFIG_BOARD_LENOVO_L520 is not set > # CONFIG_BOARD_LENOVO_R400 is not set > @@ -338,6 +339,7 @@ > # > CONFIG_EC_ACPI=y > CONFIG_EC_LENOVO_H8=y > +CONFIG_SEABIOS_PS2_TIMEOUT=3000 > CONFIG_H8_BEEP_ON_DEATH=y > CONFIG_H8_FLASH_LEDS_ON_DEATH=y > # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set > @@ -348,9 +350,9 @@ > # Intel Firmware > # > # CONFIG_EM100 is not set > -# CONFIG_CHECK_ME is not set > +CONFIG_CHECK_ME=y > # CONFIG_USE_ME_CLEANER is not set > -CONFIG_GBE_BIN_PATH="site-local/gbe.bin" > +CONFIG_GBE_BIN_PATH="site-local/flashregion_3_gbe.bin" > # CONFIG_HAVE_EC_BIN is not set > # CONFIG_MAINBOARD_HAS_CHROMEOS is not set > # CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set > @@ -621,17 +623,31 @@ > # > # Payload > # > -CONFIG_PAYLOAD_NONE=y > +# CONFIG_PAYLOAD_NONE is not set > # CONFIG_PAYLOAD_ELF is not set > # CONFIG_PAYLOAD_BAYOU is not set > # CONFIG_PAYLOAD_FILO is not set > # CONFIG_PAYLOAD_GRUB2 is not set > -# CONFIG_PAYLOAD_SEABIOS is not set > +CONFIG_PAYLOAD_SEABIOS=y > # CONFIG_PAYLOAD_UBOOT is not set > # CONFIG_PAYLOAD_LINUX is not set > # CONFIG_PAYLOAD_TIANOCORE is not set > +CONFIG_PAYLOAD_FILE="payloads/external/SeaBIOS/seabios/out/bios.bin.elf" > +CONFIG_SEABIOS_STABLE=y > +# CONFIG_SEABIOS_MASTER is not set > +# CONFIG_SEABIOS_REVISION is not set > +# CONFIG_SEABIOS_THREAD_OPTIONROMS is not set > +CONFIG_SEABIOS_VGA_COREBOOT=y > +CONFIG_SEABIOS_BOOTORDER_FILE="" > +CONFIG_PAYLOAD_VGABIOS_FILE="payloads/external/SeaBIOS/seabios/out/vgabios.bin" > +CONFIG_SEABIOS_DEBUG_LEVEL=-1 > + > +# > +# Using default SeaBIOS log level > +# > CONFIG_PAYLOAD_OPTIONS="" > # CONFIG_PXE is not set > +CONFIG_COMPRESSED_PAYLOAD_LZMA=y > # CONFIG_PAYLOAD_IS_FLAT_BINARY is not set > > You should probably ignore CONFIG_ANY_TOOLCHAIN=y since I simply built > gcc 6.3 with coreboot patches via nix package manager and then built > coreboot using that, so I'm using exactly the same compiler, only > packaged via nix (because it was simpler for me this way). > > # Flashing with "WoL on AC" trick > > A couple of words on reading/flashing X230's SPI > > Neither Raspberry Pi 3 B+, nor Beagle Bone Black can supply enough power > to feed the MX chips to the board, so the wiki > https://www.coreboot.org/Board:lenovo/x230 both recommends an external > power supply and warns against using it at the same time (as it can > brick the board). The wiki page says many things. I've edited the page for clarity about that and removed the odd Buspirate-specific instructions (I am not sure why BusPirate users can't just look at Flashrom wiki etc). In general don't use external power for in-system-programming (ISP) on the X230 (or any other recent Intel laptop) - the boards in question really weren't designed to have flash powered that way. > > But there's a much simpler and safer method described in > https://www.bios-mods.com/forum/Thread-REQUEST-Lenovo-Thinkpad-X230-Whitelist-removal?pid=91134#pid91134 > and > https://www.bios-mods.com/forum/Thread-REQUEST-Lenovo-Thinkpad-X230-Whitelist-removal?pid=91787#pid91787 > that doesn't require an external power supply. > > In short: enable Wake On L
