Re: [coreboot] Using linux as payload

2018-08-20 Thread Youness Alaoui
Hi,

I might not be the best one to answer your question, but here are my thoughts :
- the "unknown type 'payload'" error is probably because cbfs changed
the type name from "payload' to "simple elf" since you can add elfs in
there that are not actual 'payloads'. I think though that it
auto-changed the file type to 'simple elf', since you can see in the
cbfs print :
fallback/payload   0xc7a80simple elf5244700 none
So the payload is added, it has type "simple elf" and is 5.2MB (which
is the bzImage + initrd.cpio size).
Then in your cbmem log you can see that it did find the payload and
that it decompressed all the sections and everything seems fine :
CBFS: Locating 'fallback/payload'
CBFS: Found @ offset c7b80 size 5006d5
[...]

And then it jumps into it (i.e: it executes the payload) :
Jumping to boot code at 0004(8fe11000)

The reason that's the last messages you see is simply because linux
does not print any messages to cbmem (SeaBIOS does, and if you look at
your old logs, you'd see right after that "jumping to boot code"
there's the SeaBIOS debug messages starting).

So I think it's all good for you, but your problem is actually with
your linux (Heads) configuration itself, you probably simply do not
have the right graphics driver enabled in the kernel, so linux boots
but it doesn't initialize the GPU so nothing appears. You can either
find and enable your GPU driver in the kernel and rebuild Heads, or
you can tell coreboot to initialize the gpu (either with the GOP
driver+VBT or by running the option rom) and tell it to initialize the
VGA framebuffer (probably in text mode though I'm not sure) or
whatever is needed to actually get some graphics output.
I remember trying a few different options and configurations for the
Librem and in the end, I simply removed the vgabios/vbt from coreboot,
told coreboot not to initialize the graphics, and added the i915
kernel driver to heads and that was all that was needed. Once heads
booted, the kernel driver initialized the graphics and that's it.

I hope that helps,
Youness.

On Sat, Aug 18, 2018 at 4:51 AM Jorge Fernandez Monteagudo
 wrote:
>
> Hi all!
>
>
> I have a coreboot from master git working ok in my AMD Bettong demoboard with 
> SeaBIOS and now
>
> I'm trying to use a bzImage (2651888 bytes) and initrd.cpio.xz (2604544 
> bytes) generated by Heads in
>
> order to test the linux payload.
>
>
> When I compile the coreboot I see:
>
>
> Created CBFS (capacity = 8388056 bytes)
> CBFS   apu/amdfw
> CBFS   AGESA
> CBFS   fallback/romstage
> CBFS   fallback/ramstage
> CBFS   cmos_layout.bin
> CBFS   pci1002,9874.rom
> CBFS   fallback/dsdt.aml
> CBFS   fallback/payload
> W: Unknown type 'payload' ignored
> CBFS   coreboot.rom
> CBFSLAYOUT  coreboot.rom
>
> This image contains the following sections that can be manipulated with this 
> tool:
>
> 'COREBOOT' (CBFS, size 8388096, offset 512)
>
> It is possible to perform either the write action or the CBFS add/remove 
> actions on every section listed above.
> To see the image's read-only sections as well, rerun with the -w option.
> CBFSPRINT  coreboot.rom
>
> Name   Offset Type   Size   Comp
> cbfs master header 0x0cbfs header32 none
> fallback/romstage  0x80   stage   32220 none
> fallback/ramstage  0x7ec0 stage   56689 none
> cmos_layout.bin0x15c80cmos_layout  1516 none
> fallback/dsdt.aml  0x162c0raw  6673 none
> (empty)0x17d40null32856 none
> apu/amdfw  0x1fdc0raw622592 none
> pci1002,9874.rom   0xb7e00optionrom   64512 none
> fallback/payload   0xc7a80simple elf5244700 none
> (empty)0x5c8200   null   228248 none
> AGESA  0x5ffdc0   raw690436 none
> (empty)0x6a8740   null  1405592 none
> bootblock  0x7ffa00   bootblock 912 none
>
> Built amd/bettong (FP4)
>
>
> The "W: Unknown type 'payload' ignored" message is ok? Maybe the payload 
> doesn't fit in the
>
> coreboot image?
>
>
> Now when I boot the board the last messages I can see on serial console are:
>
>
> ...
>
> Writing table forward entry at 0x0500
> Wrote coreboot table at: 0500, 0x10 bytes, checksum 5ffd
> Writing coreboot table at 0x8fe11000
>  0. -0fff: CONFIGURATION TABLES
>  1. 1000-0009: RAM
>  2. 000c-8fdd9fff: RAM
>  3. 8fdda000-8fff: CONFIGURATION TABLES
>  4. 9000-cfff: RESERVED
>  5. f800-fbff: RESERVED
>  6. fed4-fed44fff: RESERVED
>  7. 0001-00022eff: 

Re: [coreboot] How to send a patch?

2018-08-20 Thread Th3Fanbus .
Hello Jorge,

You can submit the patch yourself, check out
https://doc.coreboot.org/lessons/index.html as a reference.

Regards,

Angel Pons Pons

On Mon, Aug 20, 2018, 19:22 Jorge Fernandez Monteagudo 
wrote:

> Hi
>
> I would like to contribute with some questions I've found trying to
> running an AMD Bettong board.
>
> Attached is a little patch to enable the SATA and to set the
> domain_acpi_name... If someone could review it and upload it to
> repository...
>
> Thanks!
> --
> coreboot mailing list: coreboot@coreboot.org
> https://mail.coreboot.org/mailman/listinfo/coreboot
-- 
coreboot mailing list: coreboot@coreboot.org
https://mail.coreboot.org/mailman/listinfo/coreboot

[coreboot] How to send a patch?

2018-08-20 Thread Jorge Fernandez Monteagudo
Hi

I would like to contribute with some questions I've found trying to running an 
AMD Bettong board.

Attached is a little patch to enable the SATA and to set the 
domain_acpi_name... If someone could review it and upload it to repository...

Thanks!
diff -uNr coreboot_saved/src/mainboard/amd/bettong/BiosCallOuts.c coreboot/src/mainboard/amd/bettong/BiosCallOuts.c
--- coreboot_saved/src/mainboard/amd/bettong/BiosCallOuts.c	2018-08-19 18:31:13.155272026 +0200
+++ coreboot/src/mainboard/amd/bettong/BiosCallOuts.c	2018-08-20 19:05:53.567150909 +0200
@@ -86,6 +86,9 @@
 		FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
 		FchParams_reset->FchReset.Xhci1Enable = FALSE;
 		FchParams_reset->EarlyOemGpioTable = oem_bettong_gpio;
+		/* sata configuration */
+		FchParams_reset->FchReset.SataEnable = (CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 2);
+
 	} else if (StdHeader->Func == AMD_INIT_ENV) {
 		FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData;
 		printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
@@ -102,7 +105,6 @@
 		FchParams_env->Usb.Xhci1Enable = FALSE;
 		FchParams_env->Usb.USB30PortInit = 8; /* 8: If USB3 port is unremoveable. */
 
-		/* sata configuration */
 		/* SD configuration */
 		/* Rev F has an on-board eMMC, which only supports SD 2.0 */
 		if (board_id() == 'F') {
diff -uNr coreboot_saved/src/northbridge/amd/pi/00660F01/northbridge.c coreboot/src/northbridge/amd/pi/00660F01/northbridge.c
--- coreboot_saved/src/northbridge/amd/pi/00660F01/northbridge.c	2018-08-19 18:31:13.299272024 +0200
+++ coreboot/src/northbridge/amd/pi/00660F01/northbridge.c	2018-08-20 19:11:55.335147317 +0200
@@ -777,12 +777,21 @@
 	}
 }
 
+static const char *domain_acpi_name(const struct device *dev)
+{
+	if (dev->path.type == DEVICE_PATH_DOMAIN)
+		return "PCI0";
+
+	return NULL;
+}
+
 static struct device_operations pci_domain_ops = {
 	.read_resources	  = domain_read_resources,
 	.set_resources	  = domain_set_resources,
 	.enable_resources = domain_enable_resources,
 	.init		  = NULL,
 	.scan_bus	  = pci_domain_scan_bus,
+	.acpi_name= domain_acpi_name,
 };
 
 static void sysconf_init(struct device *dev) // first node
-- 
coreboot mailing list: coreboot@coreboot.org
https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] F2A85M coreboot+seabios Radeons Cards

2018-08-20 Thread Mike Banon
Hi Nekoboi, could you please attach some logs to your next message,
when a Radeon card is inserted to your system?
1) lspci -vv
2) "dmesg" kernel log
3) maybe some other logs that you think will help us to help you better
Best regards,
Mike Banon

On Mon, Aug 20, 2018 at 12:42 AM, kinky_nekoboi
 wrote:
> I can not get any Radeons Addon card working together with
> Coreboot+Seabios on this board. The cards are listed in lspci output but
> no signal to the monitor.
>
> A GF 8400GS works just fine.
>
>
> Any Ideas ?
>
>
>
> --
> coreboot mailing list: coreboot@coreboot.org
> https://mail.coreboot.org/mailman/listinfo/coreboot

-- 
coreboot mailing list: coreboot@coreboot.org
https://mail.coreboot.org/mailman/listinfo/coreboot