[coreboot] Re: HPET MSI/FSB on AMD 16h

[awokd via coreboot]

Michal Zygowski:


On 01.07.2019 14:53, Andriy Gapon wrote:



It appears that HPET MSI support
is disabled on some platforms by default:

src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/Family/Hudson2/EnvDefHudson2.c:
   TRUE,// HpetMsiDis


FWIW, I hardcoded the above to FALSE, recompiled, and reflashed my 
f15tn. It caused Qubes to run about half as fast. I checked the logs and 
didn't see any errors to explain why. I then changed it back to TRUE and 
HPET itself to FALSE (and recompiled/reflashed). Normal speed came back, 
XEN Platform timer changed from HPET to ACPI, and MSI is still enabled 
for some of the PCI devices. For example, the video controller on 
00:01.0 is IRQ 57 and capability [a0] is MSI: Enable+.

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[coreboot] Re: Does Coreboot support the following options to enable/disable?

[Ranga Rao]

Hi,



As these features are processor/SoC specific and they are part of FSPM, they 
should be configurable

during fsp early init in coreboot, though you may not find a KConfig option to 
enable/disable



Do you have access to them in fsp_early_init through fsp_upd_data?



Regards

Ranga



-Original Message-
From: ashmita.chakrabo...@ltts.com 
Sent: Tuesday 2 July 2019 07:34
To: coreboot@coreboot.org
Subject: [coreboot] Does Coreboot support the following options to 
enable/disable?



Does the coreboot support the following options to enable/disable:



HyperThreading- Disabled

Execute Disable Bit  -  Enabled

Intel Virtualization Tech- Enabled

Intel (R) TXT-   Disabled

Enhanced Error Containment Mode -Disabled

MLC Streamer   -Enabled

MLC Spatial Prefetcher   -Enabled

DUC Data Prefetcher  -Enabled

DUC Instruction Prefetcher-Enabled

LLC Prefetch  - Enabled

Intel Configurable TDB -Enabled

TDP Level  -level 2





Please let me know.



Thanks in advance.



Regards,

Ashmita Chakraborty

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[coreboot] Re: Question about blobs

[Jorge Fernandez Monteagudo]

Hi Kyösti! Thanks for the info!

>AMD contracted SilverBack for the tasks on StoneyRidge (and
>MerlinFalcon apparently). The source is a heavily modified StoneyPI
>package. You may get the unmodified one from AMD reps under NDA. Or
>pay SilverBack for the development you would be more capable of doing
>yourself, and you still might not get a license that allows
>distributing the work. There was a promise of scrubbing and
>relicensing StoneyPI source but... Let's just say legalities messed it
>up, I don't have the details.

Yes, the AMD reps we're in touch answer me to get in touch with SilverBack to 
get support :(
We've been able to get a more recent StoneyPI_1_3_0_A.ZIP under NDA because 
I've seen
this version fixed the issue:

EMBSWDEV-4487: System is not booting when memory is connected only to DIMM 1 
slot

maybe related with our problem, but I don't know how to integrate this code 
into coreboot...
And if you say that the current work in coreboot is from a heavily modified 
base from SilverBack
I don't have any chance to make it work...

>As for the the other blobs (MullinsPI, CarrizoPI, KaveriPI), those
>were either built at SAGE (R.I.P.) or AMD AES (R.I.P.) and I have been
>told the repositories and toolchains were never officially transferred
>to SilverBack's possession. In other words, even if you paid,
>SilverBack is not likely to work on those.

Then, no more options to get a working BIOS than SilverBack?

>I believe we have talked before. Maybe it was about CarrizoPI? I was
>asking for commercial adopters around coreboot and binaryPI, in
>attempts to get to the same negotiation table with AMD management. Did
>You or Your manager ever respond?

Yes. I began asking in the coreboot mailing list about the Bettong mainboard. I 
added TPM support
and tianocore to that demoboard. I remember the email and I answered it giving 
my support because
we thought coreboot is the way to go to support our custom board.

Regards,
Jorge

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[coreboot] Re: Question about blobs

[Kyösti Mälkki]

On Tue, Jul 2, 2019 at 1:01 PM Jorge Fernandez Monteagudo
 wrote:
>
> Hi all,
>
> I would like to know the source of the AGESA.bin blobs I've seen in the 
> 3rdparty directory. For instance, the 
> '3rdparty/blobs/pi/amd/00670F00/FP4/AGESA.bin'. Is it generated by AMD? Is it 
> compiled from a NDA file by a coreboot developer?

AMD contracted SilverBack for the tasks on StoneyRidge (and
MerlinFalcon apparently). The source is a heavily modified StoneyPI
package. You may get the unmodified one from AMD reps under NDA. Or
pay SilverBack for the development you would be more capable of doing
yourself, and you still might not get a license that allows
distributing the work. There was a promise of scrubbing and
relicensing StoneyPI source but... Let's just say legalities messed it
up, I don't have the details.

As for the the other blobs (MullinsPI, CarrizoPI, KaveriPI), those
were either built at SAGE (R.I.P.) or AMD AES (R.I.P.) and I have been
told the repositories and toolchains were never officially transferred
to SilverBack's possession. In other words, even if you paid,
SilverBack is not likely to work on those.

I believe we have talked before. Maybe it was about CarrizoPI? I was
asking for commercial adopters around coreboot and binaryPI, in
attempts to get to the same negotiation table with AMD management. Did
You or Your manager ever respond?


Kyösti
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[coreboot] Question about blobs

[Jorge Fernandez Monteagudo]

Hi all,


I would like to know the source of the AGESA.bin blobs I've seen in the 
3rdparty directory. For instance, the 
'3rdparty/blobs/pi/amd/00670F00/FP4/AGESA.bin'. Is it generated by AMD? Is it 
compiled from a NDA file by a coreboot developer?


Thanks!

Jorge

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