date:20190703

[coreboot] [AMD 16h / ASUS AM1I-A] 1866MHz CL9 RAM runs only as 1333MHz CL9 - how to fix?

2019-07-03 Thread Mike Banon

A pair of 1866MHz CL9 RAM modules* runs only as 1333MHz CL9 on 16h
AM1I-A with coreboot is installed, but worked faster when a
proprietary UEFI was installed. To fix this "turtle RAM" coreboot
problem I tried to play with buildOpts.c -
https://review.coreboot.org/c/coreboot/+/33920 , but the things like
"#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY" sadly did not
help.

Any ideas how to improve the RAM speeds? How I can force this RAM to run faster?

Best regards,
Mike Banon

[*] Crucial Ballistix Tactical Series DDR3 1866MHz CL9 (PC3-14900
9-9-9-24) UDIMM 240-Pin modules, part number BLT8G3D1869DT1TX0
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[coreboot] Re: HPET MSI/FSB on AMD 16h

2019-07-03 Thread Michal Zygowski


On 03.07.2019 15:13, awokd via coreboot wrote:
> Michal Zygowski:
>> On 03.07.2019 04:30, awokd via coreboot wrote:
>>> Michal Zygowski:
 On 01.07.2019 14:53, Andriy Gapon wrote:
> It appears that HPET MSI support
> is disabled on some platforms by default:
>
> src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/Family/Hudson2/EnvDefHudson2.c:
>
>    TRUE,    // HpetMsiDis
>>> FWIW, I hardcoded the above to FALSE, recompiled, and reflashed my
>>> f15tn. It caused Qubes to run about half as fast. I checked the logs
>>> and didn't see any errors to explain why. I then changed it back to
>>> TRUE and HPET itself to FALSE (and recompiled/reflashed). Normal speed
>>> came back, XEN Platform timer changed from HPET to ACPI, and MSI is
>>> still enabled for some of the PCI devices. For example, the video
>>> controller on 00:01.0 is IRQ 57 and capability [a0] is MSI: Enable+.
>> Yes, for PCI devices it can be checked by verbose lspci. However I still
>> wonder how did You determine that HPET is not using MSI?
> Apologies, omitted that part. With the original default of HPET enabled
> and HpetMsiDis TRUE, the speed was fine. Xen platform timer indicated
> HPET in this case. Devices also still seemed to be using MSI, so I'm not
> sure what that option is supposed to do except slow down my system.
If timer interrupts are not handled properly for some reason (in this
case HPET timer), it is only natural that it will dramatically slow down
the system. The MSI can be working, but may also require some IOAPIC
configuration. Can't say much without any logs from firmware/OS.
>> When You set
>> the HPET option to FALSE, it probably did not touch HPET in AGESA, that
>> is why the speed came back.  I would check whether  HPET is operable for
>> this processor family. For example on Intel Braswell platform HPET was
>> not guaranteed operable in certain conditions.
>>
>> BTW have You tried with family 16h (i.e. PC Engines APU2)?
> Don't have one of those, but wanted to give a (possibly useless) data
> point of my experience at least.
Sorry, I have mistakenly taken You as the initiator of the thread, who
stated he has an APU2 platform. Should have checked the email address first.
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Firmware Engineer
http://3mdeb.com | @3mdeb_com
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[coreboot] Re: HPET MSI/FSB on AMD 16h

2019-07-03 Thread awokd via coreboot

Michal Zygowski:
> 
> On 03.07.2019 04:30, awokd via coreboot wrote:
>> Michal Zygowski:
>>>
>>> On 01.07.2019 14:53, Andriy Gapon wrote:
>>
 It appears that HPET MSI support
 is disabled on some platforms by default:

 src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/Family/Hudson2/EnvDefHudson2.c:

    TRUE,    // HpetMsiDis
>>
>> FWIW, I hardcoded the above to FALSE, recompiled, and reflashed my
>> f15tn. It caused Qubes to run about half as fast. I checked the logs
>> and didn't see any errors to explain why. I then changed it back to
>> TRUE and HPET itself to FALSE (and recompiled/reflashed). Normal speed
>> came back, XEN Platform timer changed from HPET to ACPI, and MSI is
>> still enabled for some of the PCI devices. For example, the video
>> controller on 00:01.0 is IRQ 57 and capability [a0] is MSI: Enable+.

> Yes, for PCI devices it can be checked by verbose lspci. However I still
> wonder how did You determine that HPET is not using MSI?

Apologies, omitted that part. With the original default of HPET enabled
and HpetMsiDis TRUE, the speed was fine. Xen platform timer indicated
HPET in this case. Devices also still seemed to be using MSI, so I'm not
sure what that option is supposed to do except slow down my system.

> When You set
> the HPET option to FALSE, it probably did not touch HPET in AGESA, that
> is why the speed came back.  I would check whether  HPET is operable for
> this processor family. For example on Intel Braswell platform HPET was
> not guaranteed operable in certain conditions.
> 
> BTW have You tried with family 16h (i.e. PC Engines APU2)?

Don't have one of those, but wanted to give a (possibly useless) data
point of my experience at least.
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[coreboot] Re: Question about blobs

2019-07-03 Thread Jorge Fernandez Monteagudo

Hi again,

A clarification. From the StoneyPI_1_3_0_A.ZIP file I've got under NDA is it 
possible to compile it and get the AGESA.bin file?
For instance, for the fam15tn family the coreboot build process generates a 
libagesa.fam15tn.a file which is integrated in the
final coreboot.rom file. Could it be possible to do the same from a PI family? 
The build process in coreboot is only prepared to
use a wrapper and the AGESA.bin file, but maybe is it possible to generate the 
AGESA.bin from the zip file...

Thanks!


De: Jorge Fernandez Monteagudo 
Enviado: martes, 2 de julio de 2019 14:25
Para: Kyösti Mälkki
Cc: coreboot@coreboot.org
Asunto: [coreboot] Re: Question about blobs

Hi Kyösti! Thanks for the info!

>AMD contracted SilverBack for the tasks on StoneyRidge (and
>MerlinFalcon apparently). The source is a heavily modified StoneyPI
>package. You may get the unmodified one from AMD reps under NDA. Or
>pay SilverBack for the development you would be more capable of doing
>yourself, and you still might not get a license that allows
>distributing the work. There was a promise of scrubbing and
>relicensing StoneyPI source but... Let's just say legalities messed it
>up, I don't have the details.

Yes, the AMD reps we're in touch answer me to get in touch with SilverBack to 
get support :(
We've been able to get a more recent StoneyPI_1_3_0_A.ZIP under NDA because 
I've seen
this version fixed the issue:

EMBSWDEV-4487: System is not booting when memory is connected only to DIMM 1 
slot

maybe related with our problem, but I don't know how to integrate this code 
into coreboot...
And if you say that the current work in coreboot is from a heavily modified 
base from SilverBack
I don't have any chance to make it work...

>As for the the other blobs (MullinsPI, CarrizoPI, KaveriPI), those
>were either built at SAGE (R.I.P.) or AMD AES (R.I.P.) and I have been
>told the repositories and toolchains were never officially transferred
>to SilverBack's possession. In other words, even if you paid,
>SilverBack is not likely to work on those.

Then, no more options to get a working BIOS than SilverBack?

>I believe we have talked before. Maybe it was about CarrizoPI? I was
>asking for commercial adopters around coreboot and binaryPI, in
>attempts to get to the same negotiation table with AMD management. Did
>You or Your manager ever respond?

Yes. I began asking in the coreboot mailing list about the Bettong mainboard. I 
added TPM support
and tianocore to that demoboard. I remember the email and I answered it giving 
my support because
we thought coreboot is the way to go to support our custom board.

Regards,
Jorge

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[coreboot] Re: HPET MSI/FSB on AMD 16h

2019-07-03 Thread Michal Zygowski


On 03.07.2019 04:30, awokd via coreboot wrote:
> Michal Zygowski:
>>
>> On 01.07.2019 14:53, Andriy Gapon wrote:
>
>>> It appears that HPET MSI support
>>> is disabled on some platforms by default:
>>>
>>> src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/Family/Hudson2/EnvDefHudson2.c:
>>>
>>>    TRUE,    // HpetMsiDis
>
> FWIW, I hardcoded the above to FALSE, recompiled, and reflashed my
> f15tn. It caused Qubes to run about half as fast. I checked the logs
> and didn't see any errors to explain why. I then changed it back to
> TRUE and HPET itself to FALSE (and recompiled/reflashed). Normal speed
> came back, XEN Platform timer changed from HPET to ACPI, and MSI is
> still enabled for some of the PCI devices. For example, the video
> controller on 00:01.0 is IRQ 57 and capability [a0] is MSI: Enable+.
Yes, for PCI devices it can be checked by verbose lspci. However I still
wonder how did You determine that HPET is not using MSI? When You set
the HPET option to FALSE, it probably did not touch HPET in AGESA, that
is why the speed came back.  I would check whether  HPET is operable for
this processor family. For example on Intel Braswell platform HPET was
not guaranteed operable in certain conditions.

BTW have You tried with family 16h (i.e. PC Engines APU2)?
> ___
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-- 
Michał Żygowski
Firmware Engineer
http://3mdeb.com | @3mdeb_com

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[coreboot] Re: Does Coreboot support the following options to enable/disable?

2019-07-03 Thread Lance Zhao

That's Denverton? If the selection is not part of fspupd file
https://github.com/IntelFsp/FSP/tree/master/DenvertonNSFspBinPkg/Include,
then probably they only have default setting. We can't enable/disable those
option through FSP didn't mean those feature is not available.

Lance

Ashmita Chakraborty  于2019年7月3日周三 上午2:10写道：

> Hi Ranga,
>
> Exactly, only Hyperthreading is available. I could not find Intel
> Virtualization Tech , MLC streamer, etc. So here's my question if all these
> options support coreboot for Xeon D-15xx?
>
>
> Thanks&Regards,
>
> Ashmita Chakraborty
> --
> *From:* Ranga Rao 
> *Sent:* Wednesday, July 3, 2019 1:15:07 PM
> *To:* Ashmita Chakraborty; coreboot@coreboot.org
> *Subject:* RE: [coreboot] Re: Does Coreboot support the following options
> to enable/disable?
>
>
> Hi Ashmita,
>
>
>
> I could see HyperThreading Enable/Disable in Upd_Data_region
>
> FSP-master\BroadwellDEFspBinPkg\include\fspvpd.h
>
>
>
> Regards
>
> Ranga
>
>
>
> *From:* Ranga Rao 
> *Sent:* Wednesday 3 July 2019 08:18
> *To:* Ashmita Chakraborty ;
> coreboot@coreboot.org
> *Subject:* [coreboot] Re: Does Coreboot support the following options to
> enable/disable?
>
>
>
> Hi Ashmita,
>
>
>
> Broadwell-DE / Xeon D support still depends Intel's closed-source FSP
> (Firmware Support Package) binary-only blobs.
>
> Broadwell-DE SoC / Xeon D Support Added To Coreboot
>
>
>
> Hope you could configure them through fsp_upd_data?
>
>
>
> Regards
>
> Ranga
>
>
>
>
>
>
>
>
>
> *From:* Ashmita Chakraborty 
> *Sent:* Wednesday 3 July 2019 08:14
> *To:* Ranga Rao ; coreboot@coreboot.org
> *Subject:* Re: [coreboot] Does Coreboot support the following options to
> enable/disable?
>
>
>
> Dear Ranga,
>
>
>
> These options are meant for Xeon D-15xx series family. So will the
> coreboot support these options? The coreboot will be built for Xeon D-15xx
> processor. Yes, I have access to them in fsp_early_init through
> fsp_upd_data.
>
>
>
> Thanks&Regards,
>
> Ashmita Chakraborty
>
>
> --
>
> *From:* Ranga Rao 
> *Sent:* Tuesday, July 2, 2019 8:41 PM
> *To:* Ashmita Chakraborty; coreboot@coreboot.org
> *Subject:* RE: [coreboot] Does Coreboot support the following options to
> enable/disable?
>
>
>
> Hi,
>
>
>
> As these features are processor/SoC specific and they are part of FSPM,
> they should be configurable
>
> during fsp early init in coreboot, though you may not find a KConfig
> option to enable/disable
>
>
>
> Do you have access to them in *fsp_early_init* through *fsp_upd_data?*
>
>
>
> Regards
>
> Ranga
>
>
>
> -Original Message-
> From: ashmita.chakrabo...@ltts.com 
> Sent: Tuesday 2 July 2019 07:34
> To: coreboot@coreboot.org
> Subject: [coreboot] Does Coreboot support the following options to
> enable/disable?
>
>
>
> Does the coreboot support the following options to enable/disable:
>
>
>
> HyperThreading- Disabled
>
> Execute Disable Bit  -  Enabled
>
> Intel Virtualization Tech- Enabled
>
> Intel (R) TXT-   Disabled
>
> Enhanced Error Containment Mode -Disabled
>
> MLC Streamer   -Enabled
>
> MLC Spatial Prefetcher   -Enabled
>
> DUC Data Prefetcher  -Enabled
>
> DUC Instruction Prefetcher-Enabled
>
> LLC Prefetch  - Enabled
>
> Intel Configurable TDB -Enabled
>
> TDP Level  -level 2
>
>
>
>
>
> Please let me know.
>
>
>
> Thanks in advance.
>
>
>
> Regards,
>
> Ashmita Chakraborty
>
> ___
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>
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>
> This Email may contain confidential or privileged information for the
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>
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[coreboot] Re: Does Coreboot support the following options to enable/disable?

2019-07-03 Thread Ashmita Chakraborty

Hi Ranga,

Exactly, only Hyperthreading is available. I could not find Intel 
Virtualization Tech , MLC streamer, etc. So here's my question if all these 
options support coreboot for Xeon D-15xx?


Thanks&Regards,

Ashmita Chakraborty


From: Ranga Rao 
Sent: Wednesday, July 3, 2019 1:15:07 PM
To: Ashmita Chakraborty; coreboot@coreboot.org
Subject: RE: [coreboot] Re: Does Coreboot support the following options to 
enable/disable?


Hi Ashmita,



I could see HyperThreading Enable/Disable in Upd_Data_region

FSP-master\BroadwellDEFspBinPkg\include\fspvpd.h



Regards

Ranga



From: Ranga Rao 
Sent: Wednesday 3 July 2019 08:18
To: Ashmita Chakraborty ; coreboot@coreboot.org
Subject: [coreboot] Re: Does Coreboot support the following options to 
enable/disable?



Hi Ashmita,



Broadwell-DE / Xeon D support still depends Intel's closed-source FSP (Firmware 
Support Package) binary-only blobs.

Broadwell-DE SoC / Xeon D Support Added To Coreboot



Hope you could configure them through fsp_upd_data?



Regards

Ranga









From: Ashmita Chakraborty 
mailto:ashmita.chakrabo...@ltts.com>>
Sent: Wednesday 3 July 2019 08:14
To: Ranga Rao mailto:ranga...@ircona.com>>; 
coreboot@coreboot.org
Subject: Re: [coreboot] Does Coreboot support the following options to 
enable/disable?



Dear Ranga,



These options are meant for Xeon D-15xx series family. So will the coreboot 
support these options? The coreboot will be built for Xeon D-15xx processor. 
Yes, I have access to them in fsp_early_init through fsp_upd_data.



Thanks&Regards,

Ashmita Chakraborty





From: Ranga Rao mailto:ranga...@ircona.com>>
Sent: Tuesday, July 2, 2019 8:41 PM
To: Ashmita Chakraborty; coreboot@coreboot.org
Subject: RE: [coreboot] Does Coreboot support the following options to 
enable/disable?



Hi,



As these features are processor/SoC specific and they are part of FSPM, they 
should be configurable

during fsp early init in coreboot, though you may not find a KConfig option to 
enable/disable



Do you have access to them in fsp_early_init through fsp_upd_data?



Regards

Ranga



-Original Message-
From: ashmita.chakrabo...@ltts.com 
mailto:ashmita.chakrabo...@ltts.com>>
Sent: Tuesday 2 July 2019 07:34
To: coreboot@coreboot.org
Subject: [coreboot] Does Coreboot support the following options to 
enable/disable?



Does the coreboot support the following options to enable/disable:



HyperThreading- Disabled

Execute Disable Bit  -  Enabled

Intel Virtualization Tech- Enabled

Intel (R) TXT-   Disabled

Enhanced Error Containment Mode -Disabled

MLC Streamer   -Enabled

MLC Spatial Prefetcher   -Enabled

DUC Data Prefetcher  -Enabled

DUC Instruction Prefetcher-Enabled

LLC Prefetch  - Enabled

Intel Configurable TDB -Enabled

TDP Level  -level 2





Please let me know.



Thanks in advance.



Regards,

Ashmita Chakraborty

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[coreboot] Re: Does Coreboot support the following options to enable/disable?

2019-07-03 Thread Ranga Rao

Hi Ashmita,

I could see HyperThreading Enable/Disable in Upd_Data_region
FSP-master\BroadwellDEFspBinPkg\include\fspvpd.h

Regards
Ranga

From: Ranga Rao 
Sent: Wednesday 3 July 2019 08:18
To: Ashmita Chakraborty ; coreboot@coreboot.org
Subject: [coreboot] Re: Does Coreboot support the following options to 
enable/disable?

Hi Ashmita,

Broadwell-DE / Xeon D support still depends Intel's closed-source FSP (Firmware 
Support Package) binary-only blobs.
Broadwell-DE SoC / Xeon D Support Added To Coreboot

Hope you could configure them through fsp_upd_data?

Regards
Ranga




From: Ashmita Chakraborty 
mailto:ashmita.chakrabo...@ltts.com>>
Sent: Wednesday 3 July 2019 08:14
To: Ranga Rao mailto:ranga...@ircona.com>>; 
coreboot@coreboot.org
Subject: Re: [coreboot] Does Coreboot support the following options to 
enable/disable?

Dear Ranga,

These options are meant for Xeon D-15xx series family. So will the coreboot 
support these options? The coreboot will be built for Xeon D-15xx processor. 
Yes, I have access to them in fsp_early_init through fsp_upd_data.

Thanks&Regards,
Ashmita Chakraborty


From: Ranga Rao mailto:ranga...@ircona.com>>
Sent: Tuesday, July 2, 2019 8:41 PM
To: Ashmita Chakraborty; coreboot@coreboot.org
Subject: RE: [coreboot] Does Coreboot support the following options to 
enable/disable?


Hi,



As these features are processor/SoC specific and they are part of FSPM, they 
should be configurable

during fsp early init in coreboot, though you may not find a KConfig option to 
enable/disable



Do you have access to them in fsp_early_init through fsp_upd_data?



Regards

Ranga



-Original Message-
From: ashmita.chakrabo...@ltts.com 
mailto:ashmita.chakrabo...@ltts.com>>
Sent: Tuesday 2 July 2019 07:34
To: coreboot@coreboot.org
Subject: [coreboot] Does Coreboot support the following options to 
enable/disable?



Does the coreboot support the following options to enable/disable:



HyperThreading- Disabled

Execute Disable Bit  -  Enabled

Intel Virtualization Tech- Enabled

Intel (R) TXT-   Disabled

Enhanced Error Containment Mode -Disabled

MLC Streamer   -Enabled

MLC Spatial Prefetcher   -Enabled

DUC Data Prefetcher  -Enabled

DUC Instruction Prefetcher-Enabled

LLC Prefetch  - Enabled

Intel Configurable TDB -Enabled

TDP Level  -level 2





Please let me know.



Thanks in advance.



Regards,

Ashmita Chakraborty

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[coreboot] Re: Does Coreboot support the following options to enable/disable?

2019-07-03 Thread Ashmita Chakraborty

Hi Ranga,


Yes, Xeon D depends on Intels's FSP. I have explored that the coreboot will be 
built on Xeon D but I am not confident enough that  those options could be 
configured through fsp_upd_data.


Thanks&Regards,

Ashmita Chakraborty



From: Ranga Rao 
Sent: Wednesday, July 3, 2019 12:47:59 PM
To: Ashmita Chakraborty; coreboot@coreboot.org
Subject: RE: [coreboot] Does Coreboot support the following options to 
enable/disable?


Hi Ashmita,



Broadwell-DE / Xeon D support still depends Intel's closed-source FSP (Firmware 
Support Package) binary-only blobs.

Broadwell-DE SoC / Xeon D Support Added To Coreboot



Hope you could configure them through fsp_upd_data?



Regards

Ranga









From: Ashmita Chakraborty 
Sent: Wednesday 3 July 2019 08:14
To: Ranga Rao ; coreboot@coreboot.org
Subject: Re: [coreboot] Does Coreboot support the following options to 
enable/disable?



Dear Ranga,



These options are meant for Xeon D-15xx series family. So will the coreboot 
support these options? The coreboot will be built for Xeon D-15xx processor. 
Yes, I have access to them in fsp_early_init through fsp_upd_data.



Thanks&Regards,

Ashmita Chakraborty





From: Ranga Rao mailto:ranga...@ircona.com>>
Sent: Tuesday, July 2, 2019 8:41 PM
To: Ashmita Chakraborty; coreboot@coreboot.org
Subject: RE: [coreboot] Does Coreboot support the following options to 
enable/disable?



Hi,



As these features are processor/SoC specific and they are part of FSPM, they 
should be configurable

during fsp early init in coreboot, though you may not find a KConfig option to 
enable/disable



Do you have access to them in fsp_early_init through fsp_upd_data?



Regards

Ranga



-Original Message-
From: ashmita.chakrabo...@ltts.com 
mailto:ashmita.chakrabo...@ltts.com>>
Sent: Tuesday 2 July 2019 07:34
To: coreboot@coreboot.org
Subject: [coreboot] Does Coreboot support the following options to 
enable/disable?



Does the coreboot support the following options to enable/disable:



HyperThreading- Disabled

Execute Disable Bit  -  Enabled

Intel Virtualization Tech- Enabled

Intel (R) TXT-   Disabled

Enhanced Error Containment Mode -Disabled

MLC Streamer   -Enabled

MLC Spatial Prefetcher   -Enabled

DUC Data Prefetcher  -Enabled

DUC Instruction Prefetcher-Enabled

LLC Prefetch  - Enabled

Intel Configurable TDB -Enabled

TDP Level  -level 2





Please let me know.



Thanks in advance.



Regards,

Ashmita Chakraborty

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[coreboot] Re: Does Coreboot support the following options to enable/disable?

2019-07-03 Thread Ranga Rao

Hi Ashmita,

Broadwell-DE / Xeon D support still depends Intel's closed-source FSP (Firmware 
Support Package) binary-only blobs.
Broadwell-DE SoC / Xeon D Support Added To Coreboot

Hope you could configure them through fsp_upd_data?

Regards
Ranga




From: Ashmita Chakraborty 
Sent: Wednesday 3 July 2019 08:14
To: Ranga Rao ; coreboot@coreboot.org
Subject: Re: [coreboot] Does Coreboot support the following options to 
enable/disable?

Dear Ranga,

These options are meant for Xeon D-15xx series family. So will the coreboot 
support these options? The coreboot will be built for Xeon D-15xx processor. 
Yes, I have access to them in fsp_early_init through fsp_upd_data.

Thanks&Regards,
Ashmita Chakraborty


From: Ranga Rao mailto:ranga...@ircona.com>>
Sent: Tuesday, July 2, 2019 8:41 PM
To: Ashmita Chakraborty; coreboot@coreboot.org
Subject: RE: [coreboot] Does Coreboot support the following options to 
enable/disable?


Hi,



As these features are processor/SoC specific and they are part of FSPM, they 
should be configurable

during fsp early init in coreboot, though you may not find a KConfig option to 
enable/disable



Do you have access to them in fsp_early_init through fsp_upd_data?



Regards

Ranga



-Original Message-
From: ashmita.chakrabo...@ltts.com 
mailto:ashmita.chakrabo...@ltts.com>>
Sent: Tuesday 2 July 2019 07:34
To: coreboot@coreboot.org
Subject: [coreboot] Does Coreboot support the following options to 
enable/disable?



Does the coreboot support the following options to enable/disable:



HyperThreading- Disabled

Execute Disable Bit  -  Enabled

Intel Virtualization Tech- Enabled

Intel (R) TXT-   Disabled

Enhanced Error Containment Mode -Disabled

MLC Streamer   -Enabled

MLC Spatial Prefetcher   -Enabled

DUC Data Prefetcher  -Enabled

DUC Instruction Prefetcher-Enabled

LLC Prefetch  - Enabled

Intel Configurable TDB -Enabled

TDP Level  -level 2





Please let me know.



Thanks in advance.



Regards,

Ashmita Chakraborty

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[coreboot] Re: Does Coreboot support the following options to enable/disable?

2019-07-03 Thread Ashmita Chakraborty

Dear Ranga,

These options are meant for Xeon D-15xx series family. So will the coreboot 
support these options? The coreboot will be built for Xeon D-15xx processor. 
Yes, I have access to them in fsp_early_init through fsp_upd_data.

Thanks&Regards,
Ashmita Chakraborty



From: Ranga Rao 
Sent: Tuesday, July 2, 2019 8:41 PM
To: Ashmita Chakraborty; coreboot@coreboot.org
Subject: RE: [coreboot] Does Coreboot support the following options to 
enable/disable?


Hi,



As these features are processor/SoC specific and they are part of FSPM, they 
should be configurable

during fsp early init in coreboot, though you may not find a KConfig option to 
enable/disable



Do you have access to them in fsp_early_init through fsp_upd_data?



Regards

Ranga



-Original Message-
From: ashmita.chakrabo...@ltts.com 
Sent: Tuesday 2 July 2019 07:34
To: coreboot@coreboot.org
Subject: [coreboot] Does Coreboot support the following options to 
enable/disable?



Does the coreboot support the following options to enable/disable:



HyperThreading- Disabled

Execute Disable Bit  -  Enabled

Intel Virtualization Tech- Enabled

Intel (R) TXT-   Disabled

Enhanced Error Containment Mode -Disabled

MLC Streamer   -Enabled

MLC Spatial Prefetcher   -Enabled

DUC Data Prefetcher  -Enabled

DUC Instruction Prefetcher-Enabled

LLC Prefetch  - Enabled

Intel Configurable TDB -Enabled

TDP Level  -level 2





Please let me know.



Thanks in advance.



Regards,

Ashmita Chakraborty

___

coreboot mailing list -- coreboot@coreboot.org To 
unsubscribe send an email to 
coreboot-le...@coreboot.org

L&T Technology Services Ltd

www.LTTS.com

This Email may contain confidential or privileged information for the intended 
recipient (s). If you are not the intended recipient, please do not use or 
disseminate the information, notify the sender and delete it from your system.
___
coreboot mailing list -- coreboot@coreboot.org
To unsubscribe send an email to coreboot-le...@coreboot.org

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[coreboot] Re: Does Coreboot support the following options to enable/disable?

[coreboot] Re: Does Coreboot support the following options to enable/disable?

[coreboot] Re: Does Coreboot support the following options to enable/disable?

[coreboot] Re: Does Coreboot support the following options to enable/disable?

[coreboot] Re: Does Coreboot support the following options to enable/disable?

[coreboot] Re: Does Coreboot support the following options to enable/disable?

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