[coreboot] Re: Status of Optimus work? Target laptops?
Is [1] the current, most recent work on supporting nvidia Optimus? Yes! Needs rebasing, though. ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Xeon SP code structure
Dear coreboot folks, As some you know we at OSF are working on enabling Xeons in coreboot. We have recently uploaded Skylake-SP which goes in src/soc/intel/skylake_sp. At the same time we are working on enabling next generation SP processor. I was wondering what may be a good way to structure the code. It feels wrong to just throw code into src/soc/intel especially for systems with discrete PCH. I'd like to hear opinions and discuss what may be a good way to structure and organize the code. Here is what we want to achieve: * Make code modular It looks like certain things are similar to all -SP variants and it makes sense to share that code rather than copy-paste. * Allow same motherboard to host different CPU (and potentially different PCH) The practical thing here is that some server boards support two generations of CPUs that are pin-compatible. However, chip code is different. PCH may be same or different. * Did I already say eliminate/decrease copy-pasta? Here is a structure that I came up with so far (patch stack ending with 39017) cpu/xeon_sp/ ├─ Kconfig # baseline of config ├─ include/ # common headers ├─ common/ # true common code such as IIO stacks code, ACPI tables ├─ cpu/skylake-sp/ │├─ include/ # cpu/northbridge defines specific to given model │├─ Kconfig # whatever overrides from common we need │└─ *.c # code that implements specific platform bits ├─ cpu/nextlake-sp/ │├─ include/ # same │├─ Kconfig # same │└─ *.c # same Now then, the "common" xeon_sp code may be placed in src/northbridge. We probably should add Lewisburg C62x code in src/southbridge as well. Thoughts? Alternatively, we can place everything in soc/intel/ and put Xeon server common code in soc/intel/common/block/ or similar. This may be easiest way but fells messy. Is there any other way with pros and cons? thanks Andrey ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Re: Still need assistance porting to ASUS P8Z77-M
Hi Frans, Thanks for confirming. Hi Angel, I was unable to get any serial output, even with early serial configured. Z77 power on defaults will see port 80 decoded by LPC according to their datasheet, and I found Asus actually included with some boards a POST card that plugs into the TPM header, so I'm on the right track. Now to see if I can implement the LPC protocol correctly on an Arduino Due, chosen for its 84MHz clock and 3.3v operation. I looked at the source and only see the CONFIG_POST_DEVICE_* options used by sb/amd/*/hudson, not by any Intel platform code. I then looked at the datasheet and the lspci dump with OEM BIOS. I would need to do something to device 0x1e.0 (disabled!) and 0x1c.6 (PCIe root port 6) and I would need new code that connects to CONFIG_POST_DEVICE_*. I will be back with more questions, so bear with me. Thanks Keith On Fri, Feb 28, 2020 at 4:54 AM Frans Hendriks wrote: > > Hi Keith, > > PCI-to-PCI bridge need to be configured before you can use PCI POST card. > > Default post code are send out to port 80h. > Depending on the chipset (and your needs) you need to enable the port80 to > the right channel PCI/LPC. > > Best regards, > Frans Hendriks > Eltan B.V. > > -Original Message- > From: Angel Pons [mailto:th3fan...@gmail.com] > Sent: vrijdag 28 februari 2020 10:30 > To: Keith Hui > Cc: coreboot > Subject: [coreboot] Re: Still need assistance porting to ASUS P8Z77-M > > Hi Keith, > > On Fri, Feb 28, 2020 at 7:18 AM Keith Hui wrote: > > > > A week ago I wrote here about my problems trying to port coreboot to > > my board. Unfortunately I am still no closer to booting. > > > > In the meantime I flashed my new chip with my OEM firmware backup. It > > boots; then I flashed my patched IFD (for chip ID and flash unlock) > > and it still boots. So it's not chip compatibility or corrupted > > descriptor. > > > > The only sign of life I got is the bootblock banner left in the SPI > > console. My PCI POST card is showing nothing, but knowing that it sits > > on a PCIe-PCI bridge (ASM1063 that P8Z77M-PRO does not have) and not > > knowing if it needs software init to work, I am now trying to pull > > POST codes off the LPC bus over the TPM header, using an Arduino Due. > > Do I have to add some early init to have port 80 accesses sent to LPC > > bus for this to work? > > You have to tell coreboot where to route LPC post codes to. It defaults to > "None", but you can choose PCI or LPC. I have never tried to print post codes > with coreboot, though. I would try using the serial port though, as it is > more practical for debugging than post codes. > > > Thanks for your help > > Keith > > ___ > > coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an > > email to coreboot-le...@coreboot.org > > Best regards, > > Angel Pons > ___ > coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email > to coreboot-le...@coreboot.org > > > > ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Re: Still need assistance porting to ASUS P8Z77-M
Hi Keith, PCI-to-PCI bridge need to be configured before you can use PCI POST card. Default post code are send out to port 80h. Depending on the chipset (and your needs) you need to enable the port80 to the right channel PCI/LPC. Best regards, Frans Hendriks Eltan B.V. -Original Message- From: Angel Pons [mailto:th3fan...@gmail.com] Sent: vrijdag 28 februari 2020 10:30 To: Keith Hui Cc: coreboot Subject: [coreboot] Re: Still need assistance porting to ASUS P8Z77-M Hi Keith, On Fri, Feb 28, 2020 at 7:18 AM Keith Hui wrote: > > A week ago I wrote here about my problems trying to port coreboot to > my board. Unfortunately I am still no closer to booting. > > In the meantime I flashed my new chip with my OEM firmware backup. It > boots; then I flashed my patched IFD (for chip ID and flash unlock) > and it still boots. So it's not chip compatibility or corrupted > descriptor. > > The only sign of life I got is the bootblock banner left in the SPI > console. My PCI POST card is showing nothing, but knowing that it sits > on a PCIe-PCI bridge (ASM1063 that P8Z77M-PRO does not have) and not > knowing if it needs software init to work, I am now trying to pull > POST codes off the LPC bus over the TPM header, using an Arduino Due. > Do I have to add some early init to have port 80 accesses sent to LPC > bus for this to work? You have to tell coreboot where to route LPC post codes to. It defaults to "None", but you can choose PCI or LPC. I have never tried to print post codes with coreboot, though. I would try using the serial port though, as it is more practical for debugging than post codes. > Thanks for your help > Keith > ___ > coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an > email to coreboot-le...@coreboot.org Best regards, Angel Pons ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Re: Still need assistance porting to ASUS P8Z77-M
Hi Keith, On Fri, Feb 28, 2020 at 7:18 AM Keith Hui wrote: > > A week ago I wrote here about my problems trying to port coreboot to > my board. Unfortunately I am still no closer to booting. > > In the meantime I flashed my new chip with my OEM firmware backup. It > boots; then I flashed my patched IFD (for chip ID and flash unlock) > and it still boots. So it's not chip compatibility or corrupted > descriptor. > > The only sign of life I got is the bootblock banner left in the SPI > console. My PCI POST card is showing nothing, but knowing that it sits > on a PCIe-PCI bridge (ASM1063 that P8Z77M-PRO does not have) and not > knowing if it needs software init to work, I am now trying to pull > POST codes off the LPC bus over the TPM header, using an Arduino Due. > Do I have to add some early init to have port 80 accesses sent to LPC > bus for this to work? You have to tell coreboot where to route LPC post codes to. It defaults to "None", but you can choose PCI or LPC. I have never tried to print post codes with coreboot, though. I would try using the serial port though, as it is more practical for debugging than post codes. > Thanks for your help > Keith > ___ > coreboot mailing list -- coreboot@coreboot.org > To unsubscribe send an email to coreboot-le...@coreboot.org Best regards, Angel Pons ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
