[coreboot] Re: Extended IvyBridge CPU configuration

[Evgeny Zinoviev via coreboot]

So, it's been three weeks, no hangs, no crashes, everything's fine on my 
W530 (which is my primary working machine) with 5.4.28-gentoo kernel and 
HT disabled by coreboot patch. CPU is i7-3940XM.


On 20.06.2020 14:46, Evgeny Zinoviev via coreboot wrote:

Could be... Thanks for testing!

I've also put it on some of my daily work machines: a quad-code Ivy 
and a dual-code Sandy in order to see how it works in a real world... 
Works so far. So if it doesn't end up crashing in a week or two I'd 
say it's stable. We'll see.


On 6/20/20 1:42 PM, Lars Hochstetter wrote:

Update II:

All tests passed with and without HT enabled!

I discovered something curious though - if I disable HT memtest86+ 
finishes a pass in 45ish minutes. If I enable HT it takes 4+ hours.


I don't know if it's due to coreboot or memtest86+ as memtest86+ 
v5.01 also took around 4+ hours for all tests with HT enabled.


Maybe it is a bug with memtest86+ ?

On 19.06.20 00:58, Lars Hochstetter wrote:

Update: I managed to get memtest86+ v5.31b running.

I downloaded the .iso.zip and used geteltorito v0.6 to turn the .iso 
file into a 1.44meg floppy image. I then added the floppy image like 
the memtest86+ v5.01 floppy image to my coreboot image (4.12 + 
patchset 15).


Preliminary tests with memtest86+ v5.31b went without an issue 
(Note: I didn't run all the tests, but test #7 was passed with and 
without HT).


I'll try to run all tests with and without HT on 4.12 + patchset 15 
around the weekend.

___
coreboot mailing list -- coreboot@coreboot.org
To unsubscribe send an email to coreboot-le...@coreboot.org

___
coreboot mailing list -- coreboot@coreboot.org
To unsubscribe send an email to coreboot-le...@coreboot.org

___
coreboot mailing list -- coreboot@coreboot.org
To unsubscribe send an email to coreboot-le...@coreboot.org

[coreboot] New Defects reported by Coverity Scan for coreboot

[scan-admin--- via coreboot]

Hi,

Please find the latest report on new defect(s) introduced to coreboot found 
with Coverity Scan.

106 new defect(s) introduced to coreboot found with Coverity Scan.
2 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent 
build analyzed by Coverity Scan.

New defect(s) Reported-by: Coverity Scan
Showing 20 of 106 defect(s)


** CID 1429780:  Uninitialized variables  (UNINIT)



*** CID 1429780:  Uninitialized variables  (UNINIT)
/src/mainboard/dell/optiplex_9010/sch5545_ec.c: 619 in sch5545_ec_hwm_init()
613 
614 printk(BIOS_DEBUG, "%s\n", __func__);
615 sch5545_emi_init(0x2e);
616 
617 chassis_type = get_chassis_type();
618 
>>> CID 1429780:  Uninitialized variables  (UNINIT)
>>> Using uninitialized value "val" when calling "ec_read_write_reg".
619 ec_read_write_reg(EC_HWM_LDN, 0x0048, , READ_OP);
620 ec_read_write_reg(EC_HWM_LDN, 0x0048, , WRITE_OP);
621 ec_read_write_reg(EC_HWM_LDN, 0x0042, , READ_OP);
622 ec_read_write_reg(EC_HWM_LDN, 0x0048, , READ_OP);
623 val |= 0x02;
624 ec_read_write_reg(EC_HWM_LDN, 0x0048, , WRITE_OP);

** CID 1429772:  Uninitialized variables  (UNINIT)



*** CID 1429772:  Uninitialized variables  (UNINIT)
/src/mainboard/dell/optiplex_9010/sch5545_ec.c: 432 in 
sch5545_get_ec_fw_version()
426 uint16_t sch5545_get_ec_fw_version(void)
427 {
428 uint8_t val;
429 uint16_t ec_fw_version;
430 
431 /* Read the FW version currently loaded used by EC */
>>> CID 1429772:  Uninitialized variables  (UNINIT)
>>> Using uninitialized value "val" when calling "ec_read_write_reg".
432 ec_read_write_reg(EC_HWM_LDN, 0x2ad, , READ_OP);
433 ec_fw_version = (val << 8);
434 ec_read_write_reg(EC_HWM_LDN, 0x2ae, , READ_OP);
435 ec_fw_version |= val;
436 ec_read_write_reg(EC_HWM_LDN, 0x2ac, , READ_OP);
437 ec_read_write_reg(EC_HWM_LDN, 0x2fd, , READ_OP);

** CID 1429765:  Uninitialized variables  (UNINIT)



*** CID 1429765:  Uninitialized variables  (UNINIT)
/src/mainboard/dell/optiplex_9010/sch5545_ec.c: 513 in 
sch5545_ec_hwm_early_init()
507 int i;
508 
509 printk(BIOS_DEBUG, "%s\n", __func__);
510 
511 ec_check_mbox_and_int_status(0x20, 0x01);
512 
>>> CID 1429765:  Uninitialized variables  (UNINIT)
>>> Using uninitialized value "val" when calling "ec_read_write_reg".
513 ec_read_write_reg(2, 0xcb, , READ_OP);
514 ec_read_write_reg(2, 0xb8, , READ_OP);
515 
516 for (i = 0; i < ARRAY_SIZE(ec_hwm_init_seq); i++) {
517 val = ec_hwm_init_seq[i].val;
518 ec_read_write_reg(EC_HWM_LDN, ec_hwm_init_seq[i].reg, 
,

** CID 1428711:(OVERRUN)



*** CID 1428711:(OVERRUN)
/src/vendorcode/eltan/security/mboot/mboot.c: 431 in mb_crtm()
425 tcgEventHdr.pcrIndex = MBOOT_PCR_INDEX_0;
426 tcgEventHdr.eventType = EV_S_CRTM_VERSION;
427 tcgEventHdr.eventSize = sizeof(crtm_version);
428 printk(BIOS_DEBUG, "%s: EventSize - %u\n", __func__,
429 tcgEventHdr.eventSize);
430 
>>> CID 1428711:(OVERRUN)
>>> Overrunning callee's array of size 32 by passing argument 
>>> "tcgEventHdr.eventSize" (which evaluates to 67) in call to 
>>> "mboot_hash_extend_log".
431 status = mboot_hash_extend_log(0, (uint8_t *)crtm_version, 
tcgEventHdr.eventSize,
432, (uint8_t 
*)crtm_version);
433 if (status) {
434 printk(BIOS_DEBUG, "Measure CRTM Version returned 
0x%x\n", status);
435 return status;
436 }
/src/mainboard/facebook/fbg1701/romstage.c: 78 in mb_crtm()
72  memset(, 0, sizeof(tcgEventHdr));
73  tcgEventHdr.pcrIndex = MBOOT_PCR_INDEX_0;
74  tcgEventHdr.eventType = EV_S_CRTM_VERSION;
75  tcgEventHdr.eventSize = sizeof(crtm_version);
76  printk(BIOS_DEBUG, "%s: EventSize - %u\n", __func__, 
tcgEventHdr.eventSize);
77 
>>> CID 1428711:(OVERRUN)
>>> Overrunning callee's array of size 32 by passing argument 
>>> "tcgEventHdr.eventSize" (which evaluates to 67) in call to 
>>> "mboot_hash_extend_log".
78  status = mboot_hash_extend_log(0, (uint8_t *)crtm_version,
79 tcgEventHdr.eventSize, ,
80 (uint8_t