[coreboot] [coreboot - Bug #478] X200 booting Linux takes a long time with TSC (`clocksource=hpet` works)
Issue #478 has been updated by Nico Huber. Can you provide a dmesg log? or even better, one with coreboot and one with vendor. It's probably just a flag somewhere that's telling Linux to use TSC. But that's easiest debugged in the OS. Bug #478: X200 booting Linux takes a long time with TSC (`clocksource=hpet` works) https://ticket.coreboot.org/issues/478#change-1470 * Author: Robert Gruber * Status: New * Priority: Normal * Target version: master * Start date: 2023-04-04 * Affected versions: 4.15, 4.16, 4.17, 4.18, 4.19, master * Needs backport to: master * Related links: Thank you for reporting this issue. Does booting with `'tsc=unstable` also work? Please the coreboot log messages for example by running `cbmem -1`. * Affected OS: xubuntu 22.04 LTS, Trisquel 11.0 dmesg: TSC found unstable after boot, most likely due to broken BIOS. Use 'tsc=unstable'. After a period of time the boot finished by auto-switching to hpet. Setting kernel parameter directly to clocksource=hpet the system is booting fast. Why is the faster clocksource tsc not working and tells coreboot is broken ? ---Files cbmem.log (38.6 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] About device tree in Coreboot
Dear Sir This is Inventec BIOS team, we are trying to port Coreboot to our Server Board which is based on Intel CRB ArcherCity. We have to add “Devicetree.cb” files under mainboard folder, right ? We had read the following files but we are still confused and don’t know how to modify those files to match our design. Documentation/getting_started/devicetree.md Documentation/drivers/dt_entries.md We would like to know if there are any training materials or further Docs; particular to “syntax”. that we can refer to. Any kind of helps are appreciated. Thanks Gain Confidentiality Note 本郵件含有英業達股?有限公司機密資訊、或受法律保護之資料，唯有原發信人指定之收信人得?讀或使用本郵件之?容。如?並非被指定之收信人，請立即將本郵件及所有附件予以刪除；請勿?露、儲存或使用本郵件之任何資訊，並請?立即告知原發信人本郵件的傳遞錯誤。謝謝?的合作。 This e-mail transmission and any attachments contain information from Inventec Corporation. The information is confidential and/or privileged and intended to be solely for the use of the individuals or entities named in this e-mail transmission. If you are not the intended recipient, be aware that any disclosure, saving or use of the content of this e-mail transmission and attachments is strictly prohibited. If you have received this email transmission in error, please notify us immediately, and delete the e-mail and attachments. We greatly appreciate your cooperation. ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Introduction as GSoC applicant
Hi dear Coreboot@ list, my name is Philipp and a am applying for the Google Summer of Code to work at Coreboot. I first thought of working on Power8/9 support, but I think that it would take a while until I could help you at all with this, so maybe I will try to contribute there after the GSoC when I know the rest of Coreboot better. So I applied to work at supporting zlib as a compression algorithm and maybe update lz4 and lzma, if needed. Feel free to tell me if you have any comments/suggestions regarding this project. About myself, I am currently studying for my Bachelor's Degree in CS in Darmstadt, Germany, since 2020. If I'm not working or studying, I do some IoT and soldering things, because I like low-level microcontroller and blinky-blinky stuff. ESPecially on ESP32 boards. I also pushed a first commit, doing some linter fixing, if you want to check it out [0]. Regards, Philipp [0] https://review.coreboot.org/c/coreboot/+/74173 OpenPGP_0x2D1CAA6A4608F3DF.asc Description: OpenPGP public key OpenPGP_signature Description: OpenPGP digital signature ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Supermicro X11SSH-LN4F PCI-e bifurcation?
Hi, I installed Coreboot with SeaBIOS on a Supermicro X11SSH-LN4F. The stock BIOS can read two NVMe drives in a Dual m.2 splitter card inserted in the middle slot 5 on the motherboard. But coreboot can not. In the coreboot nconfig menu there is no setting that will enable bifurcation of the x8 slot to x4x4. Is this something that is configurable in any way? /Tomas ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] request for support new hardware from coreboot
Hello Im Artem from Khadas https://www.khadas.com/ We developing new product our hardware based on: Alder Lake ULT 12th Gen Intel Core i7-1280P We have plans to use coreboot as alternative bootloader for our new product We need some information about: 1) coreboot possibilities for current hardware 2) estimated time to create some initial workable prototype 3) what information we need provide for your side at this moment we use BIOS from AMI: Vendor: Amerian Megatrends Core Verion: 5.27 Compiancy: UEFI 2.8; PI 1.7 etc... About us We are Shenzhen Wesion Technology Co., Ltd is the company that owns the brand "Khadas", our company was founded on 5 November 2014. We focus on developing, manufacturing and marketing single board computers (SBCs) ... more info https://www.khadas.com/about Best regards Artem ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Re: Coreboot chat room
Hi David, thanks for your answer. - I believe XMPP is on a state of revive and always got a lot of improvements over the last years. There are plenty of clients and some really good working ones for example Conversations for android (or my own userfriendly fork monocles chat) or siskin for IPhone but also clients for desktop. I think adding XMPP could help both, coreboot and XMPP to get more interested people and developers. But especially XMPP is an official international chat standard which is much more lightweight and therefore much more resource friendly than Slack or Discord. It supports a secure end-to-end encrypted communication, file transfer, one-to-one audio/video calls and more. It is even used by the military and companies. Google once used it too for google talk. The XMPP standards Foundation also has been accepted as a mentoring organization in Goolge summer of codes 2023. For coreboot I would add a news bot to the XMPP chat room which automatically fetches and posts news from the mastodon rss feed or any other rss feed. - Currently the moderation is done by Hans, Ingolf and me. But more moderators can be be added. The latest monocles chat version but also other xmpp clients support a good spam handling like blocking users, message deletion. Additionally the chat room is set to "moderated" which only allows users that are marked by the moderators as members to write in the chat. I would add [2] to the chat rooms description when you accept it. The users of the chat room need to read it then before they are marked as members by the moderators to get writing rights. Kind regards, Arne PS: A list of clients: https://xmpp.org/software/ Am 27. März 2023 01:33:50 MESZ schrieb David Hendricks : >Hi Arne, >A couple of questions about this came up in a recent leadership meeting [1]: >- How does this improve upon the existing options? We already have >IRC, Slack, and Discord channels. Is there something about XMPP that >makes it more compelling than those other options? > >- Who moderates the XMPP chatroom? At the very least there needs to be >admins who can deal with spam, abuse, and enforce community guidelines >[2] when needed. > >[1] >https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkKrgKjeDQ/edit# >[2] >https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/Documentation/community/code_of_conduct.md > > >On Tue, Mar 7, 2023 at 11:00 AM Arne via coreboot >wrote: >> >> Hi, >> I just created a XMPP chat room about coreboot on our public XMPP server and >> I would be happy to make it to an official coreboot chatroom. The server is >> running since 2,5 years and will stay online for at least the next years. >> Maybe you like to join. >> So the main question is, can I write in the chatroom description "official >> coreboot chatroom"? >> >> I would also offer the coreboot delevopers a free XMPP chat account on >> https://ocean.monocles.de/apps/registration/ >> or >> https://ocean.monocles.eu/apps/registration/ >> >> >> Thanks for your project and best regards, >> >> Arne >> ___ >> coreboot mailing list -- coreboot@coreboot.org >> To unsubscribe send an email to coreboot-le...@coreboot.org ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Hardware Compatibility Help
Hi, Hope you are having a wonderful day. Kindly requesting if the following two laptops can install coreboot? Lenovo Yoga 13 Intel Core i7 - Model Number 20175 & Lenovo Thinkpad X1 Carbon Intel Corei7 Please let me know if any further information is required. Regards, Parakawa ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Support Question: "overflow detected" error message on start up (boothole?)
Please tell me who I should contact if the following support question should be directed elsewhere. I have a System 76 computer with coreboot installed. A fine print error message flashes that an "overflow" is detected and I think the file path has "grub" in it. Brief flash, can't see. Is this the boothole vulnerability? It is in the firmware or coreboot, not on a disk grub. I have multiple OS and the message appears independently of loading a particular hard disk, although I have Fedora with the community copr installed on my primary disk. Thanks! ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] [coreboot - Bug #478] X200 booting Linux takes a long time with TSC (`clocksource=hpet` works)
Issue #478 has been updated by Robert Gruber. Bill XIE wrote in #note-4: > Robert Gruber wrote: > > dmesg: TSC found unstable after boot, most likely due to broken BIOS. Use > > 'tsc=unstable'. > > After a period of time the boot finished by auto-switching to hpet. Setting > > kernel parameter directly to clocksource=hpet the system is booting fast. > > > > Why is the faster clocksource tsc not working and tells coreboot is broken ? > > As stated in > https://www.chromium.org/chromium-os/how-tos-and-troubleshooting/tsc-resynchronization/ > , there are 4 types of TSC, while a core 2 cpu only has Constant TSC, which > may change on C state transitions. > > Newer cpu like Ivy Bridge have nonstop_tsc and tsc_deadline in addition to > constant_tsc. They can keep using tsc as clock source. > > Does this issue remain on an x200 running vendor firmware? Only coreboot is affected. On vendor firmware the system boots with kernel defaults and clocksource=hpet fast. Bug #478: X200 booting Linux takes a long time with TSC (`clocksource=hpet` works) https://ticket.coreboot.org/issues/478#change-1469 * Author: Robert Gruber * Status: New * Priority: Normal * Target version: master * Start date: 2023-04-04 * Affected versions: 4.15, 4.16, 4.17, 4.18, 4.19, master * Needs backport to: master * Related links: Thank you for reporting this issue. Does booting with `'tsc=unstable` also work? Please the coreboot log messages for example by running `cbmem -1`. * Affected OS: xubuntu 22.04 LTS, Trisquel 11.0 dmesg: TSC found unstable after boot, most likely due to broken BIOS. Use 'tsc=unstable'. After a period of time the boot finished by auto-switching to hpet. Setting kernel parameter directly to clocksource=hpet the system is booting fast. Why is the faster clocksource tsc not working and tells coreboot is broken ? ---Files cbmem.log (38.6 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] [coreboot - Bug #478] X200 booting Linux takes a long time with TSC (`clocksource=hpet` works)
Issue #478 has been updated by Robert Gruber. Affected OS set to xubuntu 22.04 LTS, Trisquel 11.0 Bug #478: X200 booting Linux takes a long time with TSC (`clocksource=hpet` works) https://ticket.coreboot.org/issues/478#change-1468 * Author: Robert Gruber * Status: New * Priority: Normal * Target version: master * Start date: 2023-04-04 * Affected versions: 4.15, 4.16, 4.17, 4.18, 4.19, master * Needs backport to: master * Related links: Thank you for reporting this issue. Does booting with `'tsc=unstable` also work? Please the coreboot log messages for example by running `cbmem -1`. * Affected OS: xubuntu 22.04 LTS, Trisquel 11.0 dmesg: TSC found unstable after boot, most likely due to broken BIOS. Use 'tsc=unstable'. After a period of time the boot finished by auto-switching to hpet. Setting kernel parameter directly to clocksource=hpet the system is booting fast. Why is the faster clocksource tsc not working and tells coreboot is broken ? ---Files cbmem.log (38.6 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
