[coreboot] Re: how to change FSP-M UPD data in coreboot
Hi Lance, I use Denverton FSP version 004 and have added following code in romstage.c: mupd->FspmConfig.SpsIccClkSscSetting = 0; And it works that FSP sends HECI message to ME to have SSC disabled. Thanks for your great help!! -Hilbert This e-mail and its attachment may contain information that is confidential or privileged, and are solely for the use of the individual to whom this e-mail is addressed. If you are not the intended recipient or have received it accidentally, please immediately notify the sender by reply e-mail and destroy all copies of this email and its attachment. Please be advised that any unauthorized use, disclosure, distribution or copying of this email or its attachment is strictly prohibited. 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子郵件，請立即回覆郵件通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。 ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] how to change FSP-M UPD data in coreboot
Hi, I need to change one UPD data (SpsIccClkSscSetting) of FSP-M structure in Coreboot 4.8.1. I am not sure if it is correct to use HECI message to modify it. Does anyone know how to do it in Coreboot? Actually I have changed that setting in BCT but it was reinited to default when executing in FSP. That’s why I need to change it again in Coreboot. Please help. Thanks. -Hilbert This e-mail and its attachment may contain information that is confidential or privileged, and are solely for the use of the individual to whom this e-mail is addressed. If you are not the intended recipient or have received it accidentally, please immediately notify the sender by reply e-mail and destroy all copies of this email and its attachment. Please be advised that any unauthorized use, disclosure, distribution or copying of this email or its attachment is strictly prohibited. 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子郵件，請立即回覆郵件通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。 ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] RTC issue
Hi, My platform is Intel Denverton with Coreboot 4.8.1 and it can boot up successfully except RTC. There is always an error like “unable to open rtc device (rtc0)” when I try to set clock. But if I use BIOS to boot up again, this error will be disappeared and later boot up with Coreboot and setup hwclock successfully. Does anyone have same experience and know how to fix it? Thanks. -Hilbert This e-mail and its attachment may contain information that is confidential or privileged, and are solely for the use of the individual to whom this e-mail is addressed. If you are not the intended recipient or have received it accidentally, please immediately notify the sender by reply e-mail and destroy all copies of this email and its attachment. Please be advised that any unauthorized use, disclosure, distribution or copying of this email or its attachment is strictly prohibited. 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子郵件，請立即回覆郵件通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。 ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] To modify MCTRL.SPDDIS of Intel Denvertion in coreboot
Hi, Is there anyone can tell me how to change MCTRL.SPDDIS in Coreboot? The Intel Denverton blocks write permission to address A0~AE due to security concern of DIMM SPD, but this also restricts the write access to generic EEPROM access in our platform. So I need to modify the SPDDIS bit to bypass the protection. But I don’t know how to do that in Coreboot. Please help and thanks in advance. -Hilbert This e-mail and its attachment may contain information that is confidential or privileged, and are solely for the use of the individual to whom this e-mail is addressed. If you are not the intended recipient or have received it accidentally, please immediately notify the sender by reply e-mail and destroy all copies of this email and its attachment. Please be advised that any unauthorized use, disclosure, distribution or copying of this email or its attachment is strictly prohibited. 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子郵件，請立即回覆郵件通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。 ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] SSC setting in FSP
Hi, My platform is Intel Denverton with Coreboot 4.8.1 and SSC(Spread Spectrum Clocking) setting is default enabled by FSP even I set it disabled in soft strap pin. Is there any way that I can change it back in Coreboot or how to send command through HECI to configure it? The “Intelmetool” seems only can read. Thanks. -Hilbert This e-mail and its attachment may contain information that is confidential or privileged, and are solely for the use of the individual to whom this e-mail is addressed. If you are not the intended recipient or have received it accidentally, please immediately notify the sender by reply e-mail and destroy all copies of this email and its attachment. Please be advised that any unauthorized use, disclosure, distribution or copying of this email or its attachment is strictly prohibited. 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子郵件，請立即回覆郵件通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。 -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] APIC and lspci
Hi Nico, I think there is no MSI mode in my system. In my case, device 00:14.0 is SATA controller and as you said, there is likely a 1 to 1 mapping, so I expect it should maps to one of IRQ16-23 for IOxAPIC. But from lspci, it is IRQ28 and I want to know if this is changed in Coreboot or in kernel and where to modify it. Another is my MAC (02:00.0) which connects to Denverton through PCI-e, the lspci's output is "pin A routed to IRQ 0". Why IRQ0 is being used? Anything I forgot to configure? I'll check the BWG, but I have to admit I am too "fresh" to understand it :p. If you know something, please advise. Thanks. -Hilbert -Original Message- From: Nico Huber [mailto:nic...@gmx.de] Sent: Tuesday, September 04, 2018 1:46 AM To: Hilbert Tu(杜睿哲_Pegatron); coreboot@coreboot.org Subject: Re: [coreboot] APIC and lspci Hi Hilbert, On 03.09.2018 12:36, Hilbert Tu(杜睿哲_Pegatron) wrote: > I have a customized Intel Denverton-NS platform similar like Harcuvar > CRB. In dmesg, I can see following: > [ 10.973387] ACPI: PCI Interrupt Link [LNKA] (IRQs 6 7 10 *11 12 14 15) > [ 10.981587] ACPI: PCI Interrupt Link [LNKB] (IRQs 6 7 *10 11 12 14 15) > [ 10.989776] ACPI: PCI Interrupt Link [LNKC] (IRQs *6 7 10 11 12 14 15) > [ 10.997961] ACPI: PCI Interrupt Link [LNKD] (IRQs 6 *7 10 11 12 14 15) > [ 11.006147] ACPI: PCI Interrupt Link [LNKE] (IRQs 6 7 10 11 *12 14 15) > [ 11.014332] ACPI: PCI Interrupt Link [LNKF] (IRQs 6 7 10 11 12 *14 15) > [ 11.022518] ACPI: PCI Interrupt Link [LNKG] (IRQs 6 7 10 11 12 14 *15) > [ 11.030697] ACPI: PCI Interrupt Link [LNKH] (IRQs 6 7 10 11 12 14 *15) > And by “lspci -s 00:14.0 -vv”, there is a message “Interrupt: pin A > routed to IRQ 28”. Actually I know in the devicetree.cb, the device 14’s > interrupt is configured by IR08 which routes INTA to PIRQE and LNKE is > using IRQ12. This is the legacy interrupt mode as kernel message dumped. > But in ACPI mode, why does lspci report IRQ28 and how to reconfigure it > in Coreboot? Please help to clarify. Thanks. there is actually a third case, MSI interrupts. It's hard to tell if that is used without seeing the lspci output. MSIs are configured by the OS, not coreboot. In APIC mode, there is likely a 1:1 mapping of the PIRQ LNK* to APIC IRQs; e.g. LNKA -> 16, LNKB -> 17, ..., LNKH -> 23 (this usually can't be changed, but I don't know for sure if that is the case for Denver- ton). It should be documented in the BIOS Writer's Guide for your SoC. Nico This e-mail and its attachment may contain information that is confidential or privileged, and are solely for the use of the individual to whom this e-mail is addressed. If you are not the intended recipient or have received it accidentally, please immediately notify the sender by reply e-mail and destroy all copies of this email and its attachment. Please be advised that any unauthorized use, disclosure, distribution or copying of this email or its attachment is strictly prohibited. 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子郵件，請立即回覆郵件通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。 -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
[coreboot] APIC and lspci
Hi, I have a customized Intel Denverton-NS platform similar like Harcuvar CRB. In dmesg, I can see following: [ 10.973387] ACPI: PCI Interrupt Link [LNKA] (IRQs 6 7 10 *11 12 14 15) [ 10.981587] ACPI: PCI Interrupt Link [LNKB] (IRQs 6 7 *10 11 12 14 15) [ 10.989776] ACPI: PCI Interrupt Link [LNKC] (IRQs *6 7 10 11 12 14 15) [ 10.997961] ACPI: PCI Interrupt Link [LNKD] (IRQs 6 *7 10 11 12 14 15) [ 11.006147] ACPI: PCI Interrupt Link [LNKE] (IRQs 6 7 10 11 *12 14 15) [ 11.014332] ACPI: PCI Interrupt Link [LNKF] (IRQs 6 7 10 11 12 *14 15) [ 11.022518] ACPI: PCI Interrupt Link [LNKG] (IRQs 6 7 10 11 12 14 *15) [ 11.030697] ACPI: PCI Interrupt Link [LNKH] (IRQs 6 7 10 11 12 14 *15) And by “lspci -s 00:14.0 -vv”, there is a message “Interrupt: pin A routed to IRQ 28”. Actually I know in the devicetree.cb, the device 14’s interrupt is configured by IR08 which routes INTA to PIRQE and LNKE is using IRQ12. This is the legacy interrupt mode as kernel message dumped. But in ACPI mode, why does lspci report IRQ28 and how to reconfigure it in Coreboot? Please help to clarify. Thanks. -Hilbert This e-mail and its attachment may contain information that is confidential or privileged, and are solely for the use of the individual to whom this e-mail is addressed. If you are not the intended recipient or have received it accidentally, please immediately notify the sender by reply e-mail and destroy all copies of this email and its attachment. Please be advised that any unauthorized use, disclosure, distribution or copying of this email or its attachment is strictly prohibited. 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子郵件，請立即回覆郵件通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。 -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] how to change PCI device's PFA
Hi Lance, Got it. I’ll check that. Thanks. -Hilbert From: Lance Zhao [mailto:lance.z...@gmail.com] Sent: Saturday, September 01, 2018 1:29 AM To: Hilbert Tu(杜睿哲_Pegatron) Cc: coreboot@coreboot.org Subject: Re: [coreboot] how to change PCI device's PFA Those devices have been fixed from chipset, I don't think any software side can change that. I will prefer to have a quick scan of PCI spec 2.2 first, which mentioned that clearly. On Thu, Aug 30, 2018 at 11:44 PM Hilbert Tu(杜睿哲_Pegatron) mailto:hilbert...@pegatroncorp.com>> wrote: Hi, In my devicetree.cb of Intel Harcuvar CRB, I see the following PCI configuration: device pci 14.0 on end # SATA Controller 1 device pci 15.0 on end # XHCI USB Controller Can I change the device number for each different PCI device? For example, device pci 16.0 on end # SATA Controller 1 device pci 17.0 on end # XHCI USB Controller Is this PCI enumeration same in Coreboot and kernel? Or can I change it dynamically? Thanks. -Hilbert This e-mail and its attachment may contain information that is confidential or privileged, and are solely for the use of the individual to whom this e-mail is addressed. If you are not the intended recipient or have received it accidentally, please immediately notify the sender by reply e-mail and destroy all copies of this email and its attachment. Please be advised that any unauthorized use, disclosure, distribution or copying of this email or its attachment is strictly prohibited. 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子郵件，請立即回覆郵件通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。 -- coreboot mailing list: coreboot@coreboot.org<mailto:coreboot@coreboot.org> https://mail.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
[coreboot] how to change PCI device's PFA
Hi, In my devicetree.cb of Intel Harcuvar CRB, I see the following PCI configuration: device pci 14.0 on end # SATA Controller 1 device pci 15.0 on end # XHCI USB Controller Can I change the device number for each different PCI device? For example, device pci 16.0 on end # SATA Controller 1 device pci 17.0 on end # XHCI USB Controller Is this PCI enumeration same in Coreboot and kernel? Or can I change it dynamically? Thanks. -Hilbert This e-mail and its attachment may contain information that is confidential or privileged, and are solely for the use of the individual to whom this e-mail is addressed. If you are not the intended recipient or have received it accidentally, please immediately notify the sender by reply e-mail and destroy all copies of this email and its attachment. Please be advised that any unauthorized use, disclosure, distribution or copying of this email or its attachment is strictly prohibited. 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子郵件，請立即回覆郵件通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。 -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] USB cannot work
Hi Nico, Thanks. I guess you are right. I'll double check with other payload. Thanks again. -Hilbert -Original Message- From: Nico Huber [mailto:nic...@gmx.de] Sent: Saturday, August 25, 2018 12:38 AM To: Hilbert Tu(杜睿哲_Pegatron) Cc: coreboot@coreboot.org Subject: Re: [coreboot] USB cannot work Hi Hilbert, On 8/24/18 4:22 AM, Hilbert Tu(杜睿哲_Pegatron) wrote: > Do you know how to check USB2.0/USB3.0 in Grub2? I am trying to prove > it. not sure. GRUB has an `lsmod` command, if that lists something with ehci or xhci, that might give a clue. Actually, I would just grep the source code. In my current GRUB master checkout, `git grep -i xhci` returns nothing. > But another question is then why EHCI driver cannot work when > running with Coreboot on Denverton-NS platform? Is that due to only xHCI > controller in Denverton-NS? Yes, an EHCI driver can't work with an xHCI controller (and Denverton has xHCI only, AUIU). Nico This e-mail and its attachment may contain information that is confidential or privileged, and are solely for the use of the individual to whom this e-mail is addressed. If you are not the intended recipient or have received it accidentally, please immediately notify the sender by reply e-mail and destroy all copies of this email and its attachment. Please be advised that any unauthorized use, disclosure, distribution or copying of this email or its attachment is strictly prohibited. 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子郵件，請立即回覆郵件通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。 -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] USB cannot work
Hi Nico, Thanks for your comments. Do you know how to check USB2.0/USB3.0 in Grub2? I am trying to prove it. But another question is then why EHCI driver cannot work when running with Coreboot on Denverton-NS platform? Is that due to only xHCI controller in Denverton-NS? Regards, -Hilbert -Original Message- From: Nico Huber [mailto:nico.hu...@secunet.com] Sent: Thursday, August 23, 2018 5:55 PM To: Hilbert Tu(杜睿哲_Pegatron) Cc: Sumo; coreboot@coreboot.org Subject: Re: [coreboot] USB cannot work Hi Hilbert, Am 23.08.18 um 09:14 schrieb Hilbert Tu(杜睿哲_Pegatron): > Yes, you are right. So can I say Grub2’s driver has issues in supporting > Denverton xHCI controller? I just want a root cause to explain why USB > cannot work in this case. Thanks. I still believe that GRUB doesn't have an xHCI driver. Broadwell-DE has an EHCI controller (alongside the xHCI one) and Rangeley only had EHCI. So you probably always used GRUB with its EHCI driver before. Nico This e-mail and its attachment may contain information that is confidential or privileged, and are solely for the use of the individual to whom this e-mail is addressed. If you are not the intended recipient or have received it accidentally, please immediately notify the sender by reply e-mail and destroy all copies of this email and its attachment. Please be advised that any unauthorized use, disclosure, distribution or copying of this email or its attachment is strictly prohibited. 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子郵件，請立即回覆郵件通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。 -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] USB cannot work
Hi Sumo, Yes, you are right. So can I say Grub2’s driver has issues in supporting Denverton xHCI controller? I just want a root cause to explain why USB cannot work in this case. Thanks. -Hilbert From: Sumo [mailto:kingsu...@gmail.com] Sent: Wednesday, August 22, 2018 10:05 PM To: Hilbert Tu(杜睿哲_Pegatron) Cc: nico.hu...@secunet.com; coreboot@coreboot.org Subject: Re: [coreboot] USB cannot work USB works a charm using CorebootPayloadPkg from Tianocore/EDK2 instead of using GRUB2 as payload (you can use grub anyway to load linux later on, or use any other bootloader without sticking this in the SPI flash image). Em qua, 22 de ago de 2018 às 07:45, Hilbert Tu(杜睿哲_Pegatron) mailto:hilbert...@pegatroncorp.com>> escreveu: Hi Nico, Confused. 1. I saw " pch: usb_xhci_init" in the boot up log and I think xHCI controller was initialized by coreboot 2. I have used coreboot with grub for Intel Rangeley and BDX-DE platform, the USB interface were working with xHCI controller. That means grub has its own xHCI driver. 3. I am trying u-boot as payload now. Sorry I really don't well understand coreboot and grub :P -Hilbert -Original Message- From: Nico Huber [mailto:nico.hu...@secunet.com<mailto:nico.hu...@secunet.com>] Sent: Wednesday, August 22, 2018 4:38 PM To: Hilbert Tu(杜睿哲_Pegatron); coreboot@coreboot.org<mailto:coreboot@coreboot.org> Subject: Re: [coreboot] USB cannot work Hi Hilbert, Am 22.08.18 um 03:24 schrieb Hilbert Tu(杜睿哲_Pegatron): > Maybe you are right. But as I know, CRB Harcuvar is one of supported > board of Coreboot and it includes xHCI controller and USB interfaces. Harcuvar is indeed supported by coreboot. But coreboot only initializes the hardware up to a point where an OS or bootloader can use it. The OS or bootloader still needs its own driver for the hardware. This is very different as in the legacy BIOS/UEFI case (a BIOS would provide a driver but coreboot doesn't). So if you want to use GRUB as a coreboot payload and use USB, GRUB needs its own driver for the xHCI. I would first try to confirm if or if not the xHCI works with other payloads (e.g. SeaBIOS, Tianocore, libpayload based) or an OS. Nico This e-mail and its attachment may contain information that is confidential or privileged, and are solely for the use of the individual to whom this e-mail is addressed. If you are not the intended recipient or have received it accidentally, please immediately notify the sender by reply e-mail and destroy all copies of this email and its attachment. Please be advised that any unauthorized use, disclosure, distribution or copying of this email or its attachment is strictly prohibited. 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子郵件，請立即回覆郵件通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。 -- coreboot mailing list: coreboot@coreboot.org<mailto:coreboot@coreboot.org> https://mail.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] USB cannot work
Hi Nico, Confused. 1. I saw " pch: usb_xhci_init" in the boot up log and I think xHCI controller was initialized by coreboot 2. I have used coreboot with grub for Intel Rangeley and BDX-DE platform, the USB interface were working with xHCI controller. That means grub has its own xHCI driver. 3. I am trying u-boot as payload now. Sorry I really don't well understand coreboot and grub :P -Hilbert -Original Message- From: Nico Huber [mailto:nico.hu...@secunet.com] Sent: Wednesday, August 22, 2018 4:38 PM To: Hilbert Tu(杜睿哲_Pegatron); coreboot@coreboot.org Subject: Re: [coreboot] USB cannot work Hi Hilbert, Am 22.08.18 um 03:24 schrieb Hilbert Tu(杜睿哲_Pegatron): > Maybe you are right. But as I know, CRB Harcuvar is one of supported > board of Coreboot and it includes xHCI controller and USB interfaces. Harcuvar is indeed supported by coreboot. But coreboot only initializes the hardware up to a point where an OS or bootloader can use it. The OS or bootloader still needs its own driver for the hardware. This is very different as in the legacy BIOS/UEFI case (a BIOS would provide a driver but coreboot doesn't). So if you want to use GRUB as a coreboot payload and use USB, GRUB needs its own driver for the xHCI. I would first try to confirm if or if not the xHCI works with other payloads (e.g. SeaBIOS, Tianocore, libpayload based) or an OS. Nico This e-mail and its attachment may contain information that is confidential or privileged, and are solely for the use of the individual to whom this e-mail is addressed. If you are not the intended recipient or have received it accidentally, please immediately notify the sender by reply e-mail and destroy all copies of this email and its attachment. Please be advised that any unauthorized use, disclosure, distribution or copying of this email or its attachment is strictly prohibited. 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子郵件，請立即回覆郵件通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。 -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] USB cannot work
Hi Nico, Maybe you are right. But as I know, CRB Harcuvar is one of supported board of Coreboot and it includes xHCI controller and USB interfaces. -Hilbert This e-mail and its attachment may contain information that is confidential or privileged, and are solely for the use of the individual to whom this e-mail is addressed. If you are not the intended recipient or have received it accidentally, please immediately notify the sender by reply e-mail and destroy all copies of this email and its attachment. Please be advised that any unauthorized use, disclosure, distribution or copying of this email or its attachment is strictly prohibited. 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子郵件，請立即回覆郵件通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。 -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] USB cannot work
Hi, From BWG(BIOS Write Guide), there are two steps needed to be done for USB to work: 1. Pre-Operating Software Initialization 2. EHCI Initialization for Pre-OS Software Usage Does anyone know where these steps are implemented in Coreboot? Thanks. -Hilbert This e-mail and its attachment may contain information that is confidential or privileged, and are solely for the use of the individual to whom this e-mail is addressed. If you are not the intended recipient or have received it accidentally, please immediately notify the sender by reply e-mail and destroy all copies of this email and its attachment. Please be advised that any unauthorized use, disclosure, distribution or copying of this email or its attachment is strictly prohibited. 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子郵件，請立即回覆郵件通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。 -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Denverton FSP usage
I found the related setting under “Generic Drivers” -> “Use FSP TempRamInit & TempRamExit APIs”. Ha. -Hilbert From: Hilbert Tu(杜睿哲_Pegatron) Sent: Monday, August 06, 2018 6:21 PM To: coreboot@coreboot.org Subject: Denverton FSP usage Hi, I have an Intel Denverton (C3538) CPU board and try to use coreboot 4.8 to boot it up. The FSP I have consisted of 3 parts as FSP-T, FSP-M, FSP-S, but I don’t see the settings for specifying FSP-T in coreboot’s menuconfig. From the debug output, I got error code 2526 and I doubt it is due to lack of including FSP-T. Is there anyone can tell how to correctly use FSP-T? Thanks. -Hilbert This e-mail and its attachment may contain information that is confidential or privileged, and are solely for the use of the individual to whom this e-mail is addressed. If you are not the intended recipient or have received it accidentally, please immediately notify the sender by reply e-mail and destroy all copies of this email and its attachment. Please be advised that any unauthorized use, disclosure, distribution or copying of this email or its attachment is strictly prohibited. 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子郵件，請立即回覆郵件通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。 -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
[coreboot] Denverton FSP usage
Hi, I have an Intel Denverton (C3538) CPU board and try to use coreboot 4.8 to boot it up. The FSP I have consisted of 3 parts as FSP-T, FSP-M, FSP-S, but I don’t see the settings for specifying FSP-T in coreboot’s menuconfig. From the debug output, I got error code 2526 and I doubt it is due to lack of including FSP-T. Is there anyone can tell how to correctly use FSP-T? Thanks. -Hilbert This e-mail and its attachment may contain information that is confidential or privileged, and are solely for the use of the individual to whom this e-mail is addressed. If you are not the intended recipient or have received it accidentally, please immediately notify the sender by reply e-mail and destroy all copies of this email and its attachment. Please be advised that any unauthorized use, disclosure, distribution or copying of this email or its attachment is strictly prohibited. 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子郵件，請立即回覆郵件通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。 -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] BDX-DE PCI init fail
Hi guys, Sorry for the late. I spent some time try to use U-Boot as payload but still get infinite reboot…maybe wrong TSC clock frequency in my dts file. About using the Grub2 as payload, it is now working after I modify “–unit=1” to “—unit=0” :P That’s why it hangs… Thanks for all your help. -Hilbert This e-mail and its attachment may contain information that is confidential or privileged, and are solely for the use of the individual to whom this e-mail is addressed. If you are not the intended recipient or have received it accidentally, please immediately notify the sender by reply e-mail and destroy all copies of this email and its attachment. Please be advised that any unauthorized use, disclosure, distribution or copying of this email or its attachment is strictly prohibited. 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子郵件，請立即回覆郵件通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。 -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] BDX-DE PCI init fail
Hi Zoran, Anyway, thanks. I have learnt a lot from the discussion. Thank you all. -Hilbert This e-mail and its attachment may contain information that is confidential or privileged, and are solely for the use of the individual to whom this e-mail is addressed. If you are not the intended recipient or have received it accidentally, please immediately notify the sender by reply e-mail and destroy all copies of this email and its attachment. Please be advised that any unauthorized use, disclosure, distribution or copying of this email or its attachment is strictly prohibited. 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子郵件，請立即回覆郵件通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。 -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] BDX-DE PCI init fail
Hi Werner, Thanks for your information. It works but still has same result. The result is like following. My usb stick is ext4fs formatted and has kernel and rootfs files. I wish SeaBIOS can give me a shell like Grub so that I can specify how to boot next. Or should I create a bootable usb stick? = PEIM FSP is Completed = Returned from FspNotify(EnumInitPhaseReadyToBoot) Jumping to boot code at 000ff06e(7eff6000) CPU0: stack: 00128000 - 00129000, lowest used address 00128b00, stack used: 1280 bytes entry= 0x000ff06e lb_start = 0x0010 lb_size = 0x0012d6d0 buffer = 0x7ed66000 SeaBIOS (version rel-1.10.2-0-g5f4c7b1) BUILD: gcc: (coreboot toolchain v1.44 March 3rd, 2017) 6.3.0 binutils: (GNU Binutils) 2.28 Found mainboard Intel Camelback Mountain CRB Relocating init from 0x000e3860 to 0x7ef74cc0 (size 49824) Found CBFS header at 0xffe00138 multiboot: eax=0, ebx=0 Found 25 PCI devices (max PCI bus is 05) Copying SMBIOS entry point from 0x7efc1000 to 0x000f7140 Copying ACPI RSDP from 0x7efd2000 to 0x000f7110 Using pmtimer, ioport 0x408 WARNING - Timeout at tis_wait_sts:160! WARNING - Timeout at tis_wait_sts:160! Scan for VGA option rom XHCI init on dev 00:14.0: regs @ 0xfea0, 21 ports, 32 slots, 32 byte contexts XHCIprotocol USB 2.00, 8 ports (offset 1), def 3001 XHCIprotocol USB 3.00, 6 ports (offset 16), def 1000 XHCIextcap 0xc1 @ 0xfea08040 XHCIextcap 0xc0 @ 0xfea08070 XHCIextcap 0x1 @ 0xfea0846c EHCI init on dev 00:1a.0 (regs=0xfea18020) EHCI init on dev 00:1d.0 (regs=0xfea19020) WARNING - Timeout at i8042_flush:71! ebda moved from 9f000 to 9e800 AHCI controller at 00:1f.2, iobase 0xfea17000, irq 5 Found 0 lpt ports Found 2 serial ports XHCI no devices found Searching bootorder for: /pci@i0cf8/usb@1d/hub@1/storage@1/*@0/*@0,0 Searching bootorder for: /pci@i0cf8/usb@1d/hub@1/usb-*@1 USB MSC vendor='Generic-' product='Multiple Reader' rev='1.11' type=0 removable=1 ehci_wait_td error - status=80e42 Initialized USB HUB (0 ports used) USB MSC blksize=512 sectors=30777344 Initialized USB HUB (1 ports used) All threads complete. Scan for option roms Running option rom at c000:0003 Running option rom at c100:0003 Searching bootorder for: /pci@i0cf8/pci-bridge@2,2/*@0 Searching bootorder for: /pci@i0cf8/pci-bridge@2,2/*@0,1 Press ESC for boot menu. WARNING - Timeout at tis_wait_sts:160! Searching bootorder for: HALT drive 0x000f70c0: PCHS=0/0/0 translation=lba LCHS=1024/255/63 s=30777344 Space available for UMB: c2000-efb00, f6960-f70c0 Returned 184320 bytes of ZoneHigh e820 map has 9 items: 0: - 0009e800 = 1 RAM 1: 0009e800 - 000a = 2 RESERVED 2: 000f - 0010 = 2 RESERVED 3: 0010 - 7efae000 = 1 RAM 4: 7efae000 - 9000 = 2 RESERVED 5: feb0 - feb1 = 2 RESERVED 6: feb8 - fef0 = 2 RESERVED 7: ff00 - 0001 = 2 RESERVED 8: 0001 - 00028000 = 1 RAM enter handle_19: NULL Booting from Hard Disk... Booting from :7c00 -Hilbert This e-mail and its attachment may contain information that is confidential or privileged, and are solely for the use of the individual to whom this e-mail is addressed. If you are not the intended recipient or have received it accidentally, please immediately notify the sender by reply e-mail and destroy all copies of this email and its attachment. Please be advised that any unauthorized use, disclosure, distribution or copying of this email or its attachment is strictly prohibited. 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子郵件，請立即回覆郵件通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。 -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] BDX-DE PCI init fail
Hi Werner, The SeaBIOS .config is always been reset when I recompile the coreboot. I am trying to figure out how to avoid that. Hi Zoran, I did not get grub2 prompt shell so I cannot do anything. I don't use UEFI or Legacy. I just use grub2 as coreboot's payload and if there is a shell prompt, then I can bring my linux kernel up. -Hilbert -Original Message- From: Zeh, Werner [mailto:werner@siemens.com] Sent: Wednesday, January 10, 2018 1:34 PM To: Hilbert Tu(杜睿哲_Pegatron); coreboot@coreboot.org Cc: David Hendricks; Leo5 Huang(黃儀祥_Pegatron); Zoran Stojsavljevic Subject: AW: [coreboot] BDX-DE PCI init fail Hi Hilbert. It might be nothing but if I have a look at your last attached log I can't see SeaBIOS finding any USB devices. There is just one Error mentioned: >ehci_wait_td error - status=80e42 So what is special with SeaBIOS and Broadwell-DE: you have to unset the config switch called "CONFIG_MALLOC_UPPERMEMORY" in SeaBIOS config. With this option set SeaBIOS has issues with USB on Broadwell-DE. It might help you, just check it and give it a try if not unset already. Werner > -Ursprüngliche Nachricht- > Von: coreboot [mailto:coreboot-boun...@coreboot.org] Im Auftrag von Zoran > Stojsavljevic > Gesendet: Mittwoch, 10. Januar 2018 05:57 > An: Hilbert Tu(杜睿哲_Pegatron) > Cc: Werner Zeh; David Hendricks; coreboot@coreboot.org; Leo5 > Huang(黃儀祥_Pegatron) > Betreff: Re: [coreboot] BDX-DE PCI init fail > > > grub> > > Yup, you have reached the GRUB2 shell. I have no idea what the underlying > system is yuo have done this? UEFI or Legacy? > > If UEFI, this USB will NOT work for Coreboot + SeaBIOS. If Legacy, then I > have no idea why it does not work (it should)!? > > If UEFI, then you might reconsider https://rufus.akeo.ie/ (5 minutes job to > create Legacy bootable USB): > [1] Partition scheme MBR used on BIOS; > [2] File System probably FAT32 (should work). > > Good Luck! > Zoran > ___ > > On Wed, Jan 10, 2018 at 2:49 AM, Hilbert Tu(杜睿哲_Pegatron) > <hilbert...@pegatroncorp.com> wrote: > > Hi Zoran, > > > > I have my USB stick formatted with ext4fs and I am pretty sure the image > > inside is bootable. > > What I mean to get a prompt shell is like following so that I can specify > > my commands. > > > > grub> linux (usb0,1)/bzImage console=ttyS1,115200 console=tty1 > > grub> root=/dev/ra > > m ramdisk_size=102400 > > grub> initrd (usb0,1)/core-image-minimal-initramfs-mohonpeak64.cpio.gz > > grub> boot > > > > But right now it just hangs there and I am looking into GIPO settings > > or maybe I have some wrong settings in ACPI table:( > > > > -Hilbert > > > > This e-mail and its attachment may contain information that is confidential > > or privileged, and are solely for the use of the individual to > whom this e-mail is addressed. If you are not the intended recipient or have > received it accidentally, please immediately notify the > sender by reply e-mail and destroy all copies of this email and its > attachment. Please be advised that any unauthorized use, > disclosure, distribution or copying of this email or its attachment is > strictly prohibited. > > 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子郵件，請立即回覆郵件 > > 通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。 > -- > coreboot mailing list: coreboot@coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] BDX-DE PCI init fail
Hi Zoran, I have my USB stick formatted with ext4fs and I am pretty sure the image inside is bootable. What I mean to get a prompt shell is like following so that I can specify my commands. grub> linux (usb0,1)/bzImage console=ttyS1,115200 console=tty1 root=/dev/ra m ramdisk_size=102400 grub> initrd (usb0,1)/core-image-minimal-initramfs-mohonpeak64.cpio.gz grub> boot But right now it just hangs there and I am looking into GIPO settings or maybe I have some wrong settings in ACPI table:( -Hilbert This e-mail and its attachment may contain information that is confidential or privileged, and are solely for the use of the individual to whom this e-mail is addressed. If you are not the intended recipient or have received it accidentally, please immediately notify the sender by reply e-mail and destroy all copies of this email and its attachment. Please be advised that any unauthorized use, disclosure, distribution or copying of this email or its attachment is strictly prohibited. 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子郵件，請立即回覆郵件通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。 -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] BDX-DE PCI init fail
Hi Zoran, 1. There is a 8GB DDR4 memory in my system. 2. I don't attach any HDD/SSD and I'll try to use Grub2 to access my kernel through USB interface. But I wish I can get shell prompt first before starting kernel. Suppose there should be a prompt for Grub2 or SeaBIOS, doesn't it? -Hilbert This e-mail and its attachment may contain information that is confidential or privileged, and are solely for the use of the individual to whom this e-mail is addressed. If you are not the intended recipient or have received it accidentally, please immediately notify the sender by reply e-mail and destroy all copies of this email and its attachment. Please be advised that any unauthorized use, disclosure, distribution or copying of this email or its attachment is strictly prohibited. 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子郵件，請立即回覆郵件通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。 -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] BDX-DE PCI init fail
Hi David, When I saw following message, I got different result when using different payload for coreboot: == Returned from FspNotify(EnumInitPhaseReadyToBoot) Jumping to boot code at 000ff06e(7eff6000) CPU0: stack: 00129000 - 0012a000, lowest used address 00129b00, stack used: 1280 bytes entry= 0x000ff06e lb_start = 0x0010 lb_size = 0x001302f0 buffer = 0x7ed6 === If U-Boot is used as payload, it just rebooted and restarted again. If Grub2 is used as payload, it just hung there. If SeaBios is used as payload, the result is like following attached file: http://mail.coreboot.org/pipermail/coreboot/attachments/20180105/209695a1/attachment.txt Do you have any idea about this? Is there any action I can do to clarify what cause reboot? Thanks. -Hilbert This e-mail and its attachment may contain information that is confidential or privileged, and are solely for the use of the individual to whom this e-mail is addressed. If you are not the intended recipient or have received it accidentally, please immediately notify the sender by reply e-mail and destroy all copies of this email and its attachment. Please be advised that any unauthorized use, disclosure, distribution or copying of this email or its attachment is strictly prohibited. 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子郵件，請立即回覆郵件通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。 -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] BDX-DE PCI init fail
Hi David, After trying to use SeaBIOS as payload, I got more information about reboot issue as attached file. While U-Boot just reboots directly and Grub hangs, the SeaBIOS’s dump complains “No bootable device” at the end. Do you think is it the cause of reboot? Can I say my U-Boot and Grub versions are not supporting BDX-DE? -Hilbert This e-mail and its attachment may contain information that is confidential or privileged, and are solely for the use of the individual to whom this e-mail is addressed. If you are not the intended recipient or have received it accidentally, please immediately notify the sender by reply e-mail and destroy all copies of this email and its attachment. Please be advised that any unauthorized use, disclosure, distribution or copying of this email or its attachment is strictly prohibited. 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子郵件，請立即回覆郵件通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。 = PEIM FSP is Completed = Returned from FspNotify(EnumInitPhaseReadyToBoot) Jumping to boot code at 000ff06e(7eff6000) CPU0: stack: 00129000 - 0012a000, lowest used address 00129b00, stack used: 1280 bytes entry= 0x000ff06e lb_start = 0x0010 lb_size = 0x001302f0 buffer = 0x7ed6 SeaBIOS (version rel-1.10.2-0-g5f4c7b1) BUILD: gcc: (coreboot toolchain v1.47 August 16th, 2017) 6.3.0 binutils: (GNU Binutils) 2.28 Found mainboard Intel Camelback Mountain CRB Relocating init from 0x000e3940 to 0x7ef74da0 (size 49600) Found CBFS header at 0xffe00138 multiboot: eax=0, ebx=0 Found 25 PCI devices (max PCI bus is 05) Copying SMBIOS entry point from 0x7efc1000 to 0x000f7120 Copying ACPI RSDP from 0x7efd2000 to 0x000f70f0 Using pmtimer, ioport 0x408 Scan for VGA option rom XHCI init on dev 00:14.0: regs @ 0xfea0, 21 ports, 32 slots, 32 byte contexts XHCIprotocol USB 2.00, 8 ports (offset 1), def 3001 XHCIprotocol USB 3.00, 6 ports (offset 16), def 1000 XHCIextcap 0xc1 @ 0xfea08040 XHCIextcap 0xc0 @ 0xfea08070 XHCIextcap 0x1 @ 0xfea0846c EHCI init on dev 00:1a.0 (regs=0xfea18020) EHCI init on dev 00:1d.0 (regs=0xfea19020) WARNING - Timeout at i8042_flush:71! AHCI controller at 00:1f.2, iobase 0xfea17000, irq 0 Found 0 lpt ports Found 2 serial ports XHCI no devices found ehci_wait_td error - status=80e42 Initialized USB HUB (0 ports used) Initialized USB HUB (0 ports used) All threads complete. Scan for option roms Running option rom at c000:0003 Running option rom at c100:0003 Searching bootorder for: /pci@i0cf8/pci-bridge@2,2/*@0 Searching bootorder for: /pci@i0cf8/pci-bridge@2,2/*@0,1 Press ESC for boot menu. Searching bootorder for: HALT Space available for UMB: c2000-ee800, f6940-f70d0 Returned 192512 bytes of ZoneHigh e820 map has 9 items: 0: - 0009fc00 = 1 RAM 1: 0009fc00 - 000a = 2 RESERVED 2: 000f - 0010 = 2 RESERVED 3: 0010 - 7efb = 1 RAM 4: 7efb - 9000 = 2 RESERVED 5: feb0 - feb1 = 2 RESERVED 6: feb8 - fef0 = 2 RESERVED 7: ff00 - 0001 = 2 RESERVED 8: 0001 - 00028000 = 1 RAM enter handle_19: NULL Booting from ROM... Booting from c000:0b91 enter handle_18: NULL Booting from ROM... Booting from c100:0b91 enter handle_18: NULL Booting from Floppy... Boot failed: could not read the boot disk enter handle_18: NULL Booting from Hard Disk... Boot failed: could not read the boot disk enter handle_18: NULL No bootable device. Retrying in 60 seconds. Rebooting. In resume (status=0) In 32bit resume Attempting a hard reboot ACPI hard reset 1:cf9 (6)-- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] BDX-DE PCI init fail
Hi Zoran, About this issue, I decide to follow David's suggestion to comment out the SMBus clock gating and then it can continue booting until load my U-Boot payload. But then it enters infinite reboot as previous attached log "smbus_init_fail_max_dump2.txt". I am not sure if is a side effect or just a new issue. Do you have any recommendation about the reboot? By the way, we have our own BDX-DE board, not Camelback CRB. But just use similar configuration. Thanks. -Hilbert This e-mail and its attachment may contain information that is confidential or privileged, and are solely for the use of the individual to whom this e-mail is addressed. If you are not the intended recipient or have received it accidentally, please immediately notify the sender by reply e-mail and destroy all copies of this email and its attachment. Please be advised that any unauthorized use, disclosure, distribution or copying of this email or its attachment is strictly prohibited. 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子郵件，請立即回覆郵件通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。 -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] BDX-DE PCI init fail
Hi Zoran, I don't understand. We don't have extra MCU and, from following message, we also have correct microcode. Why you mean we should have " PPR 0x50663 PPR PCH "? My understanding is they are in/just the same chip...Please help to clarify. Thanks. >>microcode: sig=0x50663 pf=0x10 revision=0x70e >><<=== >>CPUID: 00050663 -Hilbert This e-mail and its attachment may contain information that is confidential or privileged, and are solely for the use of the individual to whom this e-mail is addressed. If you are not the intended recipient or have received it accidentally, please immediately notify the sender by reply e-mail and destroy all copies of this email and its attachment. Please be advised that any unauthorized use, disclosure, distribution or copying of this email or its attachment is strictly prohibited. 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子郵件，請立即回覆郵件通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。 -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] BDX-DE PCI init fail
Hi Zoran, The log was just at following link: http://mail.coreboot.org/pipermail/coreboot/attachments/20171227/b07eb74e/attachment.txt With messages: MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled By the way, I have tried to use U-Boot and Grub2 as payload, but I don't think the payload was executed since it failed at PCI 00:1f.3 init. -Hilbert -Original Message- From: Zoran Stojsavljevic [mailto:zoran.stojsavlje...@gmail.com] Sent: Saturday, December 30, 2017 2:32 PM To: Hilbert Tu(杜睿哲_Pegatron) Cc: David Hendricks; coreboot@coreboot.org Subject: Re: [coreboot] BDX-DE PCI init fail > I still have same issue even tried to comment out the 1f.3 device in > ./src/mainboard/intel/camel- backmountain_fsp/devicetree.cb then > rebuild coreboot. You wrote that you submitted the log. Is this the full log? I doubt. I do NOT see physical memory layout as well as MTRR layout. Could you, please, submit the full/complete log? Which payload are you using? SeaBIOS? Thank you, Zoran On Fri, Dec 29, 2017 at 5:58 AM, Hilbert Tu(杜睿哲_Pegatron) <hilbert...@pegatroncorp.com> wrote: > Hi David, > > > > Thanks for your information. > > I still have same issue even tried to comment out the 1f.3 device in > ./src/mainboard/intel/camelbackmountain_fsp/devicetree.cb then rebuild > coreboot. > > Could you let me know how to do that? > > > > -Hilbert > > > > From: David Hendricks [mailto:david.hendri...@gmail.com] > Sent: Friday, December 29, 2017 9:46 AM > To: Hilbert Tu(杜睿哲_Pegatron) > Cc: coreboot@coreboot.org > Subject: Re: [coreboot] BDX-DE PCI init fail > > > > Hi Hilbert, > > Have you had any luck? I have a board with a similar problem. > Commenting out the entry for device 1f.3 in devicetree.cb seemed to > help (I copied src/mainboard/intel/camelbackmountain_fsp for my project). > > > > On Wed, Dec 27, 2017 at 2:17 AM, Hilbert Tu(杜睿哲_Pegatron) > <hilbert...@pegatroncorp.com> wrote: > > Hi, > > > > I am porting coreboot on Intel BDX-DE platform and it gets stuck when > init PCI 00:1f.3. This device should be SMBus, serial management bus. > But I don’t know why this happened. Does anyone can give me some hint? > Attached is my boot up log. Thanks in advance. > > > > -Hilbert > > This e-mail and its attachment may contain information that is > confidential or privileged, and are solely for the use of the > individual to whom this e-mail is addressed. If you are not the > intended recipient or have received it accidentally, please > immediately notify the sender by reply e-mail and destroy all copies > of this email and its attachment. Please be advised that any > unauthorized use, disclosure, distribution or copying of this email or its > attachment is strictly prohibited. > 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子郵件，請立即回覆郵件 > 通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。 > > > -- > coreboot mailing list: coreboot@coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot > > > > > -- > coreboot mailing list: coreboot@coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot This e-mail and its attachment may contain information that is confidential or privileged, and are solely for the use of the individual to whom this e-mail is addressed. If you are not the intended recipient or have received it accidentally, please immediately notify the sender by reply e-mail and destroy all copies of this email and its attachment. Please be advised that any unauthorized use, disclosure, distribution or copying of this email or its attachment is strictly prohibited. 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子郵件，請立即回覆郵件通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。 -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] BDX-DE PCI init fail
Hi David, Thanks for your information. I still have same issue even tried to comment out the 1f.3 device in ./src/mainboard/intel/camelbackmountain_fsp/devicetree.cb then rebuild coreboot. Could you let me know how to do that? -Hilbert From: David Hendricks [mailto:david.hendri...@gmail.com] Sent: Friday, December 29, 2017 9:46 AM To: Hilbert Tu(杜睿哲_Pegatron) Cc: coreboot@coreboot.org Subject: Re: [coreboot] BDX-DE PCI init fail Hi Hilbert, Have you had any luck? I have a board with a similar problem. Commenting out the entry for device 1f.3 in devicetree.cb seemed to help (I copied src/mainboard/intel/camelbackmountain_fsp for my project). On Wed, Dec 27, 2017 at 2:17 AM, Hilbert Tu(杜睿哲_Pegatron) <hilbert...@pegatroncorp.com<mailto:hilbert...@pegatroncorp.com>> wrote: Hi, I am porting coreboot on Intel BDX-DE platform and it gets stuck when init PCI 00:1f.3. This device should be SMBus, serial management bus. But I don’t know why this happened. Does anyone can give me some hint? Attached is my boot up log. Thanks in advance. -Hilbert This e-mail and its attachment may contain information that is confidential or privileged, and are solely for the use of the individual to whom this e-mail is addressed. If you are not the intended recipient or have received it accidentally, please immediately notify the sender by reply e-mail and destroy all copies of this email and its attachment. Please be advised that any unauthorized use, disclosure, distribution or copying of this email or its attachment is strictly prohibited. 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子郵件，請立即回覆郵件通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。 -- coreboot mailing list: coreboot@coreboot.org<mailto:coreboot@coreboot.org> https://mail.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
[coreboot] BDX-DE PCI init fail
Hi, I am porting coreboot on Intel BDX-DE platform and it gets stuck when init PCI 00:1f.3. This device should be SMBus, serial management bus. But I don’t know why this happened. Does anyone can give me some hint? Attached is my boot up log. Thanks in advance. -Hilbert This e-mail and its attachment may contain information that is confidential or privileged, and are solely for the use of the individual to whom this e-mail is addressed. If you are not the intended recipient or have received it accidentally, please immediately notify the sender by reply e-mail and destroy all copies of this email and its attachment. Please be advised that any unauthorized use, disclosure, distribution or copying of this email or its attachment is strictly prohibited. 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子郵件，請立即回覆郵件通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。 = PEIM FSP v1.0 (_BDX-DE_ v0.0.3.1) = Loading PEIM at 0x000FFEB8638 EntryPoint=0x000FFEB8CF0 Loading PEIM at 0x000FFEBB080 EntryPoint=0x000FFEBC6BC Loading PEIM at 0x000FFEBCA0C EntryPoint=0x000FFEBCFE0 Loading PEIM at 0x000FFEBE69C EntryPoint=0x000FFEBEC04 Loading PEIM at 0x000FFEBFBCC EntryPoint=0x000FFEC04D8 Loading PEIM at 0x000FFEC245C EntryPoint=0x000FFEC331C Loading PEIM at 0x000FFEC4EE4 EntryPoint=0x000FFEC5B54 Loading PEIM at 0x000FFEC79AC EntryPoint=0x000FFEF3A34 Send HostResetWarning notification to ME. ME UMA: WARNING: HostResetWarning called on non S3 resume flow (0) - ignored = PEIM FSP v1.0 (_BDX-DE_ v0.0.3.1) = Loading PEIM at 0x000FFEB8638 EntryPoint=0x000FFEB8CF0 Loading PEIM at 0x000FFEBB080 EntryPoint=0x000FFEBC6BC Loading PEIM at 0x000FFEBCA0C EntryPoint=0x000FFEBCFE0 Loading PEIM at 0x000FFEBE69C EntryPoint=0x000FFEBEC04 Loading PEIM at 0x000FFEBFBCC EntryPoint=0x000FFEC04D8 Loading PEIM at 0x000FFEC245C EntryPoint=0x000FFEC331C Loading PEIM at 0x000FFEC4EE4 EntryPoint=0x000FFEC5B54 Loading PEIM at 0x000FFEC79AC EntryPoint=0x000FFEF3A34 UMA: Memory retrain occurred during warm reset. Force ME FW reload. ME UMA: BiosAction = 0 Loading PEIM at 0x0007F7F7190 EntryPoint=0x0007F7F814C Loading PEIM at 0x0007F7F2188 EntryPoint=0x0007F7F29D0 Loading PEIM at 0x0007F7E9000 EntryPoint=0x0007F7E96F8 Loading PEIM at 0x0007F7D4000 EntryPoint=0x0007F7D56B0 Loading PEIM at 0x0007F7C5000 EntryPoint=0x0007F7C6290 Loading PEIM at 0x0007F782000 EntryPoint=0x0007F78FA90 Loading PEIM at 0x0007F771000 EntryPoint=0x0007F7722C0 Loading PEIM at 0x0007F766000 EntryPoint=0x0007F766ADC Loading PEIM at 0x0007F751000 EntryPoint=0x0007F7535E4 Loading PEIM at 0x0007F74 EntryPoint=0x0007F7417DC Loading PEIM at 0x0007F717000 EntryPoint=0x0007F7181CC Loading PEIM at 0x0007F70C000 EntryPoint=0x0007F70CFBC Loading PEIM at 0x0007F701000 EntryPoint=0x0007F701C58 FSP HOB is located at 0x7F10 FSP is waiting for NOTIFY romstage_main_continue status: 0 hob_list_ptr: 7f10 FSP Status: 0x0 CBMEM: IMD: root @ 7efff000 254 entries. IMD: root @ 7effec00 62 entries. CBFS: 'Master Header Locator' located CBFS at [100:1fffc0) CBFS: Locating 'fallback/ramstage' CBFS: Found @ offset 15d00 size c745 coreboot-coreboot-unknown Tue Sep 19 06:43:05 UTC 2017 ramstage starting... Moving GDT to 7effe9e0...ok BS: BS_PRE_DEVICE times (us): entry 0 run 2 exit 0 CBFS: 'Master Header Locator' located CBFS at [100:1fffc0) CBFS: Locating 'cpu_microcode_blob.bin' CBFS: Found @ offset 3c80 size 12000 microcode: sig=0x50663 pf=0x10 revision=0x70e CPUID: 00050663 Cores: 2 Stepping: V2 Revision ID: 05 msr(17) = 0010 msr(ce) = 20080833f2810c00 BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 158638 exit 0 Enumerating buses... Show all devs... Before device enumeration. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 DOMAIN: : enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:19.0: enabled 1 PCI: 00:1d.0: enabled 1 PCI: 00:1f.0: enabled 1 PCI: 00:1f.2: enabled 1 PCI: 00:1f.3: enabled 1 PCI: 00:1f.5: enabled 1 Compare with tree... Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 DOMAIN: : enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:19.0: enabled 1 PCI: 00:1d.0: enabled 1 PCI: 00:1f.0: enabled 1 PCI: 00:1f.2: enabled 1 PCI: 00:1f.3: enabled 1 PCI: 00:1f.5: enabled 1 Root Device scanning... root_dev_scan_bus for Root Device enable_dev(Intel(R) Xeon(R) Processor D-1500 Product Family, 7) CPU_CLUSTER: 0 enabled enable_dev(Intel(R) Xeon(R) Processor D-1500 Product Family, 6) DOMAIN: enabled DOMAIN: scanning... PCI: pci_scan_bus for bus 00 enable_dev(Intel(R) Xeon(R) Processor D-1500 Product Family, 2) PCI: 00:00.0 [8086/6f00] ops fsp_header_ptr: ffeb0094 FSP Header Version: 1 FSP Revision: 3.1 PCI: 00:00.0 [8086/6f00] enabled Capability: type 0x0d @ 0x40 Capability: type 0x05 @ 0x60 Capability: type 0x10 @ 0x90 Capability: type 0x01 @ 0xe0 Capability: type 0x0d @ 0x40 Capability: type
Re: [coreboot] Broadwell-DE NS FSP not support
Hi Zoran, Thanks for your suggestion. I’ll try. -Hilbert From: Zoran Stojsavljevic [mailto:zoran.stojsavlje...@gmail.com] Sent: Thursday, October 05, 2017 11:27 AM To: Hilbert Tu(杜睿哲_Pegatron) Cc: coreboot@coreboot.org Subject: Re: [coreboot] Broadwell-DE NS FSP not support Hello Hilbert, You might want to log in case in IPS (INTEL Premier Support) and ask there for INTEL IoT support to help you. https://supporttickets.intel.com/?lang=en-US My best bet, your best path to solution. Zoran On Thu, Oct 5, 2017 at 3:40 AM, Hilbert Tu(杜睿哲_Pegatron) <hilbert...@pegatroncorp.com<mailto:hilbert...@pegatroncorp.com>> wrote: Hi Zoran/Piotr, Yes, the current available FSP does not support BDX-DE NS. I got same information from local Intel FAE. So I don’t know the next step to evaluate my CRB. @Taiidan, Thanks for your information, “6 months for skilled person” ☺ Maybe I should try BIOS/UEFI first. -Hilbert From: Zoran Stojsavljevic [mailto:zoran.stojsavlje...@gmail.com<mailto:zoran.stojsavlje...@gmail.com>] Sent: Wednesday, October 04, 2017 7:57 PM To: Hilbert Tu(杜睿哲_Pegatron) Cc: coreboot@coreboot.org<mailto:coreboot@coreboot.org> Subject: Re: [coreboot] Broadwell-DE NS FSP not support Hello Hilbert, There is none FSP for BDW-DE? Are you sure?? And how did you conclude that??? Here is the answer: https://github.com/IntelFsp/FSP Intel® Xeon® Processor D Product Family (formerly Broadwell-DE, Compliant with FSP v1.0 Specification) Broadwell-DE: git clone -b Broadwell-DE https://github.com/IntelFsp/FSP.git <https://github.com/IntelFsp/FSP.git> git clone -b Broadwell-DE <https://github.com/IntelFsp/FSP.git> https://github.com/IntelFsp/FSP.git <https://github.com/IntelFsp/FSP.git> Zoran ___ On Tue, Oct 3, 2017 at 4:39 AM, Hilbert Tu(杜睿哲_Pegatron) <hilbert...@pegatroncorp.com<mailto:hilbert...@pegatroncorp.com>> wrote: Hi, I have an Intel Broadwell-DE NS CRB and I want to evaluate it with coreboot. But from Intel FSP git, there is no corresponding FSP for Broadwell-DE NS. Does that mean I can’t use coreboot as boot loader if Intel FSP not available for my platform? If not, does anyone know how to do that? Please help. Thanks. -Hilbert This e-mail and its attachment may contain information that is confidential or privileged, and are solely for the use of the individual to whom this e-mail is addressed. If you are not the intended recipient or have received it accidentally, please immediately notify the sender by reply e-mail and destroy all copies of this email and its attachment. Please be advised that any unauthorized use, disclosure, distribution or copying of this email or its attachment is strictly prohibited. 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子郵件，請立即回覆郵件通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。 -- coreboot mailing list: coreboot@coreboot.org<mailto:coreboot@coreboot.org> https://mail.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Broadwell-DE NS FSP not support
Hi Zoran/Piotr, Yes, the current available FSP does not support BDX-DE NS. I got same information from local Intel FAE. So I don’t know the next step to evaluate my CRB. @Taiidan, Thanks for your information, “6 months for skilled person” ☺ Maybe I should try BIOS/UEFI first. -Hilbert From: Zoran Stojsavljevic [mailto:zoran.stojsavlje...@gmail.com] Sent: Wednesday, October 04, 2017 7:57 PM To: Hilbert Tu(杜睿哲_Pegatron) Cc: coreboot@coreboot.org Subject: Re: [coreboot] Broadwell-DE NS FSP not support Hello Hilbert, There is none FSP for BDW-DE? Are you sure?? And how did you conclude that??? Here is the answer: https://github.com/IntelFsp/FSP Intel® Xeon® Processor D Product Family (formerly Broadwell-DE, Compliant with FSP v1.0 Specification) Broadwell-DE: git clone -b Broadwell-DE https://github.com/IntelFsp/FSP.git <https://github.com/IntelFsp/FSP.git> git clone -b Broadwell-DE <https://github.com/IntelFsp/FSP.git> https://github.com/IntelFsp/FSP.git <https://github.com/IntelFsp/FSP.git> Zoran ___ On Tue, Oct 3, 2017 at 4:39 AM, Hilbert Tu(杜睿哲_Pegatron) <hilbert...@pegatroncorp.com<mailto:hilbert...@pegatroncorp.com>> wrote: Hi, I have an Intel Broadwell-DE NS CRB and I want to evaluate it with coreboot. But from Intel FSP git, there is no corresponding FSP for Broadwell-DE NS. Does that mean I can’t use coreboot as boot loader if Intel FSP not available for my platform? If not, does anyone know how to do that? Please help. Thanks. -Hilbert This e-mail and its attachment may contain information that is confidential or privileged, and are solely for the use of the individual to whom this e-mail is addressed. If you are not the intended recipient or have received it accidentally, please immediately notify the sender by reply e-mail and destroy all copies of this email and its attachment. Please be advised that any unauthorized use, disclosure, distribution or copying of this email or its attachment is strictly prohibited. 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子郵件，請立即回覆郵件通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。 -- coreboot mailing list: coreboot@coreboot.org<mailto:coreboot@coreboot.org> https://mail.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
[coreboot] Broadwell-DE NS FSP not support
Hi, I have an Intel Broadwell-DE NS CRB and I want to evaluate it with coreboot. But from Intel FSP git, there is no corresponding FSP for Broadwell-DE NS. Does that mean I can’t use coreboot as boot loader if Intel FSP not available for my platform? If not, does anyone know how to do that? Please help. Thanks. -Hilbert This e-mail and its attachment may contain information that is confidential or privileged, and are solely for the use of the individual to whom this e-mail is addressed. If you are not the intended recipient or have received it accidentally, please immediately notify the sender by reply e-mail and destroy all copies of this email and its attachment. Please be advised that any unauthorized use, disclosure, distribution or copying of this email or its attachment is strictly prohibited. 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子郵件，請立即回覆郵件通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。 -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
