Re: [coreboot] How to extract fsp.bin from image?

2017-01-26 Thread 김유석 책임연구원 

Thank you.


It is very useful to me.



2017-01-26 오전 1:45에 Andy Knowles 이(가) 쓴 글:


Hi,

Use the cbfstool, like so:

build/util/cbfstool/cbfstool build/coreboot.rom extract -n fsp.bin -f 
fsp.bin


Good luck!

Andy

*From:*coreboot [mailto:coreboot-boun...@coreboot.org] *On Behalf Of 
*??? ?

*Sent:* Wednesday, 25 January 2017 08:43
*To:* coreboot@coreboot.org
*Subject:* [coreboot] How to extract fsp.bin from image?

Dear Sir.

My Purpose isextract*"Intel fsp.bin"* from bios image.


*_First_*, (I was know that get possible "Intel fsp.bin" from Intel 
website. and already download It is.)


This time i have a some bios image.

This one is _"ADI_RCCVE-01.00.00.08.rom"_. It is get from ADI.

Another one is _"BIOS.bin"_. It is dump from Intel CRB.

_This image's are perfectly support all function. ex) GbE, PCIe, *spi 
flash*_


I was download the coreboot source from official coreboot git.

And build this source code, It is done.

And attach the "Intel fsp.bin" and "descriptor.bin" to my coreboot 
image(It is a "official coreboot source").


But occured the some problem.

*_First._*Not enable all PCIe port. But was resolved, *I was modify 
the fsp.bin used by BCT.*


*_Second._*Can't access spi flash used by "flashrom" utility. this 
util can't found the spi flash on my board.


But, If i use the "ADI_RCCVE-01.00.00.08.rom" and "Intel CRB's bios 
imge" on my board, can access the spi flash memory used by "flashrom" 
utility.


So, I want to extract "Intel FSP.bin" and "descriptor.bin" from 
"ADI_RCCVE-01.00.00.08.rom" and "Intel CRB's bios imge".


I was success extract the "descriptor.bin"

*But fail the extract "Intel fsp.bin".*

Could help to me?

Thank you.



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[coreboot] How to extract fsp.bin from image?

2017-01-25 Thread 김유석 책임연구원 

Dear Sir.


My Purpose isextract *"Intel fsp.bin"* from bios image.


*_First_*, (I was know that get possible "Intel fsp.bin" from Intel 
website. and already download It is.)



This time i have a some bios image.


This one is _"ADI_RCCVE-01.00.00.08.rom"_. It is get from ADI.

Another one is _"__BIOS.bin"_. It is dump from Intel CRB.

_This image's are per__fectly __support all function.ex) GbE, PCIe, 
_*_spi flash_*



I was download the coreboot source from official coreboot git.

And build this source code, It is done.

And attach the "Intel fsp.bin" and "descriptor.bin" to my coreboot 
image(It is a "official coreboot source").



But occured the some problem.

*_First_**_._* Not enable all PCIe port. But was resolved, *I was modify 
the fsp.bin use**d by BCT.*


_*Second.*_ Can't access spi flash used by "flashrom" utility. this util 
can't found the spi flash on my board.



But, If i use the "ADI_RCCVE-01.00.00.08.rom" and "Intel CRB's bios 
imge" on my board, can access the spi flash memory used by "flashrom" 
utility.



So, I want to extract "Intel FSP.bin" and "descriptor.bin" from 
"ADI_RCCVE-01.00.00.08.rom" and "Intel CRB's bios imge".



I was success extract the "descriptor.bin"

*But fail the extract "Intel fsp.bin".*


Could help to me?


Thank you.


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[coreboot] Not running GbE interface.

2016-06-13 Thread 김유석 책임연구원 

Dear Sir.


My EVB is Rangeley Mohon peak.


I was successfuly build and boot the coreboot on my EVB.

But, not running the GbE interface.


So, I was try to find the mailing list . and Got a some threads.


*1. **Message for **G**bE(**This is **perfectly same **that my issue**)*

https://www.coreboot.org/pipermail/coreboot/2015-January/079074.html

  => But this mail is not include detail procedure.(some link a brokened.)

 Anyway. got a important thing. That "Must need a descriptor.bin".

*2. descripter.bin *

https://www.coreboot.org/pipermail/coreboot/2015-March/079532.html

  => This message recommand that It is easy, the descripter.bin is 
extract from ADI's coreboot binary.

 But i don't have a idea to extract from ADI's coreboot binary.

Please advise to me.

thank you.


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Re: [coreboot] What purpose the "mrc.cache"?

2016-06-02 Thread 김유석 책임연구원 

Dear Martin.


Thank you, your prompt reply. It is very useful to me.


I'll study the document of FSP. and tools.


Thank you.


2016-06-02 오전 5:23에 Martin Roth 이(가) 쓴 글:

1) The MRC cache is a location for saving the state of the memory
registers. These values are typically used to restore the memory
controller state on resume from S3 suspend, or to help the system boot
faster.  On systems using the Rangeley FSP it is not optional as it is
on some other platforms.

2) The file you see in cbfs is actually just a placeholder.  If you
look in that area of the rom, you'll see that it's empty.  It's just
there to reserve the space for coreboot to write the memory register
information into, and to prevent anything else from being put into
that location.

3) The memory code for Rangeley is part of the FSP.  This is currently
only available for the Rangeley chip as a binary blob.  You can
download it, along with the FSP documentation and the Binary
Configuration Tool, from Intel's website:  http://intel.com/fsp

Martin

On Tue, May 31, 2016 at 10:38 PM, 김유석 책임연구원 <kay@hansol.com> wrote:

Dear Sir.


My ENV.

   Platform : intel atom rangeley mohon peak CRB(C2358)


This time, I'm try to study for MRC(Memory Reference Code).


But, I'm can not found a some example code on coreboot source tree.(rangely)


Anyway, I'm get a some hint on last image.


Performing operation on 'COREBOOT' region...
Name   Offset Type Size
cbfs master header 0x0cbfs header  32
fallback/romstage  0x80   stage24356
config 0x6040 raw  440
revision   0x6240 raw  567
cmos_layout.bin0x64c0 cmos_layout  1316
fallback/dsdt.aml  0x6a40 raw  8074
payload_config 0x8a40 raw  1574
payload_revision   0x90c0 raw  244
(empty)0x9200 null 27800
mrc.cache  0xfec0mrc_cache  65536
cpu_microcode_blob.bin 0x1ff00microcode167936
fallback/ramstage  0x48f80stage48170
fallback/payload   0x54c00payload  61309
(empty)0x63bc0null 1163992
fsp.bin0x17fec0   fsp  389120
(empty)0x1def00   null 133528
bootblock  0x1ff8c0   bootblock1528


Question.

  1. What purpose the "mrc.cache"?

  2. Where to location the source code for "mrc.cache" ?

  3. How modify the MRC ? for the sdram.


Thank you.





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[coreboot] What purpose the "mrc.cache"?

2016-06-01 Thread 김유석 책임연구원 

Dear Sir.


My ENV.

  Platform : intel atom rangeley mohon peak CRB(C2358)


This time, I'm try to study for MRC(Memory Reference Code).


But, I'm can not found a some example code on coreboot source tree.(rangely)


Anyway, I'm get a some hint on last image.


Performing operation on 'COREBOOT' region...
Name   Offset Type Size
cbfs master header 0x0cbfs header  32
fallback/romstage  0x80   stage24356
config 0x6040 raw  440
revision   0x6240 raw  567
cmos_layout.bin0x64c0 cmos_layout  1316
fallback/dsdt.aml  0x6a40 raw  8074
payload_config 0x8a40 raw  1574
payload_revision   0x90c0 raw  244
(empty)0x9200 null 27800
*mrc.cache  0xfec0 mrc_cache  65536*
cpu_microcode_blob.bin 0x1ff00microcode167936
fallback/ramstage  0x48f80stage48170
fallback/payload   0x54c00payload  61309
(empty)0x63bc0null 1163992
fsp.bin0x17fec0   fsp  389120
(empty)0x1def00   null 133528
bootblock  0x1ff8c0   bootblock1528


*Question.*

 1. What purpose the "mrc.cache"?

 2. Where to location the source code for "mrc.cache" ?

 3. How modify the MRC ? for the sdram.


Thank you.




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Re: [coreboot] SeaBios serial(RX) is not running.

2016-05-27 Thread 김유석 책임연구원 

Dear Sir.

Thank's your work.


Enable the bi-direction serial console is done.


2016-05-20 오후 8:36에 Kyösti Mälkki 이(가) 쓴 글:



On Tue, May 17, 2016 at 10:46 PM, Martin Roth > wrote:


Hi,
  If you want bi-directional serial port in SeaBIOS, I think you need
to stick with the version from Sage. As far as I know, it's never been
supported in the upstream SeaBIOS version.


I have pulled this serial to keyboard mapping change from SageBIOS and 
posted on the seabios list today. Hitting ESC and changing boot media 
seemed to work.


BR,
Kyösti



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[coreboot] How to change the Core input voltage setting?

2016-05-27 Thread 김유석 책임연구원 

Dear Sir.


My HW enginner required to me. that Change the setting of "Core input 
voltage".



But, I don't know everything this one. Because x86 platform is first 
time of my develop life.


Anyway, I'm try to find the something on coreboot source code.

But, still unknow.


So, I need a start point or key point that Initial code for "Core input 
voltage".



Please advise to me.

Thank you.

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[coreboot] How to control the GPIO on x86 rangely?

2016-05-27 Thread 김유석 책임연구원 

Dear Sir.


My platform is intel rangely.


I'm must contol the GPIO pins, But i'm can't found the example code on 
coreboot source tree.



Could you show me the example code to control GPIO?


Thank you.


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[coreboot] SeaBios serial(RX) is not running.

2016-05-17 Thread 김유석 책임연구원 

Dear Sir.


Thank's your advise. everytime.


*Finially*, I was succsss the boot using coreboot.


But I have a *little problem.*


_*I'm can't typing throuth the serial.*_


My x86 BOX is only support serial console.


So, Serial console is very important.


*But **t**he **Sea**Bios is **Serial RX is fail*. I guess.


Coreboot => TX OK

SeaBios => TX OK. *RX Fail*

GRUB2 => TX OK, RX OK.

Linux(ubuntu 15.04) => TX OK, RX OK.


*TX OK* => Can see the log message throught the serial console.

*RX F**ail* => Can not typing throught the serial console.


I'm try to change the bootloader SeaBios to U-boot. and *U-boot is a TX, 
RX OK.*



Serial RX fail is a just SeaBios problem(Not HW issue). I guess.(Vendor 
builded coreboot(SeaBios) is TX/RX OK)



Please advise to me.


Thank you.





#
# Automatically generated file; DO NOT EDIT.
# SeaBIOS Configuration
#

#
# General Features
#
CONFIG_COREBOOT=y
# CONFIG_QEMU is not set
# CONFIG_CSM is not set
# CONFIG_QEMU_HARDWARE is not set
CONFIG_THREADS=y
CONFIG_RELOCATE_INIT=y
CONFIG_BOOTMENU=y
CONFIG_BOOTSPLASH=y
CONFIG_BOOTORDER=y
CONFIG_COREBOOT_FLASH=y
CONFIG_LZMA=y
CONFIG_CBFS_LOCATION=0
CONFIG_MULTIBOOT=y
CONFIG_ENTRY_EXTRASTACK=y
# CONFIG_MALLOC_UPPERMEMORY is not set
CONFIG_ROM_SIZE=0

#
# Hardware support
#
CONFIG_ATA=y
# CONFIG_ATA_DMA is not set
# CONFIG_ATA_PIO32 is not set
CONFIG_AHCI=y
CONFIG_SDCARD=y
CONFIG_MEGASAS=y
CONFIG_FLOPPY=y
CONFIG_FLASH_FLOPPY=y
CONFIG_PS2PORT=y
CONFIG_USB=y
CONFIG_USB_UHCI=y
CONFIG_USB_OHCI=y
CONFIG_USB_EHCI=y
CONFIG_USB_XHCI=y
CONFIG_USB_MSC=y
CONFIG_USB_UAS=y
CONFIG_USB_HUB=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_MOUSE=y
CONFIG_SERIAL=y
CONFIG_LPT=y
CONFIG_RTC_TIMER=y
CONFIG_HARDWARE_IRQ=y
CONFIG_PMTIMER=y
CONFIG_TSC_TIMER=y

#
# BIOS interfaces
#
CONFIG_DRIVES=y
CONFIG_CDROM_BOOT=y
CONFIG_CDROM_EMU=y
CONFIG_PCIBIOS=y
CONFIG_APMBIOS=y
CONFIG_PNPBIOS=y
CONFIG_OPTIONROMS=y
CONFIG_PMM=y
CONFIG_BOOT=y
CONFIG_KEYBOARD=y
CONFIG_KBD_CALL_INT15_4F=y
CONFIG_MOUSE=y
CONFIG_S3_RESUME=y
CONFIG_VGAHOOKS=y
# CONFIG_DISABLE_A20 is not set
CONFIG_TCGBIOS=y

#
# VGA ROM
#
CONFIG_NO_VGABIOS=y
# CONFIG_VGA_GEODEGX2 is not set
# CONFIG_VGA_GEODELX is not set
# CONFIG_VGA_COREBOOT is not set
# CONFIG_BUILD_VGABIOS is not set
CONFIG_VGA_EXTRA_STACK_SIZE=512

#
# Debugging
#
CONFIG_DEBUG_LEVEL=1
CONFIG_DEBUG_SERIAL=y
CONFIG_DEBUG_SERIAL_PORT=0x2f8
CONFIG_DEBUG_COREBOOT=y
#
# Automatically generated file; DO NOT EDIT.
# SeaBIOS Configuration
#

#
# General Features
#
CONFIG_COREBOOT=y
# CONFIG_QEMU is not set
# CONFIG_CSM is not set
# CONFIG_QEMU_HARDWARE is not set
CONFIG_THREADS=y
CONFIG_RELOCATE_INIT=y
CONFIG_BOOTMENU=y
CONFIG_BOOTSPLASH=y
CONFIG_BOOTORDER=y
CONFIG_COREBOOT_FLASH=y
CONFIG_LZMA=y
CONFIG_CBFS_LOCATION=0
CONFIG_MULTIBOOT=y
CONFIG_ENTRY_EXTRASTACK=y
# CONFIG_MALLOC_UPPERMEMORY is not set
CONFIG_ROM_SIZE=0

#
# Hardware support
#
CONFIG_ATA=y
# CONFIG_ATA_DMA is not set
# CONFIG_ATA_PIO32 is not set
CONFIG_AHCI=y
CONFIG_SDCARD=y
CONFIG_MEGASAS=y
CONFIG_FLOPPY=y
CONFIG_FLASH_FLOPPY=y
CONFIG_PS2PORT=y
CONFIG_USB=y
CONFIG_USB_UHCI=y
CONFIG_USB_OHCI=y
CONFIG_USB_EHCI=y
CONFIG_USB_XHCI=y
CONFIG_USB_MSC=y
CONFIG_USB_UAS=y
CONFIG_USB_HUB=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_MOUSE=y
CONFIG_SERIAL=y
CONFIG_LPT=y
CONFIG_RTC_TIMER=y
CONFIG_HARDWARE_IRQ=y
CONFIG_PMTIMER=y
CONFIG_TSC_TIMER=y

#
# BIOS interfaces
#
CONFIG_DRIVES=y
CONFIG_CDROM_BOOT=y
CONFIG_CDROM_EMU=y
CONFIG_PCIBIOS=y
CONFIG_APMBIOS=y
CONFIG_PNPBIOS=y
CONFIG_OPTIONROMS=y
CONFIG_PMM=y
CONFIG_BOOT=y
CONFIG_KEYBOARD=y
CONFIG_KBD_CALL_INT15_4F=y
CONFIG_MOUSE=y
CONFIG_S3_RESUME=y
CONFIG_VGAHOOKS=y
# CONFIG_DISABLE_A20 is not set
CONFIG_TCGBIOS=y

#
# VGA ROM
#
CONFIG_NO_VGABIOS=y
# CONFIG_VGA_GEODEGX2 is not set
# CONFIG_VGA_GEODELX is not set
# CONFIG_VGA_COREBOOT is not set
# CONFIG_BUILD_VGABIOS is not set
CONFIG_VGA_EXTRA_STACK_SIZE=512

#
# Debugging
#
CONFIG_DEBUG_LEVEL=1
CONFIG_DEBUG_SERIAL=y
CONFIG_DEBUG_SERIAL_PORT=0x2f8
CONFIG_DEBUG_COREBOOT=y
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