[coreboot] Re: Does Coreboot support the following options to enable/disable?
Hi Lance, The settings are meant for BroadwellDE not Denverton. Are these options too supported in BroadwellDE for coreboot? uncore power management Uncore frequency scaling -enabled performance p-limit -enabled cpu p-state control enhanced intel speedstep technology -disabled Hardware P-States Hardware P-States -Disabled HardwarePM nInterrupts -Disabled EPP Enable -Enabled Memory NUMA Optimized -Enabled Regards, AC ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Re: Does Coreboot support the following options to enable/disable?
Hi Ranga, Exactly, only Hyperthreading is available. I could not find Intel Virtualization Tech , MLC streamer, etc. So here's my question if all these options support coreboot for Xeon D-15xx? Thanks&Regards, Ashmita Chakraborty From: Ranga Rao Sent: Wednesday, July 3, 2019 1:15:07 PM To: Ashmita Chakraborty; coreboot@coreboot.org Subject: RE: [coreboot] Re: Does Coreboot support the following options to enable/disable? Hi Ashmita, I could see HyperThreading Enable/Disable in Upd_Data_region FSP-master\BroadwellDEFspBinPkg\include\fspvpd.h Regards Ranga From: Ranga Rao Sent: Wednesday 3 July 2019 08:18 To: Ashmita Chakraborty ; coreboot@coreboot.org Subject: [coreboot] Re: Does Coreboot support the following options to enable/disable? Hi Ashmita, Broadwell-DE / Xeon D support still depends Intel's closed-source FSP (Firmware Support Package) binary-only blobs. Broadwell-DE SoC / Xeon D Support Added To Coreboot Hope you could configure them through fsp_upd_data? Regards Ranga From: Ashmita Chakraborty mailto:ashmita.chakrabo...@ltts.com>> Sent: Wednesday 3 July 2019 08:14 To: Ranga Rao mailto:ranga...@ircona.com>>; coreboot@coreboot.org<mailto:coreboot@coreboot.org> Subject: Re: [coreboot] Does Coreboot support the following options to enable/disable? Dear Ranga, These options are meant for Xeon D-15xx series family. So will the coreboot support these options? The coreboot will be built for Xeon D-15xx processor. Yes, I have access to them in fsp_early_init through fsp_upd_data. Thanks&Regards, Ashmita Chakraborty From: Ranga Rao mailto:ranga...@ircona.com>> Sent: Tuesday, July 2, 2019 8:41 PM To: Ashmita Chakraborty; coreboot@coreboot.org<mailto:coreboot@coreboot.org> Subject: RE: [coreboot] Does Coreboot support the following options to enable/disable? Hi, As these features are processor/SoC specific and they are part of FSPM, they should be configurable during fsp early init in coreboot, though you may not find a KConfig option to enable/disable Do you have access to them in fsp_early_init through fsp_upd_data? Regards Ranga -Original Message- From: ashmita.chakrabo...@ltts.com<mailto:ashmita.chakrabo...@ltts.com> mailto:ashmita.chakrabo...@ltts.com>> Sent: Tuesday 2 July 2019 07:34 To: coreboot@coreboot.org<mailto:coreboot@coreboot.org> Subject: [coreboot] Does Coreboot support the following options to enable/disable? Does the coreboot support the following options to enable/disable: HyperThreading- Disabled Execute Disable Bit - Enabled Intel Virtualization Tech- Enabled Intel (R) TXT- Disabled Enhanced Error Containment Mode -Disabled MLC Streamer -Enabled MLC Spatial Prefetcher -Enabled DUC Data Prefetcher -Enabled DUC Instruction Prefetcher-Enabled LLC Prefetch - Enabled Intel Configurable TDB -Enabled TDP Level -level 2 Please let me know. Thanks in advance. Regards, Ashmita Chakraborty ___ coreboot mailing list -- coreboot@coreboot.org<mailto:coreboot@coreboot.org> To unsubscribe send an email to coreboot-le...@coreboot.org<mailto:coreboot-le...@coreboot.org> L&T Technology Services Ltd www.LTTS.com<http://www.LTTS.com> This Email may contain confidential or privileged information for the intended recipient (s). If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system. L&T Technology Services Ltd www.LTTS.com This Email may contain confidential or privileged information for the intended recipient (s). If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system. ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Re: Does Coreboot support the following options to enable/disable?
Hi Ranga, Yes, Xeon D depends on Intels's FSP. I have explored that the coreboot will be built on Xeon D but I am not confident enough that those options could be configured through fsp_upd_data. Thanks&Regards, Ashmita Chakraborty From: Ranga Rao Sent: Wednesday, July 3, 2019 12:47:59 PM To: Ashmita Chakraborty; coreboot@coreboot.org Subject: RE: [coreboot] Does Coreboot support the following options to enable/disable? Hi Ashmita, Broadwell-DE / Xeon D support still depends Intel's closed-source FSP (Firmware Support Package) binary-only blobs. Broadwell-DE SoC / Xeon D Support Added To Coreboot Hope you could configure them through fsp_upd_data? Regards Ranga From: Ashmita Chakraborty Sent: Wednesday 3 July 2019 08:14 To: Ranga Rao ; coreboot@coreboot.org Subject: Re: [coreboot] Does Coreboot support the following options to enable/disable? Dear Ranga, These options are meant for Xeon D-15xx series family. So will the coreboot support these options? The coreboot will be built for Xeon D-15xx processor. Yes, I have access to them in fsp_early_init through fsp_upd_data. Thanks&Regards, Ashmita Chakraborty From: Ranga Rao mailto:ranga...@ircona.com>> Sent: Tuesday, July 2, 2019 8:41 PM To: Ashmita Chakraborty; coreboot@coreboot.org<mailto:coreboot@coreboot.org> Subject: RE: [coreboot] Does Coreboot support the following options to enable/disable? Hi, As these features are processor/SoC specific and they are part of FSPM, they should be configurable during fsp early init in coreboot, though you may not find a KConfig option to enable/disable Do you have access to them in fsp_early_init through fsp_upd_data? Regards Ranga -Original Message- From: ashmita.chakrabo...@ltts.com<mailto:ashmita.chakrabo...@ltts.com> mailto:ashmita.chakrabo...@ltts.com>> Sent: Tuesday 2 July 2019 07:34 To: coreboot@coreboot.org<mailto:coreboot@coreboot.org> Subject: [coreboot] Does Coreboot support the following options to enable/disable? Does the coreboot support the following options to enable/disable: HyperThreading- Disabled Execute Disable Bit - Enabled Intel Virtualization Tech- Enabled Intel (R) TXT- Disabled Enhanced Error Containment Mode -Disabled MLC Streamer -Enabled MLC Spatial Prefetcher -Enabled DUC Data Prefetcher -Enabled DUC Instruction Prefetcher-Enabled LLC Prefetch - Enabled Intel Configurable TDB -Enabled TDP Level -level 2 Please let me know. Thanks in advance. Regards, Ashmita Chakraborty ___ coreboot mailing list -- coreboot@coreboot.org<mailto:coreboot@coreboot.org> To unsubscribe send an email to coreboot-le...@coreboot.org<mailto:coreboot-le...@coreboot.org> L&T Technology Services Ltd www.LTTS.com This Email may contain confidential or privileged information for the intended recipient (s). If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system. L&T Technology Services Ltd www.LTTS.com This Email may contain confidential or privileged information for the intended recipient (s). If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system. ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Re: Does Coreboot support the following options to enable/disable?
Dear Ranga, These options are meant for Xeon D-15xx series family. So will the coreboot support these options? The coreboot will be built for Xeon D-15xx processor. Yes, I have access to them in fsp_early_init through fsp_upd_data. Thanks&Regards, Ashmita Chakraborty From: Ranga Rao Sent: Tuesday, July 2, 2019 8:41 PM To: Ashmita Chakraborty; coreboot@coreboot.org Subject: RE: [coreboot] Does Coreboot support the following options to enable/disable? Hi, As these features are processor/SoC specific and they are part of FSPM, they should be configurable during fsp early init in coreboot, though you may not find a KConfig option to enable/disable Do you have access to them in fsp_early_init through fsp_upd_data? Regards Ranga -Original Message- From: ashmita.chakrabo...@ltts.com Sent: Tuesday 2 July 2019 07:34 To: coreboot@coreboot.org Subject: [coreboot] Does Coreboot support the following options to enable/disable? Does the coreboot support the following options to enable/disable: HyperThreading- Disabled Execute Disable Bit - Enabled Intel Virtualization Tech- Enabled Intel (R) TXT- Disabled Enhanced Error Containment Mode -Disabled MLC Streamer -Enabled MLC Spatial Prefetcher -Enabled DUC Data Prefetcher -Enabled DUC Instruction Prefetcher-Enabled LLC Prefetch - Enabled Intel Configurable TDB -Enabled TDP Level -level 2 Please let me know. Thanks in advance. Regards, Ashmita Chakraborty ___ coreboot mailing list -- coreboot@coreboot.org<mailto:coreboot@coreboot.org> To unsubscribe send an email to coreboot-le...@coreboot.org<mailto:coreboot-le...@coreboot.org> L&T Technology Services Ltd www.LTTS.com This Email may contain confidential or privileged information for the intended recipient (s). If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system. ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Does Coreboot support the following options to enable/disable?
Does the coreboot support the following options to enable/disable: HyperThreading- Disabled Execute Disable Bit - Enabled Intel Virtualization Tech- Enabled Intel (R) TXT- Disabled Enhanced Error Containment Mode -Disabled MLC Streamer -Enabled MLC Spatial Prefetcher -Enabled DUC Data Prefetcher -Enabled DUC Instruction Prefetcher-Enabled LLC Prefetch - Enabled Intel Configurable TDB -Enabled TDP Level -level 2 Please let me know. Thanks in advance. Regards, Ashmita Chakraborty ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
