[coreboot] Re: Coreboot on the Lenovo X220
On 2020-02-20 18:00, Richard Hughes wrote: On Thu, 20 Feb 2020 at 16:56, Christoph Zechner wrote: Using CONFIG_USE_NATIVE_RAMINIT not set I get the slightly more helpful: have you tried booting with only one RAM stick? If they're not identical, coreboot tends to hang and not boot at all in my experience. They're indeed not identical; I'll try later, thanks. Should I be using CONFIG_USE_NATIVE_RAMINIT on the X220 or not? On my two x220s with working coreboot, I have "CONFIG_USE_NATIVE_RAMINIT=y" in my config, so yes. :-) In my experience (and it is mentioned somewhere in the wiki as well, I think) coreboot also tends to misbehave when the RAM is slightly badly seated. Cheers Christoph Richard ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Re: Coreboot on the Lenovo X220
Hi, On 2020-02-20 17:33, Richard Hughes wrote: Hi all, I'm trying to install coreboot on an ageing Lenovo X220 (4287-CTO) to help advance the fwupd plugin support. I'm the fwupd and LVFS maintainer so having an actual coreboot machine running Fedora would be a very useful thing indeed. I've tried many different .configs, and most of the data in the wiki and various blog posts is very old (multiple years) and as yet I haven't manage to build anything that boots, or even turns on the display for that matter. Using spkmodem I am able to get some debugging output. Using CONFIG_USE_NATIVE_RAMINIT I get (ending in): SPD probe channel1, slot0 Not a DDR3 SPD! No valid XMP profile found. Not a DDR3 SPD! SPD probe channel1, slot1JNot a DDR3 SPD! No valid XMP profile found. Not a DDR3 SPD! No DIMMs were found This is with 4+4GB of PC3 RAM, more details available on request. Using CONFIG_USE_NATIVE_RAMINIT not set I get the slightly more helpful: have you tried booting with only one RAM stick? If they're not identical, coreboot tends to hang and not boot at all in my experience. Cheers Christoph FMAP: area COREBOOT found @ 710200 (982528 bytes) CBFS: Locating 'mrc.bin' CBFS: Found @ offset 8fdc0 size 2fc94 System Agent: Starting up... System Agent: Initializing PCH System Agent: Initializing PCH (SMBUS) System Agent: Initializing PCH (USB) System Agent: Initializing PCH (SA Init) SA PciExpress skipped (pcie_init is 0) System Agent: Initializing PCH (Me UMA) System Agent: Initializing Memory System Agent: failed to locate restore data hob! System Agent: Done. ...and then the system just hangs. If anyone has a working .config for the X220 (although if it's using an old version of coreboot, the git tag you used would be very useful). If anyone knows what those messages mean, I'm also very grateful. Thanks! Richard. ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Re: X220 and coreboot?
Hi, On 2020-02-12 11:11, Eero Volotinen wrote: > Hi List, > > Does anyone have dump of this bios as I don't have spi programmer? :( > do you need a ready-to-flash coreboot ROM? Did I understand correctly? Cheers Christoph > Eero > > ___ > coreboot mailing list -- coreboot@coreboot.org > To unsubscribe send an email to coreboot-le...@coreboot.org > ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Re: X220 and coreboot?
Ah, I see. I guess, you could flash coreboot on your device, but I REALLY would advice to make a backup of your existing BIOS first, in case anything goes wrong Cheers Christoph On 2020-02-12 11:48, Eero Volotinen wrote: > Well. Sorry, if this is very stupid question, but trying to follow > instructions at: https://thiccpad.blogspot.com/# > > Step: /ifdtool -x original.bin # original.bin// is the firmware you read > from the motherboard/ > / > / > /and I don't have this original.bin as it readed from bios chip of > motherboard?/ > / > / > /Is it needed or not?/ > / > / > > Eero > > On Wed, Feb 12, 2020 at 12:44 PM Christoph Zechner <mailto:zech...@vrvis.at>> wrote: > > Hi, > > On 2020-02-12 11:11, Eero Volotinen wrote: > > Hi List, > > > > Does anyone have dump of this bios as I don't have spi programmer? :( > > > > do you need a ready-to-flash coreboot ROM? Did I understand correctly? > > Cheers > Christoph > > > > Eero > > > > ___ > > coreboot mailing list -- coreboot@coreboot.org > <mailto:coreboot@coreboot.org> > > To unsubscribe send an email to coreboot-le...@coreboot.org > <mailto:coreboot-le...@coreboot.org> > > > ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Re: [SeaBIOS] Booting Memtest86+ from CBFS fails
Hi Mike! Thank you so much for this, I was getting really frustrated with memtest and coreboot, but this solved it. The only problem that remains now, is memtest is now the first entry and thus default in seabios which is rather inconvenient. Have you tried changing the boot order too? I took a look at the documentation [1] but was not sure if this is the right way to do this. :-/ Thanks in advance! Cheers Christoph [1] https://www.coreboot.org/SeaBIOS#Configuring_boot_order On 01/11/2019 11:43, Mike Banon wrote: Perhaps a bit late, but I've found a coreboot's memtest86+ payload is buggy compared to memtest86+ floppy (which could be downloaded from memtest.org and added to CBFS to be accessible as SeaBIOS menu entry). In addition to your observed problem: at AMD Lenovo G505S and maybe some other coreboot laptops, the USB devices like keyboard are not working at coreboot's memtest86+ while working fine at all the other payloads using "libpayload" (i.e. coreinfo or tint) - so it's not a libpayload problem - and also the same USB keyboards are working at memtest86+ floppy. So it is obvious something is broken at 86+ payload source code. Also, with LZMA compression 86+ floppy occupies much less space than 86+ payload. So, aside from academic/research purposes, I do not see any advantages of 86+ payload compared to 86+ floppy - only disadvantages: larger size and troubled USB. I've seriously considered submitting a patch which replaces coreboot's memtest86+ payload with a floppy (download, compare its' checksum and then insert to CBFS), but then I thought that maybe someone could need 86+ payload as a coding example. If you would like to try out a floppy (e.g. because something else - like 2GB support - could be also broken at 86+ payload, while working fine at 86+ floppy booted through SeaBIOS) , here are the instructions: 1) Download the latest 5.01 version of memtest86+ from memtest86.org : wget https://www.memtest.org/download/5.01/memtest86+-5.01.floppy.zip 2) Calculate its' sha256 : sha256sum ./memtest86+-5.01.floppy.zip should be 2a2d4c1234c9130e1da5fea941ccfbaa343739d5b3302b5f3f9b24077868f8ee ./memtest86+-5.01.floppy.zip 3) If sha256 is correct, unzip ./memtest86+-5.01.floppy.zip . You'll get a "floppy" directory with these files: ls ./floppy/ dd.exe install64.bat install.bat memtestp.bin rawrite.exe README.txt You only need memtestp.bin , sha256 of which is " ddd4a2ba44c312aa4f2c7506a388cc2ca7f1caec60c3c6d80ed8a9f0b43d529c " 4) Size of memtestp.bin file is 150024 bytes. To be understood by SeaBIOS, it needs to be expanded to 1474560 bytes (by zeroes), which could be done with this command: dd if=/dev/zero of=./memtestp.bin bs=1 count=1 seek=1474559 conv=notrunc sha256 of expanded memtestp.bin file will be " 364535abd0d105da9396df6015e480c4d4c52b07dcc4e1d4756bde8ef87a30f1 " 5) Now it could be added to the compiled coreboot.rom with this command: ./build/cbfstool ./build/coreboot.rom add -f ./floppy/memtestp.bin -n floppyimg/memtestp.lzma -t raw -c lzma If done everything correctly, it will be available at SeaBIOS boot menu as Ramdisk [memtestp] Best regards, Mike Banon On Sun, Jul 28, 2019 at 8:40 AM Martin Kepplinger wrote: Hi, I use the simple coreboot config https://github.com/merge/skulls/blob/master/x230/free-defconfig-555419f356 on today's coreboot master branch HEAD (403f433238), using SeaBIOS 1.12.1. When choosing memtest86+ in SeaBIOS' menu, "Booting from CBFS" gets printed but nothing else happens. Booting into nvramcui or coreinfo works though. (earlier, at least on coreboot 555419f356, using the same version of SeaBIOS, things were fine). Can you imagine why? thanks, martin ___ SeaBIOS mailing list -- seab...@seabios.org To unsubscribe send an email to seabios-le...@seabios.org ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] coreboot on new Supermicro boards with AMD Epyc CPUs?
Hi there, is anyone working on coreboot for new supermicro boards with AMD Epyc CPUs right now or is planning on doing this? I'd appreciate any information for future upgrade plans. :-) Thanks in advance! Best regards Christoph Zechner ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] coreboot not working on Supermicro X11SSH-CTF
00 00 00 00 00 00 00 00 00 00 00 00 00 fef03b68: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... fef03d38: 00 00 00 01 00 18 00 00 a0 ef 00 00 00 00 00 00 fef03d48: 00 00 00 00 00 00 00 00 15 01 00 00 12 02 00 ff fef03d58: 01 00 07 03 00 00 00 00 00 00 00 00 00 00 00 00 fef03d68: 54 45 53 54 01 00 01 01 01 01 00 02 00 02 02 02 TEST fef03d78: 00 00 00 01 00 02 02 00 00 00 00 00 00 00 00 00 fef03d88: 00 00 00 01 07 07 07 07 07 07 07 07 07 07 07 07 fef03d98: 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 fef03da8: 07 07 07 07 02 02 02 02 02 02 02 02 02 02 02 02 fef03db8: 02 02 02 02 b8 0b 02 00 10 27 02 00 00 00 00 00 .'.. fef03dc8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... fef03de8: 00 00 00 20 00 01 00 00 01 01 00 01 00 01 00 00 ... fef03df8: 01 00 01 01 00 00 00 00 00 00 00 00 00 00 00 00 fef03e08: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... fef03e88: 00 00 00 00 00 00 aa 55 ...U POST: 0x92 Next step was taking the amberlake (kabylake was not working) fps files from the Intel repo [1] and using those to build coreboot with it (added option "Use the IntelFSP based binaries" and their paths) Any help would be much appreciated, thank you in advance! Best regards Christoph Zechner [1] https://github.com/IntelFsp/FSP/tree/master/AmberLakeFspBinPkg ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
