[coreboot] Re: Caby lake support
Thanks for quick response. I see below release- this support is added. https://coreboot.org/releases/coreboot-4.8.1-relnotes.txt Is there any reference board used with this chipset , which can be referred as some POC? From: Angel Pons Sent: 20 February 2019 15:55 To: Mayuri Tendulkar Cc: coreboot Subject: Re: [coreboot] Caby lake support ** This mail has been sent from an external source ** Hello, On Wed, Feb 20, 2019, 11:23 Mayuri Tendulkar mailto:mayuri.tendul...@aricent.com> wrote: Is there support for Intel Cabylake chipset in latest coreboot? Kaby Lake? Yes. = Please refer to http://www.aricent.com/email-disclaimer for important disclosures regarding this electronic communication. = ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Caby lake support
Hi Team Is there support for Intel Cabylake chipset in latest coreboot? [cid:image001.png@01D4C934.5B4BE590] Regards Mayuri = Please refer to http://www.aricent.com/email-disclaimer for important disclosures regarding this electronic communication. = ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
Re: [coreboot] SVID interface support on Intel Baytrail
We want to access this from Linux kernel Ubuntu 14.04.5 From: Zoran Stojsavljevic [mailto:zoran.stojsavlje...@gmail.com] Sent: 01 February 2017 14:33 To: Mayuri Tendulkar Cc: coreboot Subject: Re: [coreboot] SVID interface support on Intel Baytrail > In our design, we are using SVID interface on Intel Baytrail for accessing > PMIC. From where? BIOS? Linux kernel? Which SW package? What about EC in these equations? Zoran On Wed, Feb 1, 2017 at 9:26 AM, Mayuri Tendulkar mailto:mayuri.tendul...@aricent.com>> wrote: Hi In our design, we are using SVID interface on Intel Baytrail for accessing PMIC. But in coreboot, we don’t see any support enabled for this interface for Baytrail. Does anybody have idea how to access this interface? Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- coreboot mailing list: coreboot@coreboot.org<mailto:coreboot@coreboot.org> https://www.coreboot.org/mailman/listinfo/coreboot "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] SVID interface support on Intel Baytrail
Hi In our design, we are using SVID interface on Intel Baytrail for accessing PMIC. But in coreboot, we don't see any support enabled for this interface for Baytrail. Does anybody have idea how to access this interface? Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] SMBIOS table enablement in coreboot
We are using coreboot 4.4 only, because when I do dmidecode – t 0, its showing me bios version as 4.4-573. Still type 17 doesn’t come up. How we can access DIMM information from HOB? From: cheng yichen [mailto:blessyic...@gmail.com] Sent: 25 January 2017 15:35 To: Mayuri Tendulkar Cc: David Hendricks ; coreboot Subject: Re: [coreboot] SMBIOS table enablement in coreboot Hi Mayuri I have the same question with braswell coreboot that the source code is got from intel. Intel source code don't implement smbios type 17. but you can get dimm information in HOB that is created in FSB image. If you use coreboot4.4 for your bay trail platform. I think the type 17 is created. Thank you 2017-01-25 17:48 GMT+08:00 Mayuri Tendulkar mailto:mayuri.tendul...@aricent.com>>: Hi David Thanks for response. So are there any other settings which enable Type 17 i.e. DDR data information in SMBIOS? We don’t see this Type 17 information in our table. Regards Mayuri From: David Hendricks [mailto:dhend...@google.com<mailto:dhend...@google.com>] Sent: 18 January 2017 01:58 To: Mayuri Tendulkar mailto:mayuri.tendul...@aricent.com>> Cc: coreboot mailto:coreboot@coreboot.org>> Subject: Re: [coreboot] SMBIOS table enablement in coreboot Hi Mayuri, On Sun, Jan 15, 2017 at 5:40 PM, Mayuri Tendulkar mailto:mayuri.tendul...@aricent.com>> wrote: Hi David Yes, below are settings for our system. As we are using Intel Baytrail, does this SMBIOS manufacturer shd be Intel? That's up to you. Mainboard manufacturer, along with product name, serial number, and version, are strings which are expected to be assigned by the vendor. You may set these in your mainboard's Kconfig file. The Macbook 2.1 port shows an example of how to do this: https://review.coreboot.org/cgit/coreboot.git/tree/src/mainboard/apple/macbook21/Kconfig#n32. Other SMBIOS tables such as memory info is generated automatically by coreboot. For example, the type 4 table should have details about your processor manufacturer (Intel) as well as information which implies Baytrail (CPU family, model, and stepping). CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="x" # CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set CONFIG_GENERATE_SMBIOS_TABLES=y CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="" Regards Mayuri From: David Hendricks [mailto:dhend...@google.com<mailto:dhend...@google.com>] Sent: 14 January 2017 08:19 To: Mayuri Tendulkar mailto:mayuri.tendul...@aricent.com>> Cc: coreboot mailto:coreboot@coreboot.org>> Subject: Re: [coreboot] SMBIOS table enablement in coreboot Hi Mayuri, Do you have GENERATE_SMBIOS_TABLES enabled in your config? On Fri, Jan 13, 2017 at 12:56 AM, Mayuri Tendulkar mailto:mayuri.tendul...@aricent.com>> wrote: Hi We are using coreboot for our board based on Intel Baytrail 3845. When we use dmidecode –t to get DDR details, we get empty. It means data is missing in SMBIOS. Are there any settings in coreboot to enable this? Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- coreboot mailing list: coreboot@coreboot.org<mailto:coreboot@coreboot.org> https://www.coreboot.org/mailman/listinfo/coreboot -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If yo
Re: [coreboot] SMBIOS table enablement in coreboot
Hi David Thanks for response. So are there any other settings which enable Type 17 i.e. DDR data information in SMBIOS? We don’t see this Type 17 information in our table. Regards Mayuri From: David Hendricks [mailto:dhend...@google.com] Sent: 18 January 2017 01:58 To: Mayuri Tendulkar Cc: coreboot Subject: Re: [coreboot] SMBIOS table enablement in coreboot Hi Mayuri, On Sun, Jan 15, 2017 at 5:40 PM, Mayuri Tendulkar mailto:mayuri.tendul...@aricent.com>> wrote: Hi David Yes, below are settings for our system. As we are using Intel Baytrail, does this SMBIOS manufacturer shd be Intel? That's up to you. Mainboard manufacturer, along with product name, serial number, and version, are strings which are expected to be assigned by the vendor. You may set these in your mainboard's Kconfig file. The Macbook 2.1 port shows an example of how to do this: https://review.coreboot.org/cgit/coreboot.git/tree/src/mainboard/apple/macbook21/Kconfig#n32. Other SMBIOS tables such as memory info is generated automatically by coreboot. For example, the type 4 table should have details about your processor manufacturer (Intel) as well as information which implies Baytrail (CPU family, model, and stepping). CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="x" # CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set CONFIG_GENERATE_SMBIOS_TABLES=y CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="" Regards Mayuri From: David Hendricks [mailto:dhend...@google.com<mailto:dhend...@google.com>] Sent: 14 January 2017 08:19 To: Mayuri Tendulkar mailto:mayuri.tendul...@aricent.com>> Cc: coreboot mailto:coreboot@coreboot.org>> Subject: Re: [coreboot] SMBIOS table enablement in coreboot Hi Mayuri, Do you have GENERATE_SMBIOS_TABLES enabled in your config? On Fri, Jan 13, 2017 at 12:56 AM, Mayuri Tendulkar mailto:mayuri.tendul...@aricent.com>> wrote: Hi We are using coreboot for our board based on Intel Baytrail 3845. When we use dmidecode –t to get DDR details, we get empty. It means data is missing in SMBIOS. Are there any settings in coreboot to enable this? Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- coreboot mailing list: coreboot@coreboot.org<mailto:coreboot@coreboot.org> https://www.coreboot.org/mailman/listinfo/coreboot -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] SMBIOS table enablement in coreboot
Hi David Yes, below are settings for our system. As we are using Intel Baytrail, does this SMBIOS manufacturer shd be Intel? CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="x" # CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set CONFIG_GENERATE_SMBIOS_TABLES=y CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="" Regards Mayuri From: David Hendricks [mailto:dhend...@google.com] Sent: 14 January 2017 08:19 To: Mayuri Tendulkar Cc: coreboot Subject: Re: [coreboot] SMBIOS table enablement in coreboot Hi Mayuri, Do you have GENERATE_SMBIOS_TABLES enabled in your config? On Fri, Jan 13, 2017 at 12:56 AM, Mayuri Tendulkar mailto:mayuri.tendul...@aricent.com>> wrote: Hi We are using coreboot for our board based on Intel Baytrail 3845. When we use dmidecode –t to get DDR details, we get empty. It means data is missing in SMBIOS. Are there any settings in coreboot to enable this? Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- coreboot mailing list: coreboot@coreboot.org<mailto:coreboot@coreboot.org> https://www.coreboot.org/mailman/listinfo/coreboot -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] SMBIOS table enablement in coreboot
Hi We are using coreboot for our board based on Intel Baytrail 3845. When we use dmidecode -t to get DDR details, we get empty. It means data is missing in SMBIOS. Are there any settings in coreboot to enable this? Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] USB 2.0 test pattern support on Bayley Bay
Hi Team We are trying to do the eye pattern test on USB2.0 on Bayley Bay board. But we are not able to see the test pattern support from BIOS side. Do we have any settings in coreboot to enable this? This works fine on any Linux laptop/desktop Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Any changes to coreboot for low latency kernel
Hi I have below 2 queries: 1)Do we need to do any changes in coreboot to support low latency kernel? 2) Is there a way to communicate from SeaBIOS to GRUB regarding selection of any particular partition for recover? 3)Has anybody tested TPM (Trusted platform module for Intel SOC) with coreboot and seabios? Any help will be appreciated. Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Intel EMT/RMT tool with Coreboot
Hi Team I am exploring usage of Intel memory related tools with coreboot for Intel BayTrail processors. As per their guide, it works on Valley View BIOS with some MRC settings. Has anybody explored on this? Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] USB3.0 enumeration in Baytrail E3845 with coreboot
Hi Zoran Thanks for your inputs. I am checking on Ubuntu. As per minnowmax, devicetree.cb file, below like says default will be EHCI. How we should change it at runtime, what is the setting? device pci 14.0 on end # 8086 0F35 - USB XHCI - Onboard & HSEC - Enabling both EHCI and XHCI will default to EHCI if not changed at runtime device pci 1d.0 on end # 8086 0F34 - USB EHCI - Enabling both EHCI and XHCI will default to EHCI if not changed at runtime regards Mayuri From: Zoran Stojsavljevic [mailto:zoran.stojsavlje...@gmail.com] Sent: 04 August 2016 01:06 To: Mayuri Tendulkar Cc: coreboot Subject: Re: [coreboot] USB3.0 enumeration in Baytrail E3845 with coreboot Hello Mayuri, Some of us (at least me) know that INTEL USB 3.0 implementations have here and there mortal problems for years, as well as in CORE, also in ATOM families. There are lists of problems, but most of them are closed Intellectual Properties, INTEL Inside. I had yesterday terrible problem to set CANON PIXMA MG3650 home printer edition I bought in Saturn to pair over USB with my mobile i5-4300 INTEL Inside HSW laptop (CPUID 0x40561), so I needed 4 hours to investigate and find the interim solution for INTEL buggy embedded USB 3.0 root port (it is consumers' QA issue with INTEL design, so INTEL should take care of this, my best guess)... :-(( In this lieu I will advise you the two way approach. One is to contact/to engage with your INTEL FAE/representative, and ask him about the problems which are well described in internal INTEL documents (BYT wise). The other approach is to work out these problems yourself. So, there are several facts about the USB 3.0. There are (my best guess) some BYT USB fixes done by other people in Coreboot. I'll let these people to speak for themselves. If? You can also try to bring some Linux distros (Fedora for example) and try to see what is going on while you bring up the system (dmesg log). Also you can do the following commands: lsusb -v lsusb -t At least, you can do lsusb --h to see options which can help you to start debugging this issue. Zoran On Wed, Aug 3, 2016 at 11:23 AM, Mayuri Tendulkar mailto:mayuri.tendul...@aricent.com>> wrote: Hi I am facing issue in enumerating USB3.0 device on baytrail processor with coreboot with seabios. Is there any setting in coreboot where we need to enable this separately. Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- coreboot mailing list: coreboot@coreboot.org<mailto:coreboot@coreboot.org> https://www.coreboot.org/mailman/listinfo/coreboot "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] USB3.0 enumeration in Baytrail E3845 with coreboot
Hi I am facing issue in enumerating USB3.0 device on baytrail processor with coreboot with seabios. Is there any setting in coreboot where we need to enable this separately. Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Query to release the code for new board
Hi Team I would like to know how process of releasing code for new board works in coreboot community? For example, when BayleyBay CRB or Minnowboard Max was release, is it only code changes released, mainly related to Mainboard. How TXE and Descriptor.bin for these openly available boards are shared with community? Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] TXE and Descriptor bin management in Coreboot
Ok, so do we need to ask Intel if we use Intel baytrail processor? How we can create this descriptor.bin? What we observed is if we use descriptor.bin, and not TXE, still system boots up fine. Need to understand the impact of not having TXE. But if we don't use descriptor, it seems system is booting based on current, but display doesn't come up. -Original Message- From: Martin Roth [mailto:gauml...@gmail.com] Sent: 13 July 2016 15:36 To: Mayuri Tendulkar Cc: coreboot Subject: Re: [coreboot] TXE and Descriptor bin management in Coreboot Hi Mayuri, The descriptor.bin file is relatively specific to each board. This sets the soft-straps, gives information about the ROM chip being used on that particular board, and sets the sizes of the areas on the SPI ROM. As for the TXE/ME/SPS/xxx binary, this would be specific to the CPU/SOC family at the very least. Some chips will work with an ME read off of a different board that has the same chip. As I recall, others chips have specific settings encoded in this binary as well as in the descriptor. This might just be for Xeon class chips, or it might be more widespread at this point Martin On Wed, Jul 13, 2016 at 4:05 PM, Mayuri Tendulkar wrote: > Hi Team > > > > I would like to know how we can handle TXE and descriptor bin in Coreboot? > > > > Is there any generic file for Intel processors which can be used > rather than any proprietary bin files? > > > > Regards > > Mayuri > > "DISCLAIMER: This message is proprietary to Aricent and is intended > solely for the use of the individual to whom it is addressed. It may > contain privileged or confidential information and should not be > circulated or used for any purpose other than for what it is intended. > If you have received this message in error, please notify the > originator immediately. If you are not the intended recipient, you are > notified that you are strictly prohibited from using, copying, > altering, or disclosing the contents of this message. Aricent accepts > no responsibility for loss or damage arising from the use of the > information transmitted by this email including damage from virus." > > -- > coreboot mailing list: coreboot@coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] TXE and Descriptor bin management in Coreboot
Hi Team I would like to know how we can handle TXE and descriptor bin in Coreboot? Is there any generic file for Intel processors which can be used rather than any proprietary bin files? Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Help on setting clock speed in coreboot
Hi Zoran Thanks for ur suggestions. When I mentioned I got brkthru means- I was able to bringup coreboot with seabios and Ubuntu linux up on my customized board with E3845. Display comes up fine. But serial is still having some issue and keeps giving out some garbage, not sure what is the problem. Tiano core payload is still not working, so currently managing with seabios, but that’s next on the list to debug. Any advice on this? Anybody has tried this? ‘If you did make it with normal AMI/PHOENIX BIOS, you should try to install Fedora 24 on the top of it, and install PuTTY terminal (# dnf install putty). Please, try to receive something on serial over USB (most likely ttyUSB0 device when you insert the serial to USB gadget), settings: 115200, 8, 1, no parity, no flow control. BYT in general, especially BYT-I, has (as I recall) all good with serial ports, which is not always the case with some other families. This should work.’ n This you are saying after loading OS, I shd check if serial works or not right. I can check that. But main point is if I need to debug more on coreboot to optimize/tune anything more for my board, I don’t have serial up. n Display comes up and directly shows payload is loaded, so not able to get whats happening before that. Regards Mayuri From: Zoran Stojsavljevic [mailto:zoran.stojsavlje...@gmail.com] Sent: 13 July 2016 10:43 To: Naveed Ghori Cc: Mayuri Tendulkar ; coreboot Subject: Re: [coreboot] Help on setting clock speed in coreboot > We got some brkthru today. Though serial still shows garbage, we got bios up > and then OS also. > USB, display came up, but serial still no luck. I assumed in my answer that your reference INTEL Valley Island board with E3825 works with serial port. Did not get the point. Did you get Coreboot running on custom E3845, then after Tiano Core as payload, or you just made it work with normal BIOS (with Intel BIOS Vendors - IBVs helping you) for your custom board? If you did make it with normal AMI/PHOENIX BIOS, you should try to install Fedora 24 on the top of it, and install PuTTY terminal (# dnf install putty). Please, try to receive something on serial over USB (most likely ttyUSB0 device when you insert the serial to USB gadget), settings: 115200, 8, 1, no parity, no flow control. BYT in general, especially BYT-I, has (as I recall) all good with serial ports, which is not always the case with some other families. This should work. I have for you few suggestions: try to swap your E3825 (Dual Core) SoC with E3845 (Quad Core) SoC (exact one you are using on your custom board) on your reference board (on Valley Island), and to install/program appropriate INTEL/AMI BIOS which supports E3845 Reference Valley Island. These two should be pin-to-pin compatible. Maybe even old BIOS will work... If you are lucky (so before BIOS reprogramming you should try this)! Then if E3845 by any chance works, to try again serial tests. Also you can take another path and swap another (new) E3845 with currenly used E3845 on your custom board. Maybe your SoC's Serial I/Os on the board are damaged... Could also happen. You can also try to place E3825 from Reference Valley Island to your custom board and try to see if it'll pass BIOS?! If happens, try to test serial and see what happens them? Please, do not forget the following: the boards equipped with BYT-i E3845 Stepping D0, and with E3845 Stepping B3 are DUAL Channel memory SoCs. E3825 Si D0 is SINGLE channel one. I know it (probably) does not have too much to do with your problem (just keep this info in mind). This can also influence your PCB design, since you have different PCBs... Could be also remote source of the problem?! My two ad-hoc cent to this problem. ;-) Best Regards, Zoran On Wed, Jul 13, 2016 at 3:36 AM, Naveed Ghori mailto:naveed.gh...@dti.com.au>> wrote: Great to hear! Serial does give out some useful information too so it will be useful. Maybe try a different board if you have multiples. From: Mayuri Tendulkar [mailto:mayuri.tendul...@aricent.com<mailto:mayuri.tendul...@aricent.com>] Sent: Wednesday, 13 July 2016 8:21 AM To: Naveed Ghori; coreboot Subject: Re: Help on setting clock speed in coreboot Hi We got some brkthru today. Though serial still shows garbage, we got bios up and then OS also. USB, display came up, but serial still no luck. We will continue debugging. Thanks for all support. We are using serial to USB, we tried putty as well as minicom. Regards Mayuri From: Naveed Ghori [mailto:naveed.gh...@dti.com.au] Sent: 12 July 2016 17:12 To: Mayuri Tendulkar mailto:mayuri.tendul...@aricent.com>>; coreboot mailto:coreboot@coreboot.org>> Subject: Re: Help on setting clock speed in coreboot The only thing I can think of is to use an oscilloscope to see if the signal is clear. No changes were made to the USB as it just comes up to as a COM Port and I connect using putty
Re: [coreboot] Help on setting clock speed in coreboot
Hi Minnowboard also uses the same pin BD14 (GPIO_S0_SC[57]) as TX and 61 as RX and baud rate 115200. We have not enabled post codes, but only enabled serial port console o/p. It works fine on Minnowboard, but not on this. So not getting any clue. Regards Mayuri From: Naveed Ghori [mailto:naveed.gh...@dti.com.au] Sent: 11 July 2016 20:03 To: Mayuri Tendulkar ; coreboot Subject: Re: Help on setting clock speed in coreboot First thing is to get serial output as there will probably be other hurdles before the display works. I used coreboot bayleybay as the basis and it had the port mentioned (pin BD14 (GPIO_S0_SC[57]))) setup for debug output and the baud rate of 115200. Minnowboard may be different. Also, I had to setup the full 8MB of flash using the FITC tool but this is probably not your issue since you probably have serial output already. All I can think of is baud rate setting under console in "make menuconfig". Also the output may be setup to output POST codes only in which case to a text terminal it will like only junk is coming out. Make sure console debug level is set to DEBUG or SPEW to get a lot more debug initially. Also Enable "Serial Port Console output" From: Mayuri Tendulkar [mailto:mayuri.tendul...@aricent.com] Sent: Tuesday, 12 July 2016 10:53 AM To: Naveed Ghori Subject: Re: Help on setting clock speed in coreboot We didn't change anything. Our base is valley island. As it was not having serial, we took tht part same as Minnowboard (PCU UART) Tried different rates but doesn't work. We checked TTL levels, so we were seeing freq as 38.4, so tried tht also. Somehow its stuck somewhere as we don't see USB and display also not coming, but nt able to get exact data due to serial prints. From: Naveed Ghori [mailto:naveed.gh...@dti.com.au] Sent: 11 July 2016 19:48 To: Mayuri Tendulkar mailto:mayuri.tendul...@aricent.com>> Subject: Re: Help on setting clock speed in coreboot Did you change anything? Is your base Bayley Bay? The default setting for it are 115200 with the output pin as per below. Check the console settings in the menuconfig. If you are getting junk then I assume it is already enabled but maybe just the baud is modified by mistake. From: Mayuri Tendulkar [mailto:mayuri.tendul...@aricent.com] Sent: Tuesday, 12 July 2016 10:45 AM To: Naveed Ghori Subject: Re: Help on setting clock speed in coreboot But what settings to be added in coreboot config? From: Naveed Ghori [mailto:naveed.gh...@dti.com.au] Sent: 11 July 2016 18:42 To: Mayuri Tendulkar mailto:mayuri.tendul...@aricent.com>>; coreboot mailto:coreboot@coreboot.org>> Subject: Re: Help on setting clock speed in coreboot We take the pins direct off the E3845 (only really need the tx (pin BD14 (GPIO_S0_SC[57]))). The pins direct are TTL so we had to use a TTL-USB serial port converter. From: Mayuri Tendulkar [mailto:mayuri.tendul...@aricent.com] Sent: Tuesday, 12 July 2016 9:37 AM To: Naveed Ghori; coreboot Subject: Re: Help on setting clock speed in coreboot Thanks. We tried 115200, but it didn't work. We checked TTL levels and tried to match, but no luck. Are you using PCU UART (same as minnowboard) or anything different? From: Naveed Ghori [mailto:naveed.gh...@dti.com.au] Sent: 11 July 2016 18:17 To: Mayuri Tendulkar mailto:mayuri.tendul...@aricent.com>>; coreboot mailto:coreboot@coreboot.org>> Subject: Re: Help on setting clock speed in coreboot Hi, Garbage usually means baud rate. Did you try 115200baud? If you are still getting garbage I would recommend seeing it on the scope and making sure voltage levels are fine. The output by default would be TTL level and may need to be converted. I have used some TTL (1.8V if I remember correctly (TTL-232RG) to convert the signal so I could read the output. Cheers, Naveed From: coreboot [mailto:coreboot-boun...@coreboot.org] On Behalf Of Mayuri Tendulkar Sent: Tuesday, 12 July 2016 8:27 AM To: coreboot Subject: [coreboot] Help on setting clock speed in coreboot Hi Team I have a customized board based on Intel valley island design. Reference design uses Intel Baytrail processor E3825, while my design is using E3845. I am customizing coreboot for this E3845, but getting just garbage on coreboot, so not able to debug where it is stuck. When I add memory test as secondary payload, I cd see some operations happening on console but not able to decode it. Tried with all possible baud rates, but no success. USB and display also not enumerating. Can you please give some clue? Is it due to different core speed for E3835(1.33GHZ) vs E3845(1.91GHz). Where is the option to change this in coreboot? Appreciate your support. Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for
Re: [coreboot] Help on setting clock speed in coreboot
Thanks. We tried 115200, but it didn't work. We checked TTL levels and tried to match, but no luck. Are you using PCU UART (same as minnowboard) or anything different? From: Naveed Ghori [mailto:naveed.gh...@dti.com.au] Sent: 11 July 2016 18:17 To: Mayuri Tendulkar ; coreboot Subject: Re: Help on setting clock speed in coreboot Hi, Garbage usually means baud rate. Did you try 115200baud? If you are still getting garbage I would recommend seeing it on the scope and making sure voltage levels are fine. The output by default would be TTL level and may need to be converted. I have used some TTL (1.8V if I remember correctly (TTL-232RG) to convert the signal so I could read the output. Cheers, Naveed From: coreboot [mailto:coreboot-boun...@coreboot.org] On Behalf Of Mayuri Tendulkar Sent: Tuesday, 12 July 2016 8:27 AM To: coreboot Subject: [coreboot] Help on setting clock speed in coreboot Hi Team I have a customized board based on Intel valley island design. Reference design uses Intel Baytrail processor E3825, while my design is using E3845. I am customizing coreboot for this E3845, but getting just garbage on coreboot, so not able to debug where it is stuck. When I add memory test as secondary payload, I cd see some operations happening on console but not able to decode it. Tried with all possible baud rates, but no success. USB and display also not enumerating. Can you please give some clue? Is it due to different core speed for E3835(1.33GHZ) vs E3845(1.91GHz). Where is the option to change this in coreboot? Appreciate your support. Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Help on setting clock speed in coreboot
Hi Team I have a customized board based on Intel valley island design. Reference design uses Intel Baytrail processor E3825, while my design is using E3845. I am customizing coreboot for this E3845, but getting just garbage on coreboot, so not able to debug where it is stuck. When I add memory test as secondary payload, I cd see some operations happening on console but not able to decode it. Tried with all possible baud rates, but no success. USB and display also not enumerating. Can you please give some clue? Is it due to different core speed for E3835(1.33GHZ) vs E3845(1.91GHz). Where is the option to change this in coreboot? Appreciate your support. Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Debug builds and memory testing
How u resolved memory issue? From: coreboot [mailto:coreboot-boun...@coreboot.org] On Behalf Of Naveed Ghori Sent: 31 May 2016 06:52 To: coreboot Subject: Re: [coreboot] Debug builds and memory testing To update this: There are option in the menuconfig to enable various debugging options and logs. From: Naveed Ghori Sent: Tuesday, 24 May 2016 2:04 PM To: coreboot Subject: Debug builds and memory testing Hi all, Is there a debug build of coreboot or a way to test memory very early on. My custom board goes through the romstage just fine but stops booting while trying to enumerate the buses. I am suspecting RAM might be an issue so would like to eliminate that by doing a memory test on it. -- POST: 0x72 Enumerating buses... Show all devs... Before device enumeration. Root Dev -- Thanks in advance, Naveed "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Query regarding coreboot for new intel customized board
Thanks Vim. Currently I am not able to get any serial prints out on my reference board. My board is based on Intel ISX board based on Baytrail-I soc E3825 given below. https://www-ssl.intel.com/content/www/us/en/embedded/design-tools/evaluation-platforms/atom-e3800-dev-kit-isx-ref-design-product-brief.html I have built coreboot for this, but unable to get serial prints. How I should debug this further. Regards Mayuri From: Wim Vervoorn [mailto:wvervo...@eltan.com] Sent: 24 May 2016 13:26 To: Mayuri Tendulkar Subject: Re: Query regarding coreboot for new intel customized board Hello Mayuri, If your rom image is the same it could be due to the lack of support for the flash device you are using. The MRC cache is preserved in flash so you need to be able to write it. For the others the numbers etc you mention are informational for the OS. They are not strictly required but the OS builds a registry of the items it retrieves from the SMBIOS. If you don't require this you could also disable the functionality. Best Regards, Wim Vervoorn Eltan B.V. Ambachtstraat 23 5481 SM Schijndel The Netherlands T : +31-(0)73-594 46 64 E : wvervo...@eltan.com<mailto:wvervo...@eltan.com> W : http://www.eltan.com "THIS MESSAGE CONTAINS CONFIDENTIAL INFORMATION. UNLESS YOU ARE THE INTENDED RECIPIENT OF THIS MESSAGE, ANY USE OF THIS MESSAGE IS STRICTLY PROHIBITED. IF YOU HAVE RECEIVED THIS MESSAGE IN ERROR, PLEASE IMMEDIATELY NOTIFY THE SENDER BY TELEPHONE +31-(0)73-5944664 OR REPLY EMAIL, AND IMMEDIATELY DELETE THIS MESSAGE AND ALL COPIES." From: coreboot [mailto:coreboot-boun...@coreboot.org] On Behalf Of Mayuri Tendulkar Sent: Tuesday, May 24, 2016 7:26 AM To: coreboot mailto:coreboot@coreboot.org>> Subject: [coreboot] Query regarding coreboot for new intel customized board Hi team I am working on building coreboot for one of our customized board. This is based on Intel ISX board reference design, reference can be taken as Minnowboard or BayleyBay CRB. As per documentation given under coreboot, I created folder with my board name under src/intel/mainboard/xxx and did changes required. If I tried the coreboot with these changes on minnowboard, it got stuck at FSP MRC Cache not found. But if the same code changes I copied under src/intel/mainboard/minnowmax and built, it booted fine. I would like to know what is the importance of these board names, SMBIOS table name, serial no which are defined for Minnowmax. Is there some master registry where all these are stored, and if any new entry comes, how we should add it. Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Query regarding coreboot for new intel customized board
Hi team I am working on building coreboot for one of our customized board. This is based on Intel ISX board reference design, reference can be taken as Minnowboard or BayleyBay CRB. As per documentation given under coreboot, I created folder with my board name under src/intel/mainboard/xxx and did changes required. If I tried the coreboot with these changes on minnowboard, it got stuck at FSP MRC Cache not found. But if the same code changes I copied under src/intel/mainboard/minnowmax and built, it booted fine. I would like to know what is the importance of these board names, SMBIOS table name, serial no which are defined for Minnowmax. Is there some master registry where all these are stored, and if any new entry comes, how we should add it. Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay
Hi Zoran I tried Minnowboard max bios file available on intel firmware site. With this file, I am able to boot to UEFI bios setup. But I don’t see any option to change CSM off. When I am booting thru coreboot, I don’t see any option to change this CSM mode. Regards Mayuri From: Zoran Stojsavljevic [mailto:zoran.stojsavlje...@gmail.com] Sent: 21 May 2016 12:47 To: Mayuri Tendulkar Cc: coreboot Subject: Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay Mayuri, > Zoran writes in last email: "...UEFI payload will not find EFI32 /boot/EFI > directory created..." My bad (right thinking, but too fast hands): should read FAT32 instead EFI32. > Sorry, but I am not able to understand what you have mentioned. Please, read carefully the following article: https://www.happyassassin.net/2014/01/25/uefi-boot-how-does-that-actually-work-then/ I have no time explaining the written. You need to spend maybe whole day analyzing it, trying to understand what Adam writes about. Bottom line, your Tiano Core works perfectly as payload, but you have CSM ON formatted HDD (must have CSM OFF). Zoran On Fri, May 20, 2016 at 10:41 AM, Mayuri Tendulkar mailto:mayuri.tendul...@aricent.com>> wrote: Hi Zoran Sorry, but I am not able to understand what you have mentioned. Can you please help me explain little detail? Sorry, but I am new to this coreboot environment. Regards Mayuri From: Zoran Stojsavljevic [mailto:zoran.stojsavlje...@gmail.com<mailto:zoran.stojsavlje...@gmail.com>] Sent: 20 May 2016 13:39 To: Mayuri Tendulkar mailto:mayuri.tendul...@aricent.com>> Cc: coreboot mailto:coreboot@coreboot.org>> Subject: Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay Hello Mayuri, Not sure if I am right, but to bring GRUB 2.0 from CSM OFF and CSM ON modes, you must have two distinct HDDs, one created with CSM ON, other with CSM OFF. If you are using one with CSM ON (seems the case), your UEFI payload will not find EFI32 /boot/EFI directory created, and it does not understand MBR). Does this (what I wrote) make sense? Zoran On Fri, May 20, 2016 at 7:21 AM, Mayuri Tendulkar mailto:mayuri.tendul...@aricent.com>> wrote: Hi Zoran Currently we are using FSP 3. But it works fine with seabios payload. Only when I include UEFI, I am getting this issue. So I am not sure if this is related to FSP3 or 4. My query is there any additional configurations required in UEFI Payload to make it work for Minnowboard max. I see difference in addresses for UEFI and Seabios payload. Not sure where are they set. Seabios payload (working) CBFS provider active. CBFS @ 50 size 2ff9c0 CBFS: Locating 'fallback/payload' CBFS: Found @ offset 76b40 size f782 'fallback/payload' located at offset: 576b78 size: f782 Loading segment from rom address 0xffd76b78 code (compression=1) New segment dstaddr 0xe2780 memsize 0x1d880 srcaddr 0xffd76bb0 filesize 0xf74a Loading segment from rom address 0xffd76b94 Entry Point 0x000ff06e Payload being loaded below 1MiB without region being marked as RAM usable. Bounce Buffer at 7ac5, 451744 bytes Loading Segment: addr: 0x000e2780 memsz: 0x0001d880 filesz: 0xf74a lb: [0x0010, 0x00137250) Post relocation: addr: 0x000e2780 memsz: 0x0001d880 filesz: 0xf74a using LZMA [ 0x000e2780, 0010, 0x0010) <- ffd76bb0 dest 000e2780, end 0010, bouncebuffer 7ac5 Loaded segments BS: BS_PAYLOAD_LOAD times (us): entry 0 run 130526 exit 0 FspNotify(EnumInitPhaseReadyToBoot) fsp_header_ptr: fffc0094 FSP Header Version: 1 FSP Revision: 3.3 Returned from FspNotify(EnumInitPhaseReadyToBoot) POST: 0x7b Jumping to boot code at 000ff06e(7acbf000) POST: 0xf8 CPU0: stack: 0012e000 - 0012f000, lowest used address 0012eb10, stack used: 1264 bytes entry= 0x000ff06e lb_start = 0x0010 lb_size = 0x00037250 buffer = 0x7ac5 SeaBIOS (version rel-1.9.0-127-gc8e105a) UEFI Payload logs (not working) CBFS provider active. CBFS @ 50 size 2ff9c0 CBFS: Locating 'fallback/payload' CBFS: Found @ offset 56ec0 size 90b92 'fallback/payload' located at offset: 556ef8 size: 90b92 Loading segment from rom address 0xffd56ef8 code (compression=1) New segment dstaddr 0x80 memsize 0x41 srcaddr 0xffd56f30 filesize 0x90b5a Loading segment from rom address 0xffd56f14 Entry Point 0x008002c0 Bounce Buffer at 7ac34000, 437408 bytes Loading Segment: addr: 0x0080 memsz: 0x0041 filesz: 0x00090b5a lb: [0x0010, 0x00135650) Post relocation: addr: 0x0080 memsz: 0x0041 filesz: 0x00090b5a using LZMA [ 0x0080, 00c1, 0x00c1) <- ffd56f30 dest 0080, end 00c1, bouncebuffer 7ac34000 Loaded segments BS: BS_PAYLOAD_LOAD times (us): entry 0 run 507070 exit 0 FspNotify(EnumInitP
Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay
Hi Zoran Sorry, but I am not able to understand what you have mentioned. Can you please help me explain little detail? Sorry, but I am new to this coreboot environment. Regards Mayuri From: Zoran Stojsavljevic [mailto:zoran.stojsavlje...@gmail.com] Sent: 20 May 2016 13:39 To: Mayuri Tendulkar Cc: coreboot Subject: Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay Hello Mayuri, Not sure if I am right, but to bring GRUB 2.0 from CSM OFF and CSM ON modes, you must have two distinct HDDs, one created with CSM ON, other with CSM OFF. If you are using one with CSM ON (seems the case), your UEFI payload will not find EFI32 /boot/EFI directory created, and it does not understand MBR). Does this (what I wrote) make sense? Zoran On Fri, May 20, 2016 at 7:21 AM, Mayuri Tendulkar mailto:mayuri.tendul...@aricent.com>> wrote: Hi Zoran Currently we are using FSP 3. But it works fine with seabios payload. Only when I include UEFI, I am getting this issue. So I am not sure if this is related to FSP3 or 4. My query is there any additional configurations required in UEFI Payload to make it work for Minnowboard max. I see difference in addresses for UEFI and Seabios payload. Not sure where are they set. Seabios payload (working) CBFS provider active. CBFS @ 50 size 2ff9c0 CBFS: Locating 'fallback/payload' CBFS: Found @ offset 76b40 size f782 'fallback/payload' located at offset: 576b78 size: f782 Loading segment from rom address 0xffd76b78 code (compression=1) New segment dstaddr 0xe2780 memsize 0x1d880 srcaddr 0xffd76bb0 filesize 0xf74a Loading segment from rom address 0xffd76b94 Entry Point 0x000ff06e Payload being loaded below 1MiB without region being marked as RAM usable. Bounce Buffer at 7ac5, 451744 bytes Loading Segment: addr: 0x000e2780 memsz: 0x0001d880 filesz: 0xf74a lb: [0x0010, 0x00137250) Post relocation: addr: 0x000e2780 memsz: 0x0001d880 filesz: 0xf74a using LZMA [ 0x000e2780, 0010, 0x0010) <- ffd76bb0 dest 000e2780, end 0010, bouncebuffer 7ac5 Loaded segments BS: BS_PAYLOAD_LOAD times (us): entry 0 run 130526 exit 0 FspNotify(EnumInitPhaseReadyToBoot) fsp_header_ptr: fffc0094 FSP Header Version: 1 FSP Revision: 3.3 Returned from FspNotify(EnumInitPhaseReadyToBoot) POST: 0x7b Jumping to boot code at 000ff06e(7acbf000) POST: 0xf8 CPU0: stack: 0012e000 - 0012f000, lowest used address 0012eb10, stack used: 1264 bytes entry= 0x000ff06e lb_start = 0x0010 lb_size = 0x00037250 buffer = 0x7ac5 SeaBIOS (version rel-1.9.0-127-gc8e105a) UEFI Payload logs (not working) CBFS provider active. CBFS @ 50 size 2ff9c0 CBFS: Locating 'fallback/payload' CBFS: Found @ offset 56ec0 size 90b92 'fallback/payload' located at offset: 556ef8 size: 90b92 Loading segment from rom address 0xffd56ef8 code (compression=1) New segment dstaddr 0x80 memsize 0x41 srcaddr 0xffd56f30 filesize 0x90b5a Loading segment from rom address 0xffd56f14 Entry Point 0x008002c0 Bounce Buffer at 7ac34000, 437408 bytes Loading Segment: addr: 0x0080 memsz: 0x0041 filesz: 0x00090b5a lb: [0x0010, 0x00135650) Post relocation: addr: 0x0080 memsz: 0x0041 filesz: 0x00090b5a using LZMA [ 0x0080, 00c1, 0x00c1) <- ffd56f30 dest 0080, end 00c1, bouncebuffer 7ac34000 Loaded segments BS: BS_PAYLOAD_LOAD times (us): entry 0 run 507070 exit 0 FspNotify(EnumInitPhaseReadyToBoot) fsp_header_ptr: fffc0094 FSP Header Version: 1 FSP Revision: 3.3 Returned from FspNotify(EnumInitPhaseReadyToBoot) POST: 0x7b Jumping to boot code at 008002c0(7ac9f000) POST: 0xf8 CPU0: stack: 0012c000 - 0012d000, lowest used address 0012cb10, stack used: 1264 bytes entry= 0x008002c0 lb_start = 0x0010 lb_size = 0x00035650 buffer = 0x7ac34000 From: Zoran Stojsavljevic [mailto:zoran.stojsavlje...@gmail.com<mailto:zoran.stojsavlje...@gmail.com>] Sent: 20 May 2016 10:44 To: Mayuri Tendulkar mailto:mayuri.tendul...@aricent.com>>; coreboot mailto:coreboot@coreboot.org>> Subject: Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay Hello Mayuri, If I am not mistaken (I often mix BYT Coreboot @ threads in my head), you are using BYT FSP Version 3. > fsp_header_ptr: fffc0094 <== correct > FSP Header Version: 1 > FSP Revision: 3.3 <== please, use Version 4 Please, try to use the latest public BYT FSP Version 4 posted at: www.intel.com/fsp<http://www.intel.com/fsp> BAYTRAIL_FSP_GOLD_004_22-MAY-2015.fd BAYTRAIL_FSP_GOLD_004_22-MAY-2015_DEBUG.fd Don't remember deltas between V3 and V4, I thing something was wrong in V3 with MTRRs' setup, if I do not mix data in my head. INTEL also has Version 5 for a quite some time, but this one for some reasons never got pub
Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay
Hi Zoran Currently we are using FSP 3. But it works fine with seabios payload. Only when I include UEFI, I am getting this issue. So I am not sure if this is related to FSP3 or 4. My query is there any additional configurations required in UEFI Payload to make it work for Minnowboard max. I see difference in addresses for UEFI and Seabios payload. Not sure where are they set. Seabios payload (working) CBFS provider active. CBFS @ 50 size 2ff9c0 CBFS: Locating 'fallback/payload' CBFS: Found @ offset 76b40 size f782 'fallback/payload' located at offset: 576b78 size: f782 Loading segment from rom address 0xffd76b78 code (compression=1) New segment dstaddr 0xe2780 memsize 0x1d880 srcaddr 0xffd76bb0 filesize 0xf74a Loading segment from rom address 0xffd76b94 Entry Point 0x000ff06e Payload being loaded below 1MiB without region being marked as RAM usable. Bounce Buffer at 7ac5, 451744 bytes Loading Segment: addr: 0x000e2780 memsz: 0x0001d880 filesz: 0xf74a lb: [0x0010, 0x00137250) Post relocation: addr: 0x000e2780 memsz: 0x0001d880 filesz: 0xf74a using LZMA [ 0x000e2780, 0010, 0x0010) <- ffd76bb0 dest 000e2780, end 0010, bouncebuffer 7ac5 Loaded segments BS: BS_PAYLOAD_LOAD times (us): entry 0 run 130526 exit 0 FspNotify(EnumInitPhaseReadyToBoot) fsp_header_ptr: fffc0094 FSP Header Version: 1 FSP Revision: 3.3 Returned from FspNotify(EnumInitPhaseReadyToBoot) POST: 0x7b Jumping to boot code at 000ff06e(7acbf000) POST: 0xf8 CPU0: stack: 0012e000 - 0012f000, lowest used address 0012eb10, stack used: 1264 bytes entry= 0x000ff06e lb_start = 0x0010 lb_size = 0x00037250 buffer = 0x7ac5 SeaBIOS (version rel-1.9.0-127-gc8e105a) UEFI Payload logs (not working) CBFS provider active. CBFS @ 50 size 2ff9c0 CBFS: Locating 'fallback/payload' CBFS: Found @ offset 56ec0 size 90b92 'fallback/payload' located at offset: 556ef8 size: 90b92 Loading segment from rom address 0xffd56ef8 code (compression=1) New segment dstaddr 0x80 memsize 0x41 srcaddr 0xffd56f30 filesize 0x90b5a Loading segment from rom address 0xffd56f14 Entry Point 0x008002c0 Bounce Buffer at 7ac34000, 437408 bytes Loading Segment: addr: 0x0080 memsz: 0x0041 filesz: 0x00090b5a lb: [0x0010, 0x00135650) Post relocation: addr: 0x0080 memsz: 0x0041 filesz: 0x00090b5a using LZMA [ 0x0080, 00c1, 0x00c1) <- ffd56f30 dest 0080, end 00c1, bouncebuffer 7ac34000 Loaded segments BS: BS_PAYLOAD_LOAD times (us): entry 0 run 507070 exit 0 FspNotify(EnumInitPhaseReadyToBoot) fsp_header_ptr: fffc0094 FSP Header Version: 1 FSP Revision: 3.3 Returned from FspNotify(EnumInitPhaseReadyToBoot) POST: 0x7b Jumping to boot code at 008002c0(7ac9f000) POST: 0xf8 CPU0: stack: 0012c000 - 0012d000, lowest used address 0012cb10, stack used: 1264 bytes entry= 0x008002c0 lb_start = 0x0010 lb_size = 0x00035650 buffer = 0x7ac34000 From: Zoran Stojsavljevic [mailto:zoran.stojsavlje...@gmail.com] Sent: 20 May 2016 10:44 To: Mayuri Tendulkar ; coreboot Subject: Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay Hello Mayuri, If I am not mistaken (I often mix BYT Coreboot @ threads in my head), you are using BYT FSP Version 3. > fsp_header_ptr: fffc0094 <== correct > FSP Header Version: 1 > FSP Revision: 3.3 <== please, use Version 4 Please, try to use the latest public BYT FSP Version 4 posted at: www.intel.com/fsp<http://www.intel.com/fsp> BAYTRAIL_FSP_GOLD_004_22-MAY-2015.fd BAYTRAIL_FSP_GOLD_004_22-MAY-2015_DEBUG.fd Don't remember deltas between V3 and V4, I thing something was wrong in V3 with MTRRs' setup, if I do not mix data in my head. INTEL also has Version 5 for a quite some time, but this one for some reasons never got publicly released. Please, report if this solved your problems. Zoran On Wed, May 18, 2016 at 6:56 AM, Mayuri Tendulkar mailto:mayuri.tendul...@aricent.com>> wrote: Hi While booting my Minnomboard with coreboot and UEFI, it hangs at below point while loading the payload. I followed the procedure to download latest EDK2 tree and built UEFIPAYLOAD.fd and copied it to coreboot/payloads/external/tianocore folder and gave this path in make menuconfig. Has anybody come across this? BS: BS_PAYLOAD_LOAD times (us): entry 0 run 507070 exit 0 FspNotify(EnumInitPhaseReadyToBoot) fsp_header_ptr: fffc0094 FSP Header Version: 1 FSP Revision: 3.3 Returned from FspNotify(EnumInitPhaseReadyToBoot) POST: 0x7b Jumping to boot code at 008002c0(7ac9f000) POST: 0xf8 CPU0: stack: 0012c000 - 0012d000, lowest used address 0012cb10, stack used: 1264 bytes entry= 0x008002c0 lb_start = 0x0010 lb_size = 0x00035650 buffer = 0x7ac34000 Regards Mayuri From: Mayuri Tendulkar Sent: 17 May 2016
Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay
Can anybody help here? Do we have UEFI payload changes for Minnowmax available? From: Mayuri Tendulkar Sent: 18 May 2016 10:27 To: 'Zoran Stojsavljevic' ; 'coreboot@coreboot.org' Subject: RE: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay Hi While booting my Minnomboard with coreboot and UEFI, it hangs at below point while loading the payload. I followed the procedure to download latest EDK2 tree and built UEFIPAYLOAD.fd and copied it to coreboot/payloads/external/tianocore folder and gave this path in make menuconfig. Has anybody come across this? BS: BS_PAYLOAD_LOAD times (us): entry 0 run 507070 exit 0 FspNotify(EnumInitPhaseReadyToBoot) fsp_header_ptr: fffc0094 FSP Header Version: 1 FSP Revision: 3.3 Returned from FspNotify(EnumInitPhaseReadyToBoot) POST: 0x7b Jumping to boot code at 008002c0(7ac9f000) POST: 0xf8 CPU0: stack: 0012c000 - 0012d000, lowest used address 0012cb10, stack used: 1264 bytes entry= 0x008002c0 lb_start = 0x0010 lb_size = 0x00035650 buffer = 0x7ac34000 Regards Mayuri From: Mayuri Tendulkar Sent: 17 May 2016 14:13 To: 'Zoran Stojsavljevic' mailto:zoran.stojsavlje...@gmail.com>>; coreboot@coreboot.org<mailto:coreboot@coreboot.org> Subject: RE: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay Hi Zoran and Martin Today I was able to build UEFIPAYLOAD separately. I included .fd file while building coreboot.rom. But while booting, getting some errors , so debugging those. Need to check what more customizations to be done in UEFI for Minnowmax. Has anybody tried it? Regards Mayuri From: Zoran Stojsavljevic [mailto:zoran.stojsavlje...@gmail.com] Sent: 16 May 2016 21:04 To: Mayuri Tendulkar mailto:mayuri.tendul...@aricent.com>>; coreboot@coreboot.org<mailto:coreboot@coreboot.org> Subject: Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay OK, Mayuri, You brought an interesting point. And this point is to be not only investigated by you, rather also by me and, perhaps, Coreboot community. Since here, in Bayern/Deutschland is Holiday Day, I went to buy a beer in Munchen HBf, and while walking there I was thinking about your use case. Thinking deeper. I know that you are using some INTEL CPU/SoC (do not remember which one, if you said one). But, while recapping how BIOS looks like, I did notice that SEC and PEI phases have nothing to do with UEFI EDK2. EDK 2 comes to play in DXE phase, where EDK2 actually takes place/overtakes control... It says to me one major thing I did not notice while ago: that ARM SoCs are also eligible to run on UEFI compliant OSes, namely WIN 8.1+ (including WIN 10 and WIN 10 Athens/RT WIN 10). Which makes very interesting IOT case namely for ARM, allowing it also to compete in WIN space. Interestingly enough, this idea did not come to my mind till few hours ago... I guess, Vincent (Zimmer) already thought about that. ;-) ___ Martin (Roth) just replied, to solve this immediate mystery. probably for the beginning only for INTEL SoCs, but, I really hope, ARM will also integrate in this concept seamlessly! :-) Zoran ___ On Mon, May 16, 2016 at 2:29 PM, Mayuri Tendulkar mailto:mayuri.tendul...@aricent.com>> wrote: Hi Zoran I have checked that site and downloaded EDK2 code. I am trying to build it on Linux but facing some issues. But if I generate payload file separately, I need to integrate it in coreboot separately. So I am checking if there is way to build the payload in coreboot itself. Regards Mayuri From: Zoran Stojsavljevic [mailto:zoran.stojsavlje...@gmail.com<mailto:zoran.stojsavlje...@gmail.com>] Sent: 16 May 2016 17:57 To: Mayuri Tendulkar mailto:mayuri.tendul...@aricent.com>> Cc: coreboot@coreboot.org<mailto:coreboot@coreboot.org> Subject: Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay Hello Mayuri, You should check payload called: Tiano Core (true UEFI payload). Zoran On Mon, May 16, 2016 at 2:12 PM, Mayuri Tendulkar mailto:mayuri.tendul...@aricent.com>> wrote: Hi Is there any mechanism to build UEFI payload directly in coreboot similar like seabios? Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- coreboot mailing list: coreboot@coreboot.org
Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay
Hi While booting my Minnomboard with coreboot and UEFI, it hangs at below point while loading the payload. I followed the procedure to download latest EDK2 tree and built UEFIPAYLOAD.fd and copied it to coreboot/payloads/external/tianocore folder and gave this path in make menuconfig. Has anybody come across this? BS: BS_PAYLOAD_LOAD times (us): entry 0 run 507070 exit 0 FspNotify(EnumInitPhaseReadyToBoot) fsp_header_ptr: fffc0094 FSP Header Version: 1 FSP Revision: 3.3 Returned from FspNotify(EnumInitPhaseReadyToBoot) POST: 0x7b Jumping to boot code at 008002c0(7ac9f000) POST: 0xf8 CPU0: stack: 0012c000 - 0012d000, lowest used address 0012cb10, stack used: 1264 bytes entry= 0x008002c0 lb_start = 0x0010 lb_size = 0x00035650 buffer = 0x7ac34000 Regards Mayuri From: Mayuri Tendulkar Sent: 17 May 2016 14:13 To: 'Zoran Stojsavljevic' ; coreboot@coreboot.org Subject: RE: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay Hi Zoran and Martin Today I was able to build UEFIPAYLOAD separately. I included .fd file while building coreboot.rom. But while booting, getting some errors , so debugging those. Need to check what more customizations to be done in UEFI for Minnowmax. Has anybody tried it? Regards Mayuri From: Zoran Stojsavljevic [mailto:zoran.stojsavlje...@gmail.com] Sent: 16 May 2016 21:04 To: Mayuri Tendulkar mailto:mayuri.tendul...@aricent.com>>; coreboot@coreboot.org<mailto:coreboot@coreboot.org> Subject: Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay OK, Mayuri, You brought an interesting point. And this point is to be not only investigated by you, rather also by me and, perhaps, Coreboot community. Since here, in Bayern/Deutschland is Holiday Day, I went to buy a beer in Munchen HBf, and while walking there I was thinking about your use case. Thinking deeper. I know that you are using some INTEL CPU/SoC (do not remember which one, if you said one). But, while recapping how BIOS looks like, I did notice that SEC and PEI phases have nothing to do with UEFI EDK2. EDK 2 comes to play in DXE phase, where EDK2 actually takes place/overtakes control... It says to me one major thing I did not notice while ago: that ARM SoCs are also eligible to run on UEFI compliant OSes, namely WIN 8.1+ (including WIN 10 and WIN 10 Athens/RT WIN 10). Which makes very interesting IOT case namely for ARM, allowing it also to compete in WIN space. Interestingly enough, this idea did not come to my mind till few hours ago... I guess, Vincent (Zimmer) already thought about that. ;-) ___ Martin (Roth) just replied, to solve this immediate mystery. probably for the beginning only for INTEL SoCs, but, I really hope, ARM will also integrate in this concept seamlessly! :-) Zoran ___ On Mon, May 16, 2016 at 2:29 PM, Mayuri Tendulkar mailto:mayuri.tendul...@aricent.com>> wrote: Hi Zoran I have checked that site and downloaded EDK2 code. I am trying to build it on Linux but facing some issues. But if I generate payload file separately, I need to integrate it in coreboot separately. So I am checking if there is way to build the payload in coreboot itself. Regards Mayuri From: Zoran Stojsavljevic [mailto:zoran.stojsavlje...@gmail.com<mailto:zoran.stojsavlje...@gmail.com>] Sent: 16 May 2016 17:57 To: Mayuri Tendulkar mailto:mayuri.tendul...@aricent.com>> Cc: coreboot@coreboot.org<mailto:coreboot@coreboot.org> Subject: Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay Hello Mayuri, You should check payload called: Tiano Core (true UEFI payload). Zoran On Mon, May 16, 2016 at 2:12 PM, Mayuri Tendulkar mailto:mayuri.tendul...@aricent.com>> wrote: Hi Is there any mechanism to build UEFI payload directly in coreboot similar like seabios? Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- coreboot mailing list: coreboot@coreboot.org<mailto:coreboot@coreboot.org> https://www.coreboot.org/mailman/listinfo/coreboot "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended.
Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay
Hi Zoran and Martin Today I was able to build UEFIPAYLOAD separately. I included .fd file while building coreboot.rom. But while booting, getting some errors , so debugging those. Need to check what more customizations to be done in UEFI for Minnowmax. Has anybody tried it? Regards Mayuri From: Zoran Stojsavljevic [mailto:zoran.stojsavlje...@gmail.com] Sent: 16 May 2016 21:04 To: Mayuri Tendulkar ; coreboot@coreboot.org Subject: Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay OK, Mayuri, You brought an interesting point. And this point is to be not only investigated by you, rather also by me and, perhaps, Coreboot community. Since here, in Bayern/Deutschland is Holiday Day, I went to buy a beer in Munchen HBf, and while walking there I was thinking about your use case. Thinking deeper. I know that you are using some INTEL CPU/SoC (do not remember which one, if you said one). But, while recapping how BIOS looks like, I did notice that SEC and PEI phases have nothing to do with UEFI EDK2. EDK 2 comes to play in DXE phase, where EDK2 actually takes place/overtakes control... It says to me one major thing I did not notice while ago: that ARM SoCs are also eligible to run on UEFI compliant OSes, namely WIN 8.1+ (including WIN 10 and WIN 10 Athens/RT WIN 10). Which makes very interesting IOT case namely for ARM, allowing it also to compete in WIN space. Interestingly enough, this idea did not come to my mind till few hours ago... I guess, Vincent (Zimmer) already thought about that. ;-) ___ Martin (Roth) just replied, to solve this immediate mystery. probably for the beginning only for INTEL SoCs, but, I really hope, ARM will also integrate in this concept seamlessly! :-) Zoran ___ On Mon, May 16, 2016 at 2:29 PM, Mayuri Tendulkar mailto:mayuri.tendul...@aricent.com>> wrote: Hi Zoran I have checked that site and downloaded EDK2 code. I am trying to build it on Linux but facing some issues. But if I generate payload file separately, I need to integrate it in coreboot separately. So I am checking if there is way to build the payload in coreboot itself. Regards Mayuri From: Zoran Stojsavljevic [mailto:zoran.stojsavlje...@gmail.com<mailto:zoran.stojsavlje...@gmail.com>] Sent: 16 May 2016 17:57 To: Mayuri Tendulkar mailto:mayuri.tendul...@aricent.com>> Cc: coreboot@coreboot.org<mailto:coreboot@coreboot.org> Subject: Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay Hello Mayuri, You should check payload called: Tiano Core (true UEFI payload). Zoran On Mon, May 16, 2016 at 2:12 PM, Mayuri Tendulkar mailto:mayuri.tendul...@aricent.com>> wrote: Hi Is there any mechanism to build UEFI payload directly in coreboot similar like seabios? Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- coreboot mailing list: coreboot@coreboot.org<mailto:coreboot@coreboot.org> https://www.coreboot.org/mailman/listinfo/coreboot "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this
Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay
Hi Martin Yes, I have looked at below links and working on it , but facing some issues both in windows and Linux. Anyway hopefully will sort on those issues soon. Keep me posted once u integrate payload in coreboot. Regards Mayuri -Original Message- From: Martin Roth [mailto:gauml...@gmail.com] Sent: 16 May 2016 20:43 To: Mayuri Tendulkar Cc: Zoran Stojsavljevic ; coreboot@coreboot.org Subject: Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay Hi Mayuri, As of right now, the coreboot build doesn't have a way to build tianocore/CorebootPayloadPkg into coreboot automatically, but I'm working on integrating it. I had hoped to have my initial push ready last week, but didn't get it finished. That said, it's not difficult to build it outside of coreboot, then add it as an elf payload. In case you haven't found these pages with the instructions, here they are: https://github.com/tianocore/tianocore.github.io/wiki/Using-EDK-II-with-Native-GCC https://svn.code.sf.net/p/edk2/code/trunk/edk2/CorebootPayloadPkg/BuildAndIntegrationInstructions.txt Last time I tested, I had some issues with the debug version of the rom hitting an assert and dying, but the release build booted successfully. Martin On Mon, May 16, 2016 at 6:29 AM, Mayuri Tendulkar wrote: > Hi Zoran > > > > I have checked that site and downloaded EDK2 code. I am trying to > build it on Linux but facing some issues. > > But if I generate payload file separately, I need to integrate it in > coreboot separately. > > > > So I am checking if there is way to build the payload in coreboot itself. > > > > Regards > > Mayuri > > > > From: Zoran Stojsavljevic [mailto:zoran.stojsavlje...@gmail.com] > Sent: 16 May 2016 17:57 > To: Mayuri Tendulkar > Cc: coreboot@coreboot.org > Subject: Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard > or Bayley bay > > > > Hello Mayuri, > > > > You should check payload called: Tiano Core (true UEFI payload). > > > > Zoran > > > > > > On Mon, May 16, 2016 at 2:12 PM, Mayuri Tendulkar > wrote: > > Hi > > > > Is there any mechanism to build UEFI payload directly in coreboot > similar like seabios? > > > > Regards > > Mayuri > > "DISCLAIMER: This message is proprietary to Aricent and is intended > solely for the use of the individual to whom it is addressed. It may > contain privileged or confidential information and should not be > circulated or used for any purpose other than for what it is intended. > If you have received this message in error, please notify the > originator immediately. If you are not the intended recipient, you are > notified that you are strictly prohibited from using, copying, > altering, or disclosing the contents of this message. Aricent accepts > no responsibility for loss or damage arising from the use of the > information transmitted by this email including damage from virus." > > > -- > coreboot mailing list: coreboot@coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot > > > > "DISCLAIMER: This message is proprietary to Aricent and is intended > solely for the use of the individual to whom it is addressed. It may > contain privileged or confidential information and should not be > circulated or used for any purpose other than for what it is intended. > If you have received this message in error, please notify the > originator immediately. If you are not the intended recipient, you are > notified that you are strictly prohibited from using, copying, > altering, or disclosing the contents of this message. Aricent accepts > no responsibility for loss or damage arising from the use of the > information transmitted by this email including damage from virus." > > -- > coreboot mailing list: coreboot@coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay
Hi Zoran I have checked that site and downloaded EDK2 code. I am trying to build it on Linux but facing some issues. But if I generate payload file separately, I need to integrate it in coreboot separately. So I am checking if there is way to build the payload in coreboot itself. Regards Mayuri From: Zoran Stojsavljevic [mailto:zoran.stojsavlje...@gmail.com] Sent: 16 May 2016 17:57 To: Mayuri Tendulkar Cc: coreboot@coreboot.org Subject: Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay Hello Mayuri, You should check payload called: Tiano Core (true UEFI payload). Zoran On Mon, May 16, 2016 at 2:12 PM, Mayuri Tendulkar mailto:mayuri.tendul...@aricent.com>> wrote: Hi Is there any mechanism to build UEFI payload directly in coreboot similar like seabios? Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- coreboot mailing list: coreboot@coreboot.org<mailto:coreboot@coreboot.org> https://www.coreboot.org/mailman/listinfo/coreboot "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay
Hi Is there any mechanism to build UEFI payload directly in coreboot similar like seabios? Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Coreboot image and seabios payload with debug symbols
Hi Zoran I am having Intel system studio trial version and also XDP3 connector. Regards Mayuri From: Zoran Stojsavljevic [mailto:zoran.stojsavlje...@gmail.com] Sent: 12 May 2016 17:31 To: Mayuri Tendulkar ; coreboot@coreboot.org Subject: Re: [coreboot] Coreboot image and seabios payload with debug symbols Hello Mayuri, [3] The other way how to use ITP BlueBox XDP3 is to use ISS (INTEL System Studio). I guess, there is 30 day free trial for ISS (on the intel.com<http://intel.com> public web, there is an ISS download somewhere), but if you would like to have ISS activated, you need to contact ISS INTEL support. Hope this helps, Zoran On Thu, May 12, 2016 at 9:38 AM, Mayuri Tendulkar mailto:mayuri.tendul...@aricent.com>> wrote: Thanks. I will check that. But I didn’t get 3rd point completely. From: Zoran Stojsavljevic [mailto:zoran.stojsavlje...@gmail.com<mailto:zoran.stojsavlje...@gmail.com>] Sent: 12 May 2016 12:18 To: Mayuri Tendulkar mailto:mayuri.tendul...@aricent.com>>; coreboot@coreboot.org<mailto:coreboot@coreboot.org> Subject: Re: [coreboot] Coreboot image and seabios payload with debug symbols Hello Mayuri, Sorry, I am busy with some other things (trying to perfect my Deutsch Sprache, and this goes too slow, and too pejorative)... :-( I did not look thru the second document, but here is what I'll advise here: [1] Go to https://gcc.gnu.org/onlinedocs/gcc-4.8.0/gcc/Debugging-Options.html and find how to compile Coreboot with debug and maximum warnings. Not sure, -D is for debug, -O for the warnings. [2] From www.intel.com/fsp<http://www.intel.com/fsp>, use the following Debug FSP, included in the package from: Intel® Atom™ processor E3800 product family (formerly Bay Trail, Compliant with FSP v1.0 Specification) [3] You do need to use DAL/PDT ITP2 package for your XDP3 (60 pin connector), since for BYT family only ITP2 SW is available (legacy ITP disconnected). Later... Zoran On Thu, May 12, 2016 at 7:44 AM, Mayuri Tendulkar mailto:mayuri.tendul...@aricent.com>> wrote: Hi Zoran Can you please update on this? Can we build using debug FSP and gdb enabling? Regards Mayuri From: Mayuri Tendulkar Sent: 11 May 2016 10:02 To: 'Zoran Stojsavljevic' mailto:zoran.stojsavlje...@gmail.com>> Cc: coreboot@coreboot.org<mailto:coreboot@coreboot.org> Subject: RE: [coreboot] Coreboot image and seabios payload with debug symbols Hi Zoran Please find responses: [1] When you do refer to "Intel system debugger", do you refer to INTEL ITP2 debugger, with Blue Box XDP 60 pin HW connector (http://m.eet.com/media/1073715/JTAG_101_fig5.jpg)? This is Intel® ITP-XDP3. https://software.intel.com/sites/default/files/managed/45/19/10-jtag-debugger.pdf [2] For which CPU/SoC/platform you would like to use [1]? – This I am currently using for Minnowboard Turbot (E3826 dual core) [3] Seems that you did copy some debug excerpt from some INTEL document... I guess, this one is public one. Could you, please, attach this (if?) public document to this @ thread for our review, or either pass to us www pointer to this document? This can be found from Intel system debugger use guide. https://software.intel.com/en-us/node/592929- check section debugging basics Regards Mayuri From: Zoran Stojsavljevic [mailto:zoran.stojsavlje...@gmail.com] Sent: 10 May 2016 23:15 To: Mayuri Tendulkar mailto:mayuri.tendul...@aricent.com>> Cc: coreboot@coreboot.org<mailto:coreboot@coreboot.org> Subject: Re: [coreboot] Coreboot image and seabios payload with debug symbols Hello Mayuri, Few questions, may I? [1] When you do refer to "Intel system debugger", do you refer to INTEL ITP2 debugger, with Blue Box XDP 60 pin HW connector (http://m.eet.com/media/1073715/JTAG_101_fig5.jpg)? [2] For which CPU/SoC/platform you would like to use [1]? [3] Seems that you did copy some debug excerpt from some INTEL document... I guess, this one is public one. Could you, please, attach this (if?) public document to this @ thread for our review, or either pass to us www pointer to this document? Thank you, Zoran [https://ssl.gstatic.com/ui/v1/icons/mail/images/cleardot.gif] On Tue, May 10, 2016 at 8:22 AM, Mayuri Tendulkar mailto:mayuri.tendul...@aricent.com>> wrote: Hi I want to use Intel system debugger to do coreboot source level debugging. So I need below. Can you please help me in this? To debug your software using source code you need to load debug information that is used to map the program in target memory to the original source files. To do this the debugger needs the following: * A program loaded in target memory that has been compiled with debug information * The load address of the program in target memory * The program binary file (executable file) * Debug information file for the program binary (also referred to as "symbols") * Original program source code Reg
Re: [coreboot] Coreboot image and seabios payload with debug symbols
Hi Zoran Can you please update on this? Can we build using debug FSP and gdb enabling? Regards Mayuri From: Mayuri Tendulkar Sent: 11 May 2016 10:02 To: 'Zoran Stojsavljevic' Cc: coreboot@coreboot.org Subject: RE: [coreboot] Coreboot image and seabios payload with debug symbols Hi Zoran Please find responses: [1] When you do refer to "Intel system debugger", do you refer to INTEL ITP2 debugger, with Blue Box XDP 60 pin HW connector (http://m.eet.com/media/1073715/JTAG_101_fig5.jpg)? This is Intel® ITP-XDP3. https://software.intel.com/sites/default/files/managed/45/19/10-jtag-debugger.pdf [2] For which CPU/SoC/platform you would like to use [1]? – This I am currently using for Minnowboard Turbot (E3826 dual core) [3] Seems that you did copy some debug excerpt from some INTEL document... I guess, this one is public one. Could you, please, attach this (if?) public document to this @ thread for our review, or either pass to us www pointer to this document? This can be found from Intel system debugger use guide. https://software.intel.com/en-us/node/592929- check section debugging basics Regards Mayuri From: Zoran Stojsavljevic [mailto:zoran.stojsavlje...@gmail.com] Sent: 10 May 2016 23:15 To: Mayuri Tendulkar mailto:mayuri.tendul...@aricent.com>> Cc: coreboot@coreboot.org<mailto:coreboot@coreboot.org> Subject: Re: [coreboot] Coreboot image and seabios payload with debug symbols Hello Mayuri, Few questions, may I? [1] When you do refer to "Intel system debugger", do you refer to INTEL ITP2 debugger, with Blue Box XDP 60 pin HW connector (http://m.eet.com/media/1073715/JTAG_101_fig5.jpg)? [2] For which CPU/SoC/platform you would like to use [1]? [3] Seems that you did copy some debug excerpt from some INTEL document... I guess, this one is public one. Could you, please, attach this (if?) public document to this @ thread for our review, or either pass to us www pointer to this document? Thank you, Zoran [https://ssl.gstatic.com/ui/v1/icons/mail/images/cleardot.gif] On Tue, May 10, 2016 at 8:22 AM, Mayuri Tendulkar mailto:mayuri.tendul...@aricent.com>> wrote: Hi I want to use Intel system debugger to do coreboot source level debugging. So I need below. Can you please help me in this? To debug your software using source code you need to load debug information that is used to map the program in target memory to the original source files. To do this the debugger needs the following: * A program loaded in target memory that has been compiled with debug information * The load address of the program in target memory * The program binary file (executable file) * Debug information file for the program binary (also referred to as "symbols") * Original program source code Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- coreboot mailing list: coreboot@coreboot.org<mailto:coreboot@coreboot.org> https://www.coreboot.org/mailman/listinfo/coreboot "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Coreboot image and seabios payload with debug symbols
Hi Zoran Please find responses: [1] When you do refer to "Intel system debugger", do you refer to INTEL ITP2 debugger, with Blue Box XDP 60 pin HW connector (http://m.eet.com/media/1073715/JTAG_101_fig5.jpg)? This is Intel® ITP-XDP3. https://software.intel.com/sites/default/files/managed/45/19/10-jtag-debugger.pdf [2] For which CPU/SoC/platform you would like to use [1]? – This I am currently using for Minnowboard Turbot (E3826 dual core) [3] Seems that you did copy some debug excerpt from some INTEL document... I guess, this one is public one. Could you, please, attach this (if?) public document to this @ thread for our review, or either pass to us www pointer to this document? This can be found from Intel system debugger use guide. https://software.intel.com/en-us/node/592929- check section debugging basics Regards Mayuri From: Zoran Stojsavljevic [mailto:zoran.stojsavlje...@gmail.com] Sent: 10 May 2016 23:15 To: Mayuri Tendulkar Cc: coreboot@coreboot.org Subject: Re: [coreboot] Coreboot image and seabios payload with debug symbols Hello Mayuri, Few questions, may I? [1] When you do refer to "Intel system debugger", do you refer to INTEL ITP2 debugger, with Blue Box XDP 60 pin HW connector (http://m.eet.com/media/1073715/JTAG_101_fig5.jpg)? [2] For which CPU/SoC/platform you would like to use [1]? [3] Seems that you did copy some debug excerpt from some INTEL document... I guess, this one is public one. Could you, please, attach this (if?) public document to this @ thread for our review, or either pass to us www pointer to this document? Thank you, Zoran [https://ssl.gstatic.com/ui/v1/icons/mail/images/cleardot.gif] On Tue, May 10, 2016 at 8:22 AM, Mayuri Tendulkar mailto:mayuri.tendul...@aricent.com>> wrote: Hi I want to use Intel system debugger to do coreboot source level debugging. So I need below. Can you please help me in this? To debug your software using source code you need to load debug information that is used to map the program in target memory to the original source files. To do this the debugger needs the following: * A program loaded in target memory that has been compiled with debug information * The load address of the program in target memory * The program binary file (executable file) * Debug information file for the program binary (also referred to as "symbols") * Original program source code Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- coreboot mailing list: coreboot@coreboot.org<mailto:coreboot@coreboot.org> https://www.coreboot.org/mailman/listinfo/coreboot "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Coreboot image and seabios payload with debug symbols
Hi I want to use Intel system debugger to do coreboot source level debugging. So I need below. Can you please help me in this? To debug your software using source code you need to load debug information that is used to map the program in target memory to the original source files. To do this the debugger needs the following: * A program loaded in target memory that has been compiled with debug information * The load address of the program in target memory * The program binary file (executable file) * Debug information file for the program binary (also referred to as "symbols") * Original program source code Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Serial prints not coming on Minnowboard Turbot
Hi I have built coreboot using Minnowmax config file in coreboot with seabios payload. I don't see any serial console prints. Can you please confirm what could be the issue? If I flash Minnowboard Max file given on intel site, everything works fine and I see UEFI shell prompt. Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
