from:"Riko Ho"

Re: [coreboot] radare

2016-11-08 Thread Riko Ho


This is what I had done and worked on :

bianchi@ubuntu:~/Documents/Coreboot Column$ r2 i946gz_Edited.bin
[f000:fff0]> s f000:0
[f000:]> pD 0x
Do you want to print 4401484 chars? (y/N)
   ;  [0] va=0x000f pa=0x0007 sz=65536 vsz=65536 rwx=-rwx 
bootblk

;-- section.bootblk:
,=< f000:ead41100f0   jmp word 0xf000:0x11d4
|   f000:0005 add [bx+si], al
|   f000:0007 add [bx+si], al
|   f000:0009 add [bx+si], al
|   f000:000b add [bx+si], al
|   f000:000d add [bx+si], al
|   f000:000f00e8 add al, ch
|   f000:00110c01 or al, 0x1
   ,==< f000:0013745e jz 0xf0073
and so on until the bottom 4401481 chars...


On 9/11/2016 2:32 AM, Zoran Stojsavljevic wrote:

Hello to all radare2 experienced people,

From my VM Fedora 25 x86_64 on the top of VMWorkstation 12.5.1, on 
WIN10 64 Pro!


Here is my take on radare2... And I am not getting through. Transcript 
follows:


[zoran@localhost bios]$ radare2 -e asm.bits=16 -e io.va 
<http://io.va>=true BIOS_AMI_BIOS.bin

 -- attempt to dissasemble Core IVB AMI BIOS
[:]> S $s-0x1 0xF000:0x 0x1 0x1 bootblk rwx
[:]> e asm.segoff=true
[:]> e asm.syntax = intel
[:]> s 0xf000:0xfff0
[f000:fff0]> pd 16
f000:fff0  ff invalid
f000:fff1  ff invalid
f000:fff2  ff invalid
f000:fff3  ff invalid
f000:fff4  ff invalid
f000:fff5  ff invalid
f000:fff6  ff invalid
f000:fff7  ff invalid
f000:fff8  ff invalid
f000:fff9  ff invalid
f000:fffa  ff invalid
f000:fffb  ff invalid
f000:fffc  ff invalid
f000:fffd  ff invalid
f000:fffe  ff invalid
f000:  ff00   inc word [bx + si]
[f000:fff0]>

Help needed/comments appreciated. What am I doing wrong?

Thank you,
Zoran

On Mon, Nov 7, 2016 at 2:08 AM, Riko Ho <mailto:antonius.r...@gmail.com>> wrote:


Hi Zoran,
I reckon that's the right radare, find *.bin or *.rom or *.hex and run

[zoran@localhost ~]$ radare2 *.bin
and s command and pD commandfor example :

[f000:fff0]> s f000:0
[f000:]> pD 0x


more info :
https://radare.gitbooks.io/radare2book/content/disassembling/intro.html
<https://radare.gitbooks.io/radare2book/content/disassembling/intro.html>

On 7/11/2016 5:41 AM, Zoran Stojsavljevic wrote:

Hello Riko,
I recently also became very interested to start using radare2
(Raphael Machado's dissasembly attempts got involved me, to set
the tool). Since I am very lazy person, the first was to ask my
Fedora 25 distro does the distro have package radare2?
Yes, it does have it, so I have installed it. And for you, here
is the transcript of my CLI for you.
CLI traces (radare --help) are worth 1000nd words, don't you
agree? ;-)
Best Regards,
Zoran
___
[zoran@localhost ~]$ uname -r
4.8.6-300.fc25.x86_64
[zoran@localhost ~]$ which radare2
/usr/bin/radare2
*/_[zoran@localhost ~]$ radare2 --help_/*
radare2: invalid option -- '-'
r_config_get: variable 'lp' not found
 --   open radare2 on an empty file
 -equivalent of 'r2 malloc://512'
 =read file from stdin (use -i and -c to run cmds)
 -=   perform !=! command to run all commands remotely
 -0   print \x00 after init and every command
 -a [arch]set asm.arch
 -A   run 'aaa' command to analyze all referenced code
 -b [bits]set asm.bits
 -B [baddr]   set base address for PIE binaries
 -c 'cmd..'   execute radare command
 -C   file is host:port (alias for -c+=http://%s/cmd/)
 -d   debug the executable 'file' or running process 'pid'
 -D [backend] enable debug mode (e cfg.debug=true)
 -e k=v   evaluate config var
 -f   block size = file size
 -F [binplug] force to use that rbin plugin
 -h, -hh  show help message, -hh for long
 -i [file]run script file
 -I [file]run script file before the file is opened
 -k [k=v] perform sdb query into core->sdb
 -l [lib] load plugin file
 -L   list supported IO plugins
 -m [addr]map file at given address (loadaddr)
 -M   do not demangle symbol names
 -n, -nn  do not load RBin in

[coreboot] northbridge Intel 82846 ==>southbridge Intel 82801GX (ICH7) ==>IT8718 which is UART (I/0)

2016-11-07 Thread Riko Ho

I have no idea as well, I'm a beginner on coreboot stuff..you know 
better than me...


What I'm thinking, I need to find a way for initializing northbridge 
Intel 82946 ==>southbridge Intel 82801GX (ICH7) ==>IT8718 which is UART 
(I/0) since it has GPIO as well...

I got no idea on how to initialize northbridge yet

what do you reckon ? can CPU talk directly to IT8718F in this case ? or 
it needs NB and SB ?
Is any more documentations for Intel 82946 ? or that's the only one we 
can obtain ?


It doesn't matter if we can not find it, I want to learn, it's very good 
if we can solve it...but it's not, I have nothing to loose...


On 8/11/2016 7:25 AM, Idwer Vollering wrote:

I don't know, what do you think?

2016-11-08 0:07 GMT+01:00 Riko Ho :

On 7/11/2016 10:55 AM, Idwer Vollering wrote:

/

2016-11-07 2:59 GMT+01:00 Riko Ho :

Next line you're talking about :
 |   f000:0f1066becc8100e0 mov esi, 0xe00081cc
 |   f000:0f1667268b06 mov ax, [es:esi]
 |   f000:0f1a0d0010   or ax, 0x1000

==
 From what I recall is nico_h on IRC hinted that the PCIe bus must be
  up in order to be able to use the UART.
  There could be code for this that touches PCIEXBAR around these lines:
|||   f000:0f10  66becc8100e0   mov esi, 0xe00081cc
|||   f000:0f16  67268b06   mov ax, word es:[esi]
|||   f000:0f1a  0d0010 or ax, 0x1000

Since this writes to ax, the C code could look like this:
  MCHBAR16(0xe00081cc) |=0x1000;
  This would end up in romstage.c
==

in which function I put that MCHBAR16(0xe00081cc) |=0x1000; on romstage.c ?

No idea, it might belong in src/northbridge/intel/i945/raminit.c
instead. The C macro, MCHBAR16(), I mentioned was an example and won't
be useful for PCIEXBAR.

So what should we do for getting the correct PCIEXBAR and making UART
running ?

=
I suggest that you read at least chapter "5 Host Bridge/DRAM
Controller Registers (Device 0, Function 0) " starting on page 75.
=

Ok, I will do that, but I'm sure I have a lot of questions in relation
with the reversed code and romstage.c and this chapter 5.

--
/***/
Kind Regards
Riko Ho
/***/



--
/*===*/
Kind regards,
Riko Ho
/*===*/



--
*/*===*/
Kind regards,
Riko Ho
/*===*/ *
-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] radare

2016-11-07 Thread Riko Ho


Hi Zoran,
I reckon that's the right radare, find *.bin or *.rom or *.hex and run

[zoran@localhost ~]$ radare2 *.bin
and s command and pD commandfor example :

[f000:fff0]> s f000:0
[f000:]> pD 0x


more info :
https://radare.gitbooks.io/radare2book/content/disassembling/intro.html


On 7/11/2016 5:41 AM, Zoran Stojsavljevic wrote:

Hello Riko,

I recently also became very interested to start using radare2 (Raphael 
Machado's dissasembly attempts got involved me, to set the tool). 
Since I am very lazy person, the first was to ask my Fedora 25 distro 
does the distro have package radare2?


Yes, it does have it, so I have installed it. And for you, here is the 
transcript of my CLI for you.


CLI traces (radare --help) are worth 1000nd words, don't you agree? ;-)

Best Regards,
Zoran
___

[zoran@localhost ~]$ uname -r
4.8.6-300.fc25.x86_64
[zoran@localhost ~]$ which radare2
/usr/bin/radare2
*/_[zoran@localhost ~]$ radare2 --help_/*
radare2: invalid option -- '-'
r_config_get: variable 'lp' not found
 --   open radare2 on an empty file
 -equivalent of 'r2 malloc://512'
 =read file from stdin (use -i and -c to run cmds)
 -=   perform !=! command to run all commands remotely
 -0   print \x00 after init and every command
 -a [arch]set asm.arch
 -A   run 'aaa' command to analyze all referenced code
 -b [bits]set asm.bits
 -B [baddr]   set base address for PIE binaries
 -c 'cmd..'   execute radare command
 -C   file is host:port (alias for -c+=http://%s/cmd/)
 -d   debug the executable 'file' or running process 'pid'
 -D [backend] enable debug mode (e cfg.debug=true)
 -e k=v   evaluate config var
 -f   block size = file size
 -F [binplug] force to use that rbin plugin
 -h, -hh  show help message, -hh for long
 -i [file]run script file
 -I [file]run script file before the file is opened
 -k [k=v] perform sdb query into core->sdb
 -l [lib] load plugin file
 -L   list supported IO plugins
 -m [addr]map file at given address (loadaddr)
 -M   do not demangle symbol names
 -n, -nn  do not load RBin info (-nn only load bin structures)
 -N   do not load user settings and scripts
 -o [OS/kern] set asm.os (linux, macos, w32, netbsd, ...)
 -q   quiet mode (no prompt) and quit after -i
 -p [prj] use project, list if no arg, load if no file
 -P [file]apply rapatch file and quit
 -R [rarun2]  specify rarun2 profile to load (same as -e dbg.profile=X)
 -s [addr]initial seek
 -S   start r2 in sandbox mode
 -t   load rabin2 info in thread
 -u   set bin.filter=false to get raw sym/sec/cls names
 -v, -V   show radare2 version (-V show lib versions)
 -w   open file in write mode
 -z, -zz  do not load strings or load them even in raw
Scripts:
 system   /usr/share/radare2/radare2rc
 user ~/.radare2rc ${RHOMEDIR}/radare2/radare2rc (and radare2rc.d/)
 file ${filename}.r2
Plugins:
 plugins  /usr/lib/radare2/last
 user ~/.config/radare2/plugins
 LIBR_PLUGINS /usr/lib/radare2/0.10.6-git
Environment:
 RHOMEDIR /home/zoran/.config/radare2
 RCFILE   ~/.radare2rc (user preferences, batch script)
 MAGICPATH/usr/lib64/radare2/0.10.6-git/magic
 R_DEBUG  if defined, show error messages and crash signal
 VAPIDIR  path to extra vapi directory
 R2_NOPLUGINS do not load r2 shared plugins
Paths:
 PREFIX   /usr
 INCDIR   /usr/include/libr
 LIBDIR   /usr/lib64
 LIBEXT   so
[zoran@localhost ~]$

On Sat, Nov 5, 2016 at 3:55 AM, Riko Ho <mailto:antonius.r...@gmail.com>> wrote:


Hi Rafael,

For example I want to see the asm code for the whole
512Kbytesis that possible ?
How ?

Thanks

On 5/11/2016 3:36 AM, Rafael Machado wrote:

Hi

You can use the pd command.
p = Print
d = disassemby

You can also add the number of instruction you whant to see. For
example:

pd 10

Thanks
Rafael Machado

Em qua, 2 de nov de 2016 às 04:01, Riko Ho
mailto:antonius.r...@gmail.com>> escreveu:

Everyone, Idwer,

I have radare question :

I played until this point :
c:>radare2 -e asm.bits=16 -e io.va <http://io.va>=true i946gz.bin
  -- radare2 is WYSIWYF - what you see is what you fix
[f000:fff0]> S $s-0x1 0xF000:0x 0x1 0x1
bootblk rwx
[f000:fff0]> e asm.segoff=true
[f000:fff0]> s 0xf000:0x0
[f000:]>

How can I see the assembler code from there ? It's started from
0I'm sure the last byte instruction is jump to 0x0

Cheers

--
coreboot mailing list: coreboot@coreboot.org
<mailto:coreboot@coreboot.org>
https://www.coreboot.

Re: [coreboot] radare

2016-11-05 Thread Riko Ho


Hi Rafael,

For example I want to see the asm code for the whole 512Kbytesis 
that possible ?

How ?

Thanks
On 5/11/2016 3:36 AM, Rafael Machado wrote:

Hi

You can use the pd command.
p = Print
d = disassemby

You can also add the number of instruction you whant to see. For example:

pd 10

Thanks
Rafael Machado

Em qua, 2 de nov de 2016 às 04:01, Riko Ho <mailto:antonius.r...@gmail.com>> escreveu:


Everyone, Idwer,

I have radare question :

I played until this point :
c:>radare2 -e asm.bits=16 -e io.va <http://io.va>=true i946gz.bin
  -- radare2 is WYSIWYF - what you see is what you fix
[f000:fff0]> S $s-0x1 0xF000:0x 0x1 0x1 bootblk rwx
[f000:fff0]> e asm.segoff=true
[f000:fff0]> s 0xf000:0x0
[f000:]>

How can I see the assembler code from there ? It's started from
0I'm sure the last byte instruction is jump to 0x0

Cheers

--
coreboot mailing list: coreboot@coreboot.org
<mailto:coreboot@coreboot.org>
https://www.coreboot.org/mailman/listinfo/coreboot




--
*/*===*/
Kind regards,
Riko Ho
/*===*/ *
-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] Radare i946.bin

2016-11-02 Thread Riko Ho

Everyone, Idwer...

Here's what I've been playing with radare,

bianchi@ubuntu:~/Documents/Coreboot Column$ r2 -e asm.bits=16 -e
io.va=true i946gz_Edited.bin
[f000:fff0]> b7
[f000:fff0]> pd
;-- entry0:
f000:fff0ea5be000f0   jmp word 0xf000:0xe05b
f000:fff52a4d52   sub cl, [di+0x52]
f000:fff842   inc dx
f000:fff92a02 sub al, [bp+si]
f000:fffb add [bx+si], al
f000:fffd0060ff   add [bx+si-0x1], ah
;-- section_end.bootblk:

where can I see the relation between that block with PCIEXBAR register ?

Cheers,

-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] radare

2016-11-01 Thread Riko Ho


Everyone, Idwer,

I have radare question :

I played until this point :
c:>radare2 -e asm.bits=16 -e io.va=true i946gz.bin
 -- radare2 is WYSIWYF - what you see is what you fix
[f000:fff0]> S $s-0x1 0xF000:0x 0x1 0x1 bootblk rwx
[f000:fff0]> e asm.segoff=true
[f000:fff0]> s 0xf000:0x0
[f000:]>

How can I see the assembler code from there ? It's started from 
0I'm sure the last byte instruction is jump to 0x0


Cheers

--
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] PCIEXBAR 946 and 945

2016-10-31 Thread Riko Ho


Good day everyone,

I got info from Kmalkki, that I need to adapt PCIEXBAR value for 946 
from 945

I saw in bootblock.c  for 945, it's 0x48...

What value is it for i946 ?

I tried reading datasheet, I found it on page 43, page 55 and pointing 
to chapter 6, but I can not find a clear explaination on how to use 
PCIEXBAR register...

Does anyone come to this point as well ? How to solve it ?

If I can not get the right value, I don't think I can give a good 
initialization for my IT8718F, because I can not point the address for it..


Cheers

--
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] POST 0xFFFF

2016-10-30 Thread Riko Ho

Everyone,

I got POST 0x then loop, and UART = 00
I have rewritten the ich7_enable_lpc function, and the complete
romstage.c attached, what do I miss here ? Does enable_lapic();
function depend to the board or it can run on 946 even it's written
for 945?

static void ich7_enable_lpc(void)
{
// Enable Serial IRQ
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
// Set COM1/COM2 decode range
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
// Enable COM1
//pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x140d);
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3407); //from
sudo lspci -xxx -s 0:1F.0
// Enable SuperIO Power Management Events
//pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c0681);
//pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x01340700);
  pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84,
0x003C0801);//from sudo lspci -xxx -s 0:1F.0, Idwer suggestion
}

 bianchi@bianchi-AcerPower-SK50:~$ sudo lspci -xxx -s 0:1F.0
>> [sudo] password for bianchi:
>> 00:1f.0 ISA bridge: Intel Corporation 82801GB/GR (ICH7 Family) LPC
>> Interface Bridge (rev 01)
>> 00: 86 80 b8 27 07 01 10 02 01 00 01 06 00 00 80 00
>> 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
>> 20: 00 00 00 00 00 00 00 00 00 00 00 00 19 10 96 21
>> 30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00
>> 40: 01 04 00 00 80 00 00 00 81 04 00 00 10 00 00 00
>> 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
>> 60: 8a 89 89 8f d0 00 00 00 89 80 80 8f 00 00 00 00
>> 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
>> 80: 10 00 07 34 01 08 3c 00 91 02 1c 00 00 00 00 00
>> 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
>> a0: 23 02 00 00 38 00 00 00 13 00 00 00 00 03 00 00
>> b0: 00 00 f0 00 00 00 00 00 55 55 55 59 00 00 00 00
>> c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
>> d0: 33 22 11 00 67 45 00 00 c0 c0 00 00 00 00 00 00
>> e0: 09 00 0c 10 a8 00 24 00 00 00 00 00 00 00 00 00
>> f0: 01 c0 d1 fe 00 00 00 00 86 0f 01 00 00 00 00 00
/*
 * This file is part of the coreboot project.
 *
 * Copyright (C) 2007-2008 coresystems GmbH
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

// __PRE_RAM__ means: use "unsigned" for device, not a struct.

#include 
#include 
#include 
#include 
#include 
#include 
#include 
#include 
#include 
#include 
#include 


//#include 
//Found ITE IT8718F (id=0x8718, rev=0x1) at 0x2e
//#include 
#include 
#include 
#include 
#include 
#include 
#include 
#include 


#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO)
#define CLKIN_DEV PNP_DEV(0x2e, IT8718F_GPIO)
#define EC_DEV PNP_DEV(0x2e, IT8718F_EC) //Patch on 28 October 2016
#define SUPERIO_DEV PNP_DEV(0x2e, 0)

//#define PME_DEV PNP_DEV(0x2e, LPC47M15X_PME)

void setup_ich7_gpios(void)
{
	/* TODO: This is highly board specific and should be moved */
	//printk(BIOS_DEBUG, " GPIOS...");
	/* General Registers */
	//outl(0x3f3df7c1, DEFAULT_GPIOBASE + 0x00);	/* GPIO_USE_SEL */
	//outl(0xc6fcbfc3, DEFAULT_GPIOBASE + 0x04);	/* GP_IO_SEL */
	//outl(0xecfefdff, DEFAULT_GPIOBASE + 0x0c);	/* GP_LVL */
	/* Output Control Registers */
	//outl(0x0004, DEFAULT_GPIOBASE + 0x18);	/* GPO_BLINK */
	/* Input Control Registers */
	//outl(0xa000, DEFAULT_GPIOBASE + 0x2c);	/* GPI_INV */
	//outl(0x00ff, DEFAULT_GPIOBASE + 0x30);	/* GPIO_USE_SEL2 */
	//outl(0x00bf, DEFAULT_GPIOBASE + 0x34);	/* GP_IO_SEL2 */
	//outl(0x000300fd, DEFAULT_GPIOBASE + 0x38);	/* GP_LVL */
   /*updated from intel tool for i946GZ*/
   /* TODO: This is highly board specific and should be moved */
	printk(BIOS_DEBUG, " GPIOS...");
	/* General Registers */
	outl(0x1f3ff7c3, DEFAULT_GPIOBASE + 0x00);	/* GPIO_USE_SEL */
	outl(0xe0e8ffc3, DEFAULT_GPIOBASE + 0x04);	/* GP_IO_SEL */
	outl(0xe27effc3, DEFAULT_GPIOBASE + 0x0c);	/* GP_LVL */
	/* Output Control Registers */
	outl(0x0004, DEFAULT_GPIOBASE + 0x18);	/* GPO_BLINK */
	/* Input Control Registers */
	outl(0x3900, DEFAULT_GPIOBASE + 0x2c);	/* GPI_INV */
	outl(0x00ff, DEFAULT_GPIOBASE + 0x30);	/* GPIO_USE_SEL2 */
	outl(0x00f0, DEFAULT_GPIOBASE + 0x34);	/* GP_IO_SEL2 */
	outl(0x000300f3, DEFAULT_GPIOBASE + 0x38);	/* GP_LVL */ 
}
/*
static void setup_sio(void)
{*/
	/* Set default GPIOs on superio */
/*	ite_reg_write(GPIO_DEV, 0x25, 0x40);
	ite_reg_write(GPIO_DEV, 0x26, 0x3f);
	ite_reg_write(GPIO_DEV, 0x28, 0x41);
	ite_reg_write(GPIO_DEV, 0x29, 0x88);
	ite_reg_write(GPIO_DEV, 0x2c, 0x1c);
	ite_reg_write(GPIO_DEV, 0x62, 0x08);
	ite_reg_write(GPIO_DEV, 0x72, 0x00);
	ite_reg_write(GPIO_DEV, 0x73, 0x38);

Re: [coreboot] lspci -xxx -s 0:1F.0 ?

2016-10-30 Thread Riko Ho


Idwer, thanks for the info,

How come it's different with:
80  81  82 83

80: 10 00*07 34 *01 08 3c 00 91 02 1c 00 00 00 00 00
change this to pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x*3407*);

It's reversing backward,


On 31/10/2016 7:35 AM, Idwer Vollering wrote:

2016-10-31 0:18 GMT+01:00 Riko Ho :

Hi Idwer,
 80 81 82 83 84
80: 10 00 07 34*01 08 3c 00*  91 02 1c 00 00 00 00 00

0x84 starts here:  ^^
 it's going forward, which way is the right one ? I'll have a read 
of that link may be 32bits and 16bits causing it...? I misunderstand it 
I reckon...



isn't it :

pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00073401);
?

The byte ordering has to do with endianness, see this webpage:
https://docs.oracle.com/cd/E26505_01/html/E27000/hwovr-66.html


(correct me if I'm wrong)
change this to pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84,*0x003c0801*);



--
/*===
Kind regards,
Riko Ho
===*/



--
*/*===
Kind regards,
Riko Ho
===*/ *
-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] lspci -xxx -s 0:1F.0 ?

2016-10-30 Thread Riko Ho


Hi Idwer,
*80 81 82 83 84*
80: 10*00 07 34 01*  08 3c 00 91 02 1c 00 00 00 00 00

isn't it :**pci_write_config32(PCI_DEV(0, 0x1f, 0),*0x84, 0x00073401); *
?


(correct me if I'm wrong)
change this to pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x003c0801);




--
*/*===
Kind regards,
Riko Ho
===*/ *
-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] lspci -xxx -s 0:1F.0 ?

2016-10-29 Thread Riko Ho


I have compiled this function, hopefully it will work...
http://dpaste.com/195R18B

On 30/10/2016 7:21 AM, Idwer Vollering wrote:

2016-10-30 1:18 GMT+02:00 Idwer Vollering :

2016-10-30 1:04 GMT+02:00 Riko Ho :

Everyone,

How can I use the result from

sudo lspci -xxx -s 0:1F.0

inside this function ?

static void ich7_enable_lpc(void)
{
 // Enable Serial IRQ
 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);

This looks good, because lspci tells you this: 60: 8a 89 89 8f d0 00
00 00 89 80 80 8f 00 00 00 00


 // Set COM1/COM2 decode range
 pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);

This looks good, because lspci tells you this: 60: 8a 89 89 8f d0 00
00 00 89 80 80 8f 00 00 00 00

mea culpa, the above should have been 80: 10 00 07 34 01 08 3c 00 91
02 1c 00 00 00 00 00


 // Enable COM1
 pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x140d);

lspci's output: 80: 10 00 07 34 01 08 3c 00 91 02 1c 00 00 00 00 00
change this to pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3407);


 // Enable SuperIO Power Management Events
 pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c0681);

lspci's output: 80:  01 08 3c 00

^ this was me, stripping the whole line to the value that should be
written.. whole line:
80: 10 00 07 34 01 08 3c 00 91 02 1c 00 00 00 00 00


(correct me if I'm wrong)
change this to pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x003c0801);


}


are they correctly defined or something not right ?










bianchi@bianchi-AcerPower-SK50:~$ sudo lspci -xxx -s 0:1F.0
[sudo] password for bianchi:
00:1f.0 ISA bridge: Intel Corporation 82801GB/GR (ICH7 Family) LPC
Interface Bridge (rev 01)
00: 86 80 b8 27 07 01 10 02 01 00 01 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 19 10 96 21
30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00
40: 01 04 00 00 80 00 00 00 81 04 00 00 10 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 8a 89 89 8f d0 00 00 00 89 80 80 8f 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 10 00 07 34 01 08 3c 00 91 02 1c 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 23 02 00 00 38 00 00 00 13 00 00 00 00 03 00 00
b0: 00 00 f0 00 00 00 00 00 55 55 55 59 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 33 22 11 00 67 45 00 00 c0 c0 00 00 00 00 00 00
e0: 09 00 0c 10 a8 00 24 00 00 00 00 00 00 00 00 00
f0: 01 c0 d1 fe 00 00 00 00 86 0f 01 00 00 00 00 00

Cheers


--
/*===
Kind regards,
Riko Ho
===*/

--
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot



--
*/*===
Kind regards,
Riko Ho
===*/ *
-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] lspci -xxx -s 0:1F.0 ?

2016-10-29 Thread Riko Ho


On 30/10/2016 7:21 AM, Idwer Vollering wrote:

2016-10-30 1:18 GMT+02:00 Idwer Vollering :

2016-10-30 1:04 GMT+02:00 Riko Ho :

Everyone,

How can I use the result from

sudo lspci -xxx -s 0:1F.0

inside this function ?

static void ich7_enable_lpc(void)
{
 // Enable Serial IRQ
 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);

This looks good, because lspci tells you this: 60: 8a 89 89 8f d0 00
00 00 89 80 80 8f 00 00 00 00


 // Set COM1/COM2 decode range
 pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);

This looks good, because lspci tells you this: 60: 8a 89 89 8f d0 00
00 00 89 80 80 8f 00 00 00 00

mea culpa, the above should have been 80: 10 00 07 34 01 08 3c 00 91
02 1c 00 00 00 00 00


 // Enable COM1
 pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x140d);

lspci's output: 80: 10 00 07 34 01 08 3c 00 91 02 1c 00 00 00 00 00
change this to pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3407);


 // Enable SuperIO Power Management Events
 pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c0681);

lspci's output: 80:  01 08 3c 00

^ this was me, stripping the whole line to the value that should be
written.. whole line:
80: 10 00 07 34 01 08 3c 00 91 02 1c 00 00 00 00 00


(correct me if I'm wrong)
change this to pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x003c0801);


}

if we cut from 84 and following the logic from

change this to pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3407);

pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x01340700); ...or ?






are they correctly defined or something not right ?










bianchi@bianchi-AcerPower-SK50:~$ sudo lspci -xxx -s 0:1F.0
[sudo] password for bianchi:
00:1f.0 ISA bridge: Intel Corporation 82801GB/GR (ICH7 Family) LPC
Interface Bridge (rev 01)
00: 86 80 b8 27 07 01 10 02 01 00 01 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 19 10 96 21
30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00
40: 01 04 00 00 80 00 00 00 81 04 00 00 10 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 8a 89 89 8f d0 00 00 00 89 80 80 8f 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 10 00 07 34 01 08 3c 00 91 02 1c 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 23 02 00 00 38 00 00 00 13 00 00 00 00 03 00 00
b0: 00 00 f0 00 00 00 00 00 55 55 55 59 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 33 22 11 00 67 45 00 00 c0 c0 00 00 00 00 00 00
e0: 09 00 0c 10 a8 00 24 00 00 00 00 00 00 00 00 00
f0: 01 c0 d1 fe 00 00 00 00 86 0f 01 00 00 00 00 00

Cheers


--
/*===
Kind regards,
Riko Ho
===*/

--
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot



--
*/*===
Kind regards,
Riko Ho
===*/ *
-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] lspci -xxx -s 0:1F.0 ?

2016-10-29 Thread Riko Ho

Thanks Idwer, that's what I've been thinking something is not the same 
between lspci and the function, I'll give a try, perhaps it will answer 
our puzzle...


On 30/10/2016 7:18 AM, Idwer Vollering wrote:

2016-10-30 1:04 GMT+02:00 Riko Ho :

Everyone,

How can I use the result from

sudo lspci -xxx -s 0:1F.0

inside this function ?

static void ich7_enable_lpc(void)
{
 // Enable Serial IRQ
 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);

This looks good, because lspci tells you this: 60: 8a 89 89 8f d0 00
00 00 89 80 80 8f 00 00 00 00


 // Set COM1/COM2 decode range
 pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);

This looks good, because lspci tells you this: 60: 8a 89 89 8f d0 00
00 00 89 80 80 8f 00 00 00 00


 // Enable COM1
 pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x140d);

lspci's output: 80: 10 00 07 34 01 08 3c 00 91 02 1c 00 00 00 00 00
change this to pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3407);


 // Enable SuperIO Power Management Events
 pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c0681);

lspci's output: 80:  01 08 3c 00

(correct me if I'm wrong)
change this to pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x003c0801);


}


are they correctly defined or something not right ?










bianchi@bianchi-AcerPower-SK50:~$ sudo lspci -xxx -s 0:1F.0
[sudo] password for bianchi:
00:1f.0 ISA bridge: Intel Corporation 82801GB/GR (ICH7 Family) LPC
Interface Bridge (rev 01)
00: 86 80 b8 27 07 01 10 02 01 00 01 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 19 10 96 21
30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00
40: 01 04 00 00 80 00 00 00 81 04 00 00 10 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 8a 89 89 8f d0 00 00 00 89 80 80 8f 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 10 00 07 34 01 08 3c 00 91 02 1c 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 23 02 00 00 38 00 00 00 13 00 00 00 00 03 00 00
b0: 00 00 f0 00 00 00 00 00 55 55 55 59 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 33 22 11 00 67 45 00 00 c0 c0 00 00 00 00 00 00
e0: 09 00 0c 10 a8 00 24 00 00 00 00 00 00 00 00 00
f0: 01 c0 d1 fe 00 00 00 00 86 0f 01 00 00 00 00 00

Cheers


--
/*===
Kind regards,
Riko Ho
===*/

--
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

.




--
*/*===
Kind regards,
Riko Ho
===*/ *
-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] lspci -xxx -s 0:1F.0 ?

2016-10-29 Thread Riko Ho


Everyone,

How can I use the result from

sudo lspci -xxx -s 0:1F.0

inside this function ?

static void ich7_enable_lpc(void)
{
// Enable Serial IRQ
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
// Set COM1/COM2 decode range
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
// Enable COM1
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x140d);
// Enable SuperIO Power Management Events
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c0681);
}


are they correctly defined or something not right ?











bianchi@bianchi-AcerPower-SK50:~$ sudo lspci -xxx -s 0:1F.0
[sudo] password for bianchi:
00:1f.0 ISA bridge: Intel Corporation 82801GB/GR (ICH7 Family) LPC
Interface Bridge (rev 01)
00: 86 80 b8 27 07 01 10 02 01 00 01 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 19 10 96 21
30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00
40: 01 04 00 00 80 00 00 00 81 04 00 00 10 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 8a 89 89 8f d0 00 00 00 89 80 80 8f 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 10 00 07 34 01 08 3c 00 91 02 1c 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 23 02 00 00 38 00 00 00 13 00 00 00 00 03 00 00
b0: 00 00 f0 00 00 00 00 00 55 55 55 59 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 33 22 11 00 67 45 00 00 c0 c0 00 00 00 00 00 00
e0: 09 00 0c 10 a8 00 24 00 00 00 00 00 00 00 00 00
f0: 01 c0 d1 fe 00 00 00 00 86 0f 01 00 00 00 00 00

Cheers


--
*/*===
Kind regards,
Riko Ho
===*/ *
-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Stops at 0xD2

2016-10-28 Thread Riko Ho


Stefan,

Yes I'm using the right driver, I'm not sure if that driver is 
doing what we need to run this chip, I didn't make it, but I'll improve 
it if it's needed,
 I took this register data awhile ago , and I have some discussions at 
IRC to have a look on register 0x23...


So far I can't get 8718 on my POST card
Which register is related with UART setting ? I'll find out on datasheet 
anyway, but it would be very nice if you have a clues...


Is it :
LDN 0x01 (COM1)
idx 30 60 61 70 f0 f1 f2 f3

?
How can I retrieve that value to my POST card for debugging and see what 
it's saying to us ?

Cheers,
RH

Please have a look:

Probing for ITE Super I/O (init=standard) at 0x2e...
Found ITE IT8718F (id=0x8718, rev=0x1) at 0x2e
*Register dump:**
**idx 20 21 22 23 24 2b**
**val 87 18 01 10 00 00**
**def 87 18 01 00 00 00*
LDN 0x00 (Floppy)
idx 30 60 61 70 74 f0 f1
val 00 00 00 00 00 00 80
def 00 03 f0 06 02 00 00
*LDN 0x01 (COM1)
idx 30 60 61 70 f0 f1 f2 f3
val 01 03 f8 04 00 50 00 7f
def 00 03 f8 04 00 50 00 7f*
LDN 0x02 (COM2)
idx 30 60 61 70 f0 f1 f2 f3
val 01 02 f8 03 00 50 00 7f
def 00 02 f8 03 00 50 00 7f
LDN 0x03 (Parallel port)
idx 30 60 61 62 63 70 74 f0
val 01 03 78 00 00 07 04 08
def 00 03 78 07 78 07 03 03
LDN 0x04 (Environment controller)
idx 30 60 61 62 63 70 f0 f1  f2 f3 f4 f5 f6
val 01 02 90 00 00 00 00 00  2a 00 80 00 ff
def 00 02 90 02 30 09 00 00  00 00 00 NA NA
LDN 0x05 (Keyboard)
idx 30 60 61 62 63 70 71 f0
val 01 00 60 00 64 01 02 68
def 01 00 60 00 64 01 02 00
LDN 0x06 (Mouse)
idx 30 70 71 f0
val 01 0c 02 00
def 00 0c 02 00
LDN 0x07 (GPIO)
idx 25 26 27 28 29 2a 2c 60  61 62 63 64 65 70 71 72  73 74 b0 b1 b2 b3 
b4 b5  b8 b9 ba bb bc bd c0 c1  c2 c3 c4 c5 c8 c9 ca cb  cc e0 e1 e2 e3 
e4 e5 e6  e7 f0 f1 f2 f3 f4 f5 f6  f7 f8 f9 fa fb fc fd fe  ff
val 00 10 00 01 08 80 1f 00  00 08 00 00 00 00 00 00  38 00 80 00 00 00 
00 00  00 18 00 00 00 00 00 00  00 00 00 00 00 00 00 01  08 00 00 00 00 
00 00 00  00 10 00 00 00 14 00 00  00 2b 01 00 06 ff 00 00  00
def 01 00 00 40 00 00 00 00  00 00 00 00 00 00 00 20  38 00 00 00 00 00 
00 00  00 00 00 00 00 00 01 00  00 40 00 00 01 00 00 40  00 00 00 00 00 
00 00 00  00 00 00 00 00 00 00 00  00 00 00 00 00 NA 00 00  00

LDN 0x0a (Consumer IR)
idx 30 60 61 70 f0
val 00 00 00 00 06
def 00 03 10 0b 00
Environment controller (0x0295)
Register dump:
idx 00 01 02 03 04 05 06 07  08 09 0a 0b 0c 0d 0e 0f  10 11 12 13 14 15 
16 17  18 19 1a 1b 1c 1d 20 21  22 23 24 25 26 27 28 29  2a 2b 30 31 32 
33 34 35  36 37 38 39 3a 3b 3c 3d  3e 3f 40 41 42 43 44 45  50 51 52 53 
54 56 57 58  59 5b 5c 5d 5e 5f 60 61  62 63 64 65 68 69 6a 6b  6c 6d 70 
71 72 73 74 75  80 81 82 83 88 89 8a 8b  8c 8d 8e 8f 90 91 92 94  95 96 
a0 a1 a2 a3 a4 a5  a6
val 13 14 ff 02 ff ff fb 00  00 80 00 09 07 35 ff ff  ff ff 00 77 d0 82 
80 3f  01 ff ff ff ff ff 4b bc  cd ba 4c b3 6c b8 c5 1b  7f 22 ff ff ff 
ff ff ff  ff ff 19 37 ff ff 3a 2d  ff ff 5a 7f 5a 7f 5a 7f  ff 1c 7f 7f 
7f e6 e6 90  e6 12 80 00 00 00 05 30  7f 19 28 82 05 27 7f 37  38 82 7f 
7f 7f 00 00 7f  00 00 00 00 00 00 00 00  00 00 02 00 ff 00 00 ff  00 00 
00 00 00 00 00 00  00
def 18 00 00 00 00 00 00 00  00 80 40 09 00 NA NA NA  NA NA NA 07 50 MM 
MM MM  NA NA NA NA NA NA NA NA  NA NA NA NA NA NA NA NA  NA NA NA NA NA 
NA NA NA  NA NA NA NA NA NA NA NA  NA NA NA NA NA NA NA NA  00 00 7f 7f 
7f 00 00 90  00 12 00 00 00 00 7f 7f  7f 00 00 7f 7f 7f 7f 00  00 7f 7f 
7f 7f 00 00 7f  NA NA NA NA 00 00 00 00  00 00 02 00 ff 00 00 ff  00 00 
00 00 00 00 00 00  00

BRAM (0x)
=
Probing for ITE Super I/O (init=standard) at 0x4e...
  Failed. Returned dat
On 29/10/2016 6:56 AM, Stefan Reinauer wrote:

* Riko Ho  [161026 03:36]:

Everyone,

I tried to initialize UART on IT8718F and it stopped at 0xD2...
Here's the complete function, any clues ?

Yes, there is a halt() right after the post_code(0xd2); so that is where
your last post code is coming from.

use superiotool (from coreboot/util) to dump the superio registers on a
running system and compare them with what you write in there and the
data sheet.

Are you sure you are using the correct SuperIO driver?

Stefan


Cheers
===
void mainboard_romstage_entry(unsigned long bist)
{
 int s3resume = 0, boot_mode = 0;

 if (bist == 0)
 enable_lapic();

 ich7_enable_lpc();
 post_code(0xD1);
 /* Enable SuperIO PM */
 //lpc47m15x_enable_serial(PME_DEV, 0x680);
 //lpc47m15x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */
 //enable_dev(SERIAL_DEV);
 //ite_conf_clkin();//needs a parameter, what is it ?

 /*
 04:24:31 AM) idwer: 24 or 48 MHz?

 (04:25:18 AM) idwer: how do you find out? run superiotool when
having booted with the vendor bios, and look atregister
CR23
  */
 //ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24);
 ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48);


 ite_enable_se

Re: [coreboot] Stops at 0xD2

2016-10-25 Thread Riko Ho

Which superIO register should we read to make sure LPC bus
communication to superio works?

On Wed, Oct 26, 2016 at 9:58 AM, Kyösti Mälkki  wrote:
> The information missing from the mail is I requested to have that halt()
> added after console_init().
>
> Also at least it was previously reported system was in a periodic reset-loop
> regardless of the halt() there, so sn active watchdog may be involved here.
> Looks like other boards
> with same superio use call ite_kill_watchdog(), I don't know what
> it8718f_disable_reboot() does.
>
> There was also suggestion to dump superio ID register on POST display to
> make sure LPC bus communication to superio works, but I did not hear back
> from that experiment.
>
> Kyösti
>
> On Wed, Oct 26, 2016 at 4:36 AM, Riko Ho  wrote:
>>
>> Everyone,
>>
>> I tried to initialize UART on IT8718F and it stopped at 0xD2...
>> Here's the complete function, any clues ?
>>
>> Cheers
>> ===
>> void mainboard_romstage_entry(unsigned long bist)
>> {
>> int s3resume = 0, boot_mode = 0;
>>
>> if (bist == 0)
>> enable_lapic();
>>
>> ich7_enable_lpc();
>> post_code(0xD1);
>> /* Enable SuperIO PM */
>> //lpc47m15x_enable_serial(PME_DEV, 0x680);
>> //lpc47m15x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */
>> //enable_dev(SERIAL_DEV);
>> //ite_conf_clkin();//needs a parameter, what is it ?
>>
>> /*
>> 04:24:31 AM) idwer: 24 or 48 MHz?
>>
>> (04:25:18 AM) idwer: how do you find out? run superiotool when
>> having booted with the vendor bios, and look atregister
>> CR23
>>  */
>> //ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24);
>> ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48);
>>
>>
>> ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */
>> //printk(BIOS_DEBUG,"HELLO WORLD FROM COREBOOT BY RIKO HO...\n");
>> //it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
>> it8718f_disable_reboot(GPIO_DEV);
>> /* Set up the console */
>> console_init();
>> post_code(0xD2);
>> printk(BIOS_DEBUG,"HELLO WORLD FROM COREBOOT ...\n");
>> halt();
>> post_code(0xD3);
>>
>>
>>
>> /* Halt if there was a built in self test failure */
>> report_bist_failure(bist);
>>
>> if (MCHBAR16(SSKPD) == 0xCAFE) {
>> printk(BIOS_DEBUG, "soft reset detected.\n");
>> boot_mode = 1;
>> }
>>
>> /* Perform some early chipset initialization required
>>  * before RAM initialization can work
>>  */
>> i945_early_initialization();
>> post_code(0xD4);
>> s3resume = southbridge_detect_s3_resume();
>>
>> /* Enable SPD ROMs and DDR-II DRAM */
>> enable_smbus();
>>
>> #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
>> dump_spd_registers();
>> #endif
>>
>> sdram_initialize(s3resume ? 2 : boot_mode, NULL);
>>
>> /* Perform some initialization that must run before stage2 */
>> early_ich7_init();
>>
>> /* This should probably go away. Until now it is required
>>  * and mainboard specific
>>  */
>> rcba_config();
>>
>> /* Chipset Errata! */
>> fixup_i945_errata();
>>
>> /* Initialize the internal PCIe links before we go into stage2 */
>> i945_late_initialization(s3resume);
>> }
>>
>> --
>> coreboot mailing list: coreboot@coreboot.org
>> https://www.coreboot.org/mailman/listinfo/coreboot
>
>

-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Stops at 0xD2

2016-10-25 Thread Riko Ho

It needs parameterwhat parameter do you think ?

src/mainboard/intel/i946gz/romstage.c: In function 'mainboard_romstage_entry':
src/mainboard/intel/i946gz/romstage.c:209:9: error: too few arguments
to function 'ite_kill_watchdog'
 ite_kill_watchdog();
 ^
In file included from src/mainboard/intel/i946gz/romstage.c:28:0:
src/superio/ite/common/ite.h:32:6: note: declared here
 void ite_kill_watchdog(pnp_devfn_t dev);


On Wed, Oct 26, 2016 at 9:58 AM, Kyösti Mälkki  wrote:
> The information missing from the mail is I requested to have that halt()
> added after console_init().
>
> Also at least it was previously reported system was in a periodic reset-loop
> regardless of the halt() there, so sn active watchdog may be involved here.
> Looks like other boards
> with same superio use call ite_kill_watchdog(), I don't know what
> it8718f_disable_reboot() does.
>
> There was also suggestion to dump superio ID register on POST display to
> make sure LPC bus communication to superio works, but I did not hear back
> from that experiment.
>
> Kyösti
>
> On Wed, Oct 26, 2016 at 4:36 AM, Riko Ho  wrote:
>>
>> Everyone,
>>
>> I tried to initialize UART on IT8718F and it stopped at 0xD2...
>> Here's the complete function, any clues ?
>>
>> Cheers
>> ===
>> void mainboard_romstage_entry(unsigned long bist)
>> {
>> int s3resume = 0, boot_mode = 0;
>>
>> if (bist == 0)
>> enable_lapic();
>>
>> ich7_enable_lpc();
>> post_code(0xD1);
>> /* Enable SuperIO PM */
>> //lpc47m15x_enable_serial(PME_DEV, 0x680);
>> //lpc47m15x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */
>> //enable_dev(SERIAL_DEV);
>> //ite_conf_clkin();//needs a parameter, what is it ?
>>
>> /*
>> 04:24:31 AM) idwer: 24 or 48 MHz?
>>
>> (04:25:18 AM) idwer: how do you find out? run superiotool when
>> having booted with the vendor bios, and look atregister
>> CR23
>>  */
>>     //ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24);
>> ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48);
>>
>>
>> ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */
>> //printk(BIOS_DEBUG,"HELLO WORLD FROM COREBOOT BY RIKO HO...\n");
>> //it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
>> it8718f_disable_reboot(GPIO_DEV);
>> /* Set up the console */
>> console_init();
>> post_code(0xD2);
>> printk(BIOS_DEBUG,"HELLO WORLD FROM COREBOOT ...\n");
>> halt();
>> post_code(0xD3);
>>
>>
>>
>> /* Halt if there was a built in self test failure */
>> report_bist_failure(bist);
>>
>> if (MCHBAR16(SSKPD) == 0xCAFE) {
>> printk(BIOS_DEBUG, "soft reset detected.\n");
>> boot_mode = 1;
>> }
>>
>> /* Perform some early chipset initialization required
>>  * before RAM initialization can work
>>  */
>> i945_early_initialization();
>> post_code(0xD4);
>> s3resume = southbridge_detect_s3_resume();
>>
>> /* Enable SPD ROMs and DDR-II DRAM */
>> enable_smbus();
>>
>> #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
>> dump_spd_registers();
>> #endif
>>
>> sdram_initialize(s3resume ? 2 : boot_mode, NULL);
>>
>> /* Perform some initialization that must run before stage2 */
>> early_ich7_init();
>>
>> /* This should probably go away. Until now it is required
>>  * and mainboard specific
>>  */
>> rcba_config();
>>
>> /* Chipset Errata! */
>> fixup_i945_errata();
>>
>> /* Initialize the internal PCIe links before we go into stage2 */
>> i945_late_initialization(s3resume);
>> }
>>
>> --
>> coreboot mailing list: coreboot@coreboot.org
>> https://www.coreboot.org/mailman/listinfo/coreboot
>
>

-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Stops at 0xD2

2016-10-25 Thread Riko Ho

Thanks for the reply
Let me step it :

1.
I got this when I compile it :
build/auto.conf:1974:warning: override: reassigning to symbol
CONSOLE_SERIAL_TEGRA210_UART_CHOICES

2. I requested to have that halt() added after console_init().
===>Ok, I will move it

3. Looks like other boards
with same superio use call ite_kill_watchdog(), I don't know what
it8718f_disable_reboot() does.
===> I have no idea as well, I followed on example from the board
which used it8718f

4. There was also suggestion to dump superio ID register on POST
display to make sure LPC bus communication to superio works, but I did
not hear back from that experiment.
===> can you tell me how to do that ?

Cheers

On Wed, Oct 26, 2016 at 9:58 AM, Kyösti Mälkki  wrote:
> The information missing from the mail is I requested to have that halt()
> added after console_init().
>
> Also at least it was previously reported system was in a periodic reset-loop
> regardless of the halt() there, so sn active watchdog may be involved here.
> Looks like other boards
> with same superio use call ite_kill_watchdog(), I don't know what
> it8718f_disable_reboot() does.
>
> There was also suggestion to dump superio ID register on POST display to
> make sure LPC bus communication to superio works, but I did not hear back
> from that experiment.
>
> Kyösti
>
> On Wed, Oct 26, 2016 at 4:36 AM, Riko Ho  wrote:
>>
>> Everyone,
>>
>> I tried to initialize UART on IT8718F and it stopped at 0xD2...
>> Here's the complete function, any clues ?
>>
>> Cheers
>> ===
>> void mainboard_romstage_entry(unsigned long bist)
>> {
>> int s3resume = 0, boot_mode = 0;
>>
>> if (bist == 0)
>> enable_lapic();
>>
>> ich7_enable_lpc();
>> post_code(0xD1);
>> /* Enable SuperIO PM */
>> //lpc47m15x_enable_serial(PME_DEV, 0x680);
>> //lpc47m15x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */
>> //enable_dev(SERIAL_DEV);
>> //ite_conf_clkin();//needs a parameter, what is it ?
>>
>> /*
>> 04:24:31 AM) idwer: 24 or 48 MHz?
>>
>> (04:25:18 AM) idwer: how do you find out? run superiotool when
>> having booted with the vendor bios, and look atregister
>> CR23
>>  */
>> //ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24);
>> ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48);
>>
>>
>> ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */
>> //printk(BIOS_DEBUG,"HELLO WORLD FROM COREBOOT BY RIKO HO...\n");
>> //it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
>> it8718f_disable_reboot(GPIO_DEV);
>> /* Set up the console */
>> console_init();
>> post_code(0xD2);
>> printk(BIOS_DEBUG,"HELLO WORLD FROM COREBOOT ...\n");
>> halt();
>> post_code(0xD3);
>>
>>
>>
>> /* Halt if there was a built in self test failure */
>> report_bist_failure(bist);
>>
>> if (MCHBAR16(SSKPD) == 0xCAFE) {
>> printk(BIOS_DEBUG, "soft reset detected.\n");
>> boot_mode = 1;
>> }
>>
>> /* Perform some early chipset initialization required
>>  * before RAM initialization can work
>>  */
>> i945_early_initialization();
>> post_code(0xD4);
>> s3resume = southbridge_detect_s3_resume();
>>
>> /* Enable SPD ROMs and DDR-II DRAM */
>> enable_smbus();
>>
>> #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
>> dump_spd_registers();
>> #endif
>>
>> sdram_initialize(s3resume ? 2 : boot_mode, NULL);
>>
>> /* Perform some initialization that must run before stage2 */
>> early_ich7_init();
>>
>> /* This should probably go away. Until now it is required
>>  * and mainboard specific
>>  */
>> rcba_config();
>>
>> /* Chipset Errata! */
>> fixup_i945_errata();
>>
>> /* Initialize the internal PCIe links before we go into stage2 */
>> i945_late_initialization(s3resume);
>> }
>>
>> --
>> coreboot mailing list: coreboot@coreboot.org
>> https://www.coreboot.org/mailman/listinfo/coreboot
>
>

-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] Stops at 0xD2

2016-10-25 Thread Riko Ho

Everyone,

I tried to initialize UART on IT8718F and it stopped at 0xD2...
Here's the complete function, any clues ?

Cheers
===
void mainboard_romstage_entry(unsigned long bist)
{
int s3resume = 0, boot_mode = 0;

if (bist == 0)
enable_lapic();

ich7_enable_lpc();
post_code(0xD1);
/* Enable SuperIO PM */
//lpc47m15x_enable_serial(PME_DEV, 0x680);
//lpc47m15x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */
//enable_dev(SERIAL_DEV);
//ite_conf_clkin();//needs a parameter, what is it ?

/*
04:24:31 AM) idwer: 24 or 48 MHz?

(04:25:18 AM) idwer: how do you find out? run superiotool when
having booted with the vendor bios, and look atregister
CR23
 */
//ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24);
ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48);


ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */
//printk(BIOS_DEBUG,"HELLO WORLD FROM COREBOOT BY RIKO HO...\n");
//it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
it8718f_disable_reboot(GPIO_DEV);
/* Set up the console */
console_init();
post_code(0xD2);
printk(BIOS_DEBUG,"HELLO WORLD FROM COREBOOT ...\n");
halt();
post_code(0xD3);



/* Halt if there was a built in self test failure */
report_bist_failure(bist);

if (MCHBAR16(SSKPD) == 0xCAFE) {
printk(BIOS_DEBUG, "soft reset detected.\n");
boot_mode = 1;
}

/* Perform some early chipset initialization required
 * before RAM initialization can work
 */
i945_early_initialization();
post_code(0xD4);
s3resume = southbridge_detect_s3_resume();

/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();

#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
dump_spd_registers();
#endif

sdram_initialize(s3resume ? 2 : boot_mode, NULL);

/* Perform some initialization that must run before stage2 */
early_ich7_init();

/* This should probably go away. Until now it is required
 * and mainboard specific
 */
rcba_config();

/* Chipset Errata! */
fixup_i945_errata();

/* Initialize the internal PCIe links before we go into stage2 */
i945_late_initialization(s3resume);
}

-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] SerialICE question

2016-10-25 Thread Riko Ho

Everyone,

I tried to understand :
https://www.serialice.com/Getting_Started

In my case:
I want to see i946 init sequence,

How can I tap it from vendor BIOS ?

I have one debugging system and the other is debugged system,
how SerialICE works between of them ?

When i946 cold boots then ??

Cheers

-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Microcode.bin question ?

2016-10-25 Thread Riko Ho


Is it "Allow use of binary-only repository" option ?
On 26/10/2016 8:15 AM, David Hendricks wrote:



On Tue, Oct 25, 2016 at 4:29 PM, Riko Ho <mailto:antonius.r...@gmail.com>> wrote:


Hi Martin,

Do you mean the value of CONFIG_USE_BLOBS inside .config file ?


Yes.

What's the option name one 'make menuconfig' ?


Search for it using '/' (like in vi).

--
David Hendricks (dhendrix)
Systems Software Engineer, Google Inc.



-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Microcode.bin question ?

2016-10-25 Thread Riko Ho


Hi Martin,

Do you mean the value of CONFIG_USE_BLOBS inside .config file ?
What's the option name one 'make menuconfig' ?

Cheers
On 26/10/2016 6:45 AM, Martin Roth wrote:

Hi Riko,
  Make sure you have "Allow use of binary-only repository" 
(CONFIG_USE_BLOBS) selected in kconfig.  This is disabled by default 
for people who don't want any blobs in their builds.


I've verified that the file exists in that location.

Martin

On Mon, Oct 24, 2016 at 8:40 PM, Riko Ho <mailto:antonius.r...@gmail.com>> wrote:


Everyone,

Where can I get microcode.bin, and how to patch it to my code ?

I got this when I choose "Device tree" option
No rule to make target
'3rdparty/blobs/cpu/intel/model_6ex/microcode.bin', needed by
'build/cpu_microcode_blob.bin'. Stop.

Cheers

--
coreboot mailing list: coreboot@coreboot.org
<mailto:coreboot@coreboot.org>
https://www.coreboot.org/mailman/listinfo/coreboot
<https://www.coreboot.org/mailman/listinfo/coreboot>




-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] Microcode.bin question ?

2016-10-24 Thread Riko Ho

Everyone,

Where can I get microcode.bin, and how to patch it to my code ?

I got this when I choose "Device tree" option
No rule to make target
'3rdparty/blobs/cpu/intel/model_6ex/microcode.bin', needed by
'build/cpu_microcode_blob.bin'. Stop.

Cheers

-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] POST Code 0x24 and 0x2F

2016-10-23 Thread Riko Ho

Everyone,

I got chat with idwer this noon and
my CPU model : 4
Model name : Intel (R) Pentium (R) 4 CPU 3.00 GHz x 2

I got 0x24 and 0x2F on cache_as_ram_ht.inc ...

so it stopped at before_romstage:

and loop again to
movl $1,%eax,
What do you reckon to find out what wrong with it ?

Have a look on the chat below :

[10:35]  CPU family : 15 x 2
[10:35]  model : 4
[10:35]  model name : Intel (R) Pentium (R) 4 CPU 3.00 GHz x 2
[10:35]  idwer : from here, where do we go ?
[10:38] * piccaruse (~piccar...@h-64-105.a465.priv.bahnhof.se) Quit
(Ping timeout: 256 seconds)
[10:39] * arescorpio (~arescorpi@152.171.91.145) has joined #coreboot
[10:39]  the code stopped here : before_romstage:
[10:39]  post_code(0x2f) ...and return to
[10:39]  post_code(0x24)
[10:39]  movl$1, %eax
[10:40]  around cache memory initialization..
[10:40]  model 4
[10:40]  so model_f4x
[10:40]  yup
[10:41]  I have no idea :(
[10:41]  that's allright...neither do I :(
[10:41]  may be someone else does...
[10:41]  LGA774/Kconfig shows 'select CPU_INTEL_MODEL_F4X'
[10:42]  well can you post your findings to the mailinglist
[10:42]  it's LGA775 ...
[10:42]  this chat ?
[10:42]  ok...not a problem..

Cheers

-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] coreboot 4.5 release notes

2016-10-20 Thread Riko Ho


Congratulation,

Does qemu support i946 and ICH 7 simulation ?
I have *.bin file, can I run on Qemu to see how it runs ? Or it must be 
physically run and tap via SerialICE ?


Cheers
On 21/10/2016 2:21 AM, Mike Banon wrote:

Coreboot 4.5 has been released quietly two days ago
(http://www.coreboot.org/downloads.html) , but we haven't seen the
release notes yet - either at http://blogs.coreboot.org/ or
elsewhere...

According to http://www.coreboot.org/Supported_Motherboards page, so
far the following systems have been successfully tested with this
release:

* Lenovo G505S - http://www.coreboot.org/Supported_Motherboards#lenovo.2Fg505s
* Lenovo X201 - http://www.coreboot.org/Supported_Motherboards#lenovo.2Fx201
* Lenovo X220 - http://www.coreboot.org/Supported_Motherboards#lenovo.2Fx220
* ASUS KFSN4-DRE -
http://www.coreboot.org/Supported_Motherboards#asus.2Fkfsn4-dre
* ASUS KGPE-D16 - http://www.coreboot.org/Supported_Motherboards#asus.2Fkgpe-d16
* GIGABYTE GA-B75M-D3V -
http://www.coreboot.org/Supported_Motherboards#gigabyte.2Fga-b75m-d3v
* ASROCK E350M1 - http://www.coreboot.org/Supported_Motherboards#asrock.2Fe350m1
* Google ( Acer ) C720 Chromebook -
http://www.coreboot.org/Supported_Motherboards#google.2Fpeppy
* Emulation QEMU x86 q35/ich9 -
http://www.coreboot.org/Supported_Motherboards#emulation.2Fqemu-q35

These successful test reports have been submitted after the quoted
Martin Roth's message below. Cheers!

On Thu, Sep 29, 2016 at 6:44 PM, Martin Roth  wrote:


Hi Everyone,
  We're coming up on our next coreboot release.  We'd like to get the
release done around the middle of October, but if there are issues in
flight, we can delay it a bit.  The release will absolutely happen before
end of the month.

If anyone is working on major changes that will affect all of coreboot, I'd
request that they hold off until after the release so we have time to
stabilize before the release.

Please test platforms that you're interested in now, and as we get closer
to the release.  I'll create a list of validated platforms to include in
the release notes, so if you want your favorite platform listed as having
been tested in the release notes, please test it now, and post it to the
board_status tracker.  I'll release updated documentation for running
board_status in the next few days.

We've got a number of outstanding issues right now, both on the coreboot
issue tracker, and in coverity.  Please take a moment to look over these
issues and if there are any in an area that you think you can fix, please
take a swing at them.




--
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] MSI K9A2VM question?

2016-10-19 Thread Riko Ho


Everyone,

Does coreboot support MSI K9A2VM?
It has AMD 780V northbridge and SB700 southbridge,

Spec :
https://www.msi.com/Motherboard/K9A2VMFD.html#hero-specification

I need to find 8 pin SOIC socket for it...

Cheers,

--
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Microcode question ?

2016-10-19 Thread Riko Ho

Ok, it means, I need to use microcode for LGA775 otherwise it will not 
work, please correct me ?

On 20/10/2016 1:51 AM, ron minnich wrote:

On Wed, Oct 19, 2016 at 9:36 AM Vasilief <mailto:vazopa...@gmail.com>> wrote:

On 10/18/2016 10:31 AM, Stefan Reinauer wrote:
    > * Riko Ho mailto:antonius.r...@gmail.com>> [161017 02:18]:
>> Is it ok if I'm not including microcode updates ?
>
> It might, or might not. On the i945/946 it probably is ok. A lot of
> modern CPUs can't boot successfully anymore without loading
microcode.

Most modern ARM, MIPS, and AVR CPUs can.

OK, then, although Stefan's meaning is pretty obvious, we can say it 
this way: For those CPUs that have microcode, many can not boot 
successfully without loading up to date microcode. For those CPUs that 
don't have microcode, this question won't appear in the menuconfig.

Therefore, if you see this question, you have a CPU with microcode. In 
many cases, if you say no, you may see troubles with your hardware. In 
some rare cases the CPU can't even configure memory correctly.

I hope that's sufficiently clear?

ron

-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] Disassemble i946 BIOS

2016-10-19 Thread Riko Ho

Everyone,

I've tested i945 code on i946 board and I can hear tuck tuck on its
buzzard, got FC 00 on serial...an repeat tuck tuck and nothing on serial

I'm thinking on diassembling the code on i946 bios, I've downloaded a copy
on my computer as a *.bin.
and make a copy on another chip W39V040FCPZoriginaly from W39V040FB..
now it's running with W39V040FCPZ (backup chip) I keep the original chip

Does anyone of you have a guide on disassemble this BIOS and retrieve the
init code of
i82946 ?

Cheers
-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] i946GZ test

2016-10-18 Thread Riko Ho

Hello everyone..

 I've put W39F040FCPZ on the board...but I can not see any messages on
serial...
I can hear tuck tuck on motherboard buzzardrepeatedly

command : sudo putty /dev/ttyUSB0 -serial -sercfg 115200,8,n,1,N on the host

What should I do next to debug ?

Cheers
-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] Use native graphic initialization

2016-10-18 Thread Riko Ho


Everyone,

I saw in make menuconfig

*Use native graphic initialization

How can I use it, so I can use my onboard VGA displaying message to LCD 
monitor ?


Cheers

--
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); ?

2016-10-18 Thread Riko Ho

Everyone,
Does this line use port on 0x3F8 ?

Cheers
-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] WY1200LE with coreboot

2016-10-18 Thread Riko Ho

Everyone,

Does coreboot suport WY1200LE? it's using AMD geode, and I can't access its
BIOS...directly to windows and no BIOS key access ..

Anyone has ported it ?

Cheers
-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

2016-10-17 Thread Riko Ho

continuing the chat,
for displaying "Hello world" on serial

#define CLKIN_DEV PNP_DEV(0x2e, IT8718F_GPIO)

void mainboard_romstage_entry(unsigned long bist)
{
ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24);

ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);


How can I write "Hello world !" ? and where ?

Could it be :

ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24);

ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

printk(" HELLO WORLD ! FROM COREBOOT...");
..
-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] coreboot.rom as binary file ?

2016-10-16 Thread Riko Ho


Comparing :
http://ark.intel.com/products/34505/Intel-82945GC-Graphics-and-Memory-Controller
http://ark.intel.com/products/27725/Intel-82946GZ-Graphics-and-Memory-Controller

they have the same jobbut I'm not sure if they have the same init 
code...if I'm lucky, they have the same init code, only I will miss some 
features from 82946GZ if I'm using the code from 82945GC...


How do you reckon ?

On 17/10/2016 8:19 AM, David Hendricks wrote:


On Sun, Oct 16, 2016 at 5:14 PM, Riko Ho <mailto:antonius.r...@gmail.com>> wrote:


That one ?


Yes.



-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] coreboot.rom as binary file ?

2016-10-16 Thread Riko Ho

Ok, is W39V040 FCPZ compatible with W39V040FB ? on my original board is 
FB series...my spare chip is FC series

How can I diassemble the original flash with SerialICE and run it on Qemu ?

I have written onto my FC series chip, but I want to see the original 
one running on qemu, since the chipset I have on coreboot it different,
onboard is intel 82946GZ and on coreboot I'm using intel82945GM, but 
super IO and southbridge are supported by coreboot


So I want to copy / download the original one and simulate it on qemu 
then disassemble northbridge init code and rewrite it for coreboot...



On 17/10/2016 8:19 AM, David Hendricks wrote:


On Sun, Oct 16, 2016 at 5:14 PM, Riko Ho <mailto:antonius.r...@gmail.com>> wrote:


That one ?


Yes.



-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] Diassemble i946GZ ?

2016-10-16 Thread Riko Ho


Everyone..

What's the process on diassembling i946GZ ? How can I do that from my 
original motherboard ? so I can see the init process of this northbridge ?


How can I use SerialICE doing it ? I want to know the process 
downloading the code from the original motherboard, and run it on Qemu ? 
and capture the init process for northbridge ?


Does anyone have the reference ?

Thanks


--
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

2016-10-16 Thread Riko Ho


Will coreboot run on basic mode without "microcode" ?
I've read about it :
http://inertiawar.com/microcode/

On 16/10/2016 1:10 PM, Antonius Riko wrote:

Is that the one ?
-rw-rw-r--   1 bianchi bianchi 524288 Oct 16 13:04 coreboot.rom

can it be uploaded as *.hex or *.bin to my flash ? my flash is W39V040FB

inside /coreboot/build/




--
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] coreboot.rom as binary file ?

2016-10-16 Thread Riko Ho

Ok, I can burn it already as *.binnow what do I expect to run from 
serial ? what 's the baud speed ?


On 17/10/2016 4:23 AM, Sergej Ivanov wrote:


Yes. coreboot.rom is a simple binary file (not a .hex file), so you 
can flash it like a .bin file.


16.10.2016 9:14 пользователь "Antonius Riko" > написал:


Everyone,

Can I burn coreboot.rom as a *.bin file on flash programmer ? My
flash programmer is Genius G540

Cheers

--
coreboot mailing list: coreboot@coreboot.org

https://www.coreboot.org/mailman/listinfo/coreboot




-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

2016-10-15 Thread Riko Ho


So I must do rm .config and make menu config then don't select :

 CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM , where is that option, may be I did, I 
forget already...
Can you read it from .config ?

Anyway, what's the safe mode / default for make menuconfig ? What's the payload 
option should I make ?


On 15/10/2016 9:12 PM, Nico Huber wrote


On 15.10.2016 14:57, Antonius Riko wrote:

I did rm .config and did make again :

bianchi@ubuntu:~/coreboot$ make clean
bianchi@ubuntu:~/coreboot$ make
#
# configuration written to /home/bianchi/coreboot/.config
#
 HOSTCC util/sconfig/lex.yy.o
 HOSTCC util/sconfig/sconfig.tab.o
 HOSTCC util/sconfig/main.o
 HOSTCC util/sconfig/sconfig (link)
 SCONFIGmainboard/intel/i946gz/devicetree.cb
 HOSTCC nvramtool/cli/nvramtool.o
 HOSTCC nvramtool/cli/opts.o
 HOSTCC nvramtool/cmos_lowlevel.o
 HOSTCC nvramtool/cmos_ops.o
 HOSTCC nvramtool/common.o
 HOSTCC nvramtool/compute_ip_checksum.o
 HOSTCC nvramtool/hexdump.o
 HOSTCC nvramtool/input_file.o
 HOSTCC nvramtool/layout.o
 HOSTCC nvramtool/accessors/layout-common.o
 HOSTCC nvramtool/accessors/layout-text.o
 HOSTCC nvramtool/accessors/layout-bin.o
 HOSTCC nvramtool/lbtable.o
 HOSTCC nvramtool/reg_expr.o
 HOSTCC nvramtool/cbfs.o
 HOSTCC nvramtool/accessors/cmos-mem.o
 HOSTCC nvramtool/nvramtool (link)
 OPTION option_table.h
 CC bootblock/mainboard/intel/i946gz/static.o
 CC bootblock/arch/x86/boot.o
 GENgenerated/bootblock.ld
 CP bootblock/arch/x86/bootblock.ld
 HOSTCC util/romcc/romcc (this may take a while)
 ROMCC  generated/bootblock.inc
 CC bootblock/arch/x86/bootblock_romcc.o
 CC bootblock/arch/x86/cpu_common.o
 GENbuild.h
 CC bootblock/arch/x86/id.o
 CC bootblock/arch/x86/memcpy.o
 CC bootblock/arch/x86/memset.o
 CC bootblock/arch/x86/mmap_boot.o
 CC bootblock/arch/x86/timestamp.o
 CC bootblock/arch/x86/walkcbfs.o
 CC bootblock/commonlib/cbfs.o
 CC bootblock/commonlib/lz4_wrapper.o
 CC bootblock/commonlib/mem_pool.o
 CC bootblock/commonlib/region.o
 CC bootblock/console/die.o
 CC bootblock/console/post.o
 CC bootblock/cpu/x86/lapic/boot_cpu.o
 CC bootblock/cpu/x86/mtrr/earlymtrr.o
 CC bootblock/device/device_simple.o
 CC bootblock/device/i2c.o
 CC bootblock/drivers/uart/uart8250io.o
 CC bootblock/drivers/uart/util.o
 CC bootblock/lib/boot_device.o
 CC bootblock/lib/bootmode.o
 HOSTCC cbfstool/fmaptool.o
 HOSTCC cbfstool/cbfs_sections.o
 HOSTCC cbfstool/fmap_from_fmd.o
 HOSTCC cbfstool/fmd.o
 HOSTCC cbfstool/fmd_parser.o
 HOSTCC cbfstool/fmd_scanner.o
 HOSTCC cbfstool/fmap.o
 HOSTCC cbfstool/kv_pair.o
 HOSTCC cbfstool/valstr.o
 HOSTCC cbfstool/fmaptool (link)
 FMAP   build/util/cbfstool/fmaptool -h build/fmap_config.h
build/fmap.fmd build/fmap.fmap
SUCCESS: Wrote 182 bytes to file 'build/fmap.fmap' (and generated header)
The sections containing CBFSes are: COREBOOT
 CC bootblock/lib/cbfs.o
 CC bootblock/lib/cbmem_console.o
 CC bootblock/lib/delay.o
 CC bootblock/lib/fmap.o
 CC bootblock/lib/gcc.o
 CC bootblock/lib/halt.o
 CC bootblock/lib/hexdump.o
 CC bootblock/lib/libgcc.o
 CC bootblock/lib/memchr.o
 CC bootblock/lib/memcmp.o
 CC bootblock/lib/prog_loaders.o
 CC bootblock/lib/prog_ops.o
 CC bootblock/lib/timestamp.o
 CC bootblock/lib/version.o
 CC bootblock/vboot/bootmode.o
 LINK   cbfs/fallback/bootblock.debug
 OBJCOPYcbfs/fallback/bootblock.elf
 OBJCOPYbootblock.raw.bin
 CC romstage/mainboard/intel/i946gz/static.o
 CC romstage/arch/x86/acpi_s3.o
 GENgenerated/assembly.inc
 CC romstage/arch/x86/assembly_entry.o
 CC romstage/arch/x86/boot.o
 CC romstage/arch/x86/cbfs_and_run.o
 CC romstage/arch/x86/cbmem.o
 CC romstage/arch/x86/cpu_common.o
 CC romstage/arch/x86/memcpy.o
 CP romstage/arch/x86/memlayout.ld
 CC romstage/arch/x86/memmove.o
 CC romstage/arch/x86/memset.o
 CC romstage/arch/x86/mmap_boot.o
 CC romstage/arch/x86/postcar_loader.o
 CC romstage/arch/x86/timestamp.o
 CC romstage/commonlib/cbfs.o
 CC romstage/commonlib/lz4_wrapper.o
 CC romstage/commonlib/mem_pool.o
 CC romstage/commonlib/region.o

39 matches

Mail list logo