Re: [coreboot] Intel graphics drivers: now with firmware blobs.
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 09/06/15 02:12, The Gluglug wrote: > Not sure if anyone has seen this, so I thought I'd drop it here: > https://01.org/zh/linuxgraphics/intel-linux-graphics-firmwares > http://lists.freedesktop.org/archives/intel-gfx/2015-June/068167.html -BEGIN PGP SIGNATURE- Version: GnuPG v1 iQEcBAEBAgAGBQJVds4kAAoJEP9Ft0z50c+U8wAIAJIkzUN+t5uy/yBUgjW15pX1 CA6i7gZH+2A+RNcniqzjjU+AHtnGoPu2c+IUX72zp2YnX85xngNJ4fN1IvY8nI7/ fQuXFwjHFzkeEaf+GB+Wy/a8dpUysAnCUH0pCeXKti420X2mRjhhdTXD+/pCnYZq F/2HbCNnunvdR4fO7uHxuto4jqZE98ueBQZ30O02MCrZ5WsrbWGHb1ytdHBD2zGU KAiuq3sAmErmhiPEMtuWm74qpoHs0B0h7S1wrywFbm3snI/3q1S3qOCjU4DJv3ri ZanfORcFmLAIrQyttw9Vi4P0Wa3Aipc+kLZjZIEPnuUtLtF7x5ewWmWmzhR+y78= =oLV0 -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Intel graphics drivers: now with firmware blobs.
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Not sure if anyone has seen this, so I thought I'd drop it here: https://01.org/zh/linuxgraphics/intel-linux-graphics-firmwares -BEGIN PGP SIGNATURE- Version: GnuPG v1 iQEcBAEBAgAGBQJVdj2XAAoJEP9Ft0z50c+UCssH/06Y2ahzQI50feWmOZudAW7N EpPTTvcXUrPXG5xv7LOEjPpqZNToNuVH7o5AHZ4G8v4VG6ftu8Jkcm+O5ZsxM+ys ExC5VAqMCVDTASuS2VHZxCIhtQVM3H7Mj8zfJxuMyiiHUoOFACF1dWCAxVCYf42L VRrj6tmFapNVq4Pfk9EpAqYywpP8wzdpQSH/dX8WayT9RskU8WMVirMYo0gY5Ecf lYtC+IYD6EJbokqWfA0F/ptTs5OsbSpH+2XP5tCXXFFt+62O3nO8JLGTpL8U5CwY N2zJlPKXcHUwcR3SYgW7OYu8zbBX16X0VFhFFJhAaTRCloHdY0GjW1T7XZfJQSo= =XpaA -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] grub2 coreboot
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Hi. Check the build system in libreboot. While you might not necessarily use libreboot, the build system there automates the downloading, patching and building of GRUB. There is also a script that installs build dependencies and so on (for Arch/Parabola or Debian/Ubuntu/Trisquel, but you could adapt it for Fedora). See: resources/scripts/helpers/ resources/utilities/grub-assemble/ git clone http://libreboot.org/libreboot.git On 25/05/15 16:07, sibu wrote: > Greetings, > > I a attempting to build coreboot with grub2 payload. The host runs > fedora linux. > > I used the Kconfig menu to select GRUB2 as coreboot payload and > run make crossgcc succcesfully.. On runing the next etep -make > grub2 from git is downloadedbut the build fails on the > ./configure of the downloaded grub2 as follows:- > > ### configure error qemu powerpc-ieee1275 coreboot and > longson ports need unifonts, ### I checked the hosts' > installation and I have unicode fonts installed. I changed host > with the same fesult. > > Help would be appreciated > > sincerely Sibu > > incidently when running ./configure --with-platform=coreboot. > grub-2.02beta2 failed also though the older Grub-2.00 built > succesfully. I am unclear if the latter is too old for using as > coreboot payload in the corrent instance and if not how to go > abot embedding it in the downloaded coreboot distribution from > the current git repo. > -BEGIN PGP SIGNATURE- Version: GnuPG v1 iQEcBAEBAgAGBQJVZLaQAAoJEP9Ft0z50c+Ujj8IAMA9L/+SPm/PQ5K5ULo2yQtQ 9PIx50IwlbS/VWDoiVeSZnD3U3U18KjOUQWetsZmTQg7XpaI+/he9t9/Y/3E8XlE fer2aU9GF3V+98/2iahvx0LpQKa+nJ+0XczwoZf19//0yVmh5SGqgI6hwCQqEJyU H8hhGV2fdR2uIL726UrDn83Pd2MVXBpmPK1TM72qIdp7OqCoqXgC9HsDz1Pm/87n Icp7EnrYAJI8ZngSgafqKYagsVbSJHQEzVEKEKC1md8f0nyyVqBtEiuuXt+4bNM7 Em2WO+uNWeX8QHmYTNicTlLltb5yketxCFY2c7XCaDsuQg0s1MpvypH6i1PVVV4= =bADy -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [RFC] Preparing a crowdfunding campaign for the ASUS KGPE-D16
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 17/05/15 15:11, Paul Menzel wrote: > Dear coreboot folks, > > > Timothy, congratulations again on making a coreboot port for the > ASUS KGPE-D16 and therefore completing your third coreboot port! > That’s really amazing! > > > Am Mittwoch, den 29.04.2015, 22:46 +0100 schrieb The Gluglug: >> You should crowd-fund the $35,000 figure, there are lots of >> people who will be interested in this. I personally will chip in, >> and I'd ask others to as well. > > I am thinking about organizing the crowdfunding campaign to raise > the money. > > If somebody else wants to do it, please speak up! > > As this is more or less a donation by the backers, the process > should be as open and transparent as possible. That’s why I am > sharing the following information publicly. > > 1. Giant Monkey Software Engineering [1], the German company I work > for, would be the organizing entity. As a company with five > employees and a GmbH it might have enough credibility so that > people would pledge/give their money to Giant Monkey compared to a > private person or company run by a single person. Giant Monkey also > has some PR/campaign knowledge, but most importantly knows a lot of > people in the marketing sector. > > 2. After receiving the money, Giant Monkey would contract Raptor > Engineering. > > 3. I’d like to have the domain campaign.coreboot.org redirect to > the campaign page at the crowdfunding platform or set up a simple > Web site there. > > 4. git-annex’ second funding was done by itself with PayPal. That > saves the 4 % fee most other crowdfunding platforms charge. > > Using a crowdfunding platform might be easier though, as they have > experience and also provide a big community of possible backers. > > Currently I’m thinking about Indiegogo, which Jolla also used to > fund the Jolla Tablet. I heard, Kickstarter is also great with a > big network. > > 5. I plan to raise 100.000 € (around $110.000) to upstream, that > includes *paid review* and running the campaign, the whole port. > (I’ll continue to use Euros.) More money would be used for stretch > goals. > > ?) 4.000 € Indiegogo fees ?) 35.000 € for Raptor Engineering for > upstreaming for basic port ?) 15.000 € for Raptor Engineering for > implementing support for S2R (S3) ?) 10.000 € for code review > (inclusively hardware) (just an estimate) ?) 2.000 € for Gluglug > to release images (I have not talked to Francis yet.) ?) 10.000 € > campaign goodies (cf. 7.) ?) 4.000 € taxes (probably a lot more, > depends if given money counts as donation) ?) 20.000 € Giant Monkey > for running the campaign (Web site, press, marketing, videos, mile > stone tasks (see below), …) > > (Stretch goal) ?) 15.000 € for Raptor Engineering for upstreaming > Family 15h support for the board > > 6. I’d start with a minimal Web site and campaign platform page and > see how big the momentum alone through the coreboot community is. > If we get 10.000 € in a week, I’d fully step in with a professional > campaign. Otherwise I’d stop the campaign. > > 7. As a thank you for backers, I think of a payload included in > the distributed coreboot based firmware image, reading a text file > from CBFS with the names of the backers and displaying it. (Or a > simple splash screen.) Of course just for those wanting it. Big > backers (25.000 €) get a board with one CPU and RAM and coreboot > preinstalled; medium backers (10.000 €) get some BLOB free laptop > for example (Rockchip Chromebook or some Lenovo board). flash ROM > chips are sent to backers donating 25 €. > > 8. Milestone tasks: At certain mile stones (probably each 10.000 > €), I’d promise some more tasks to improve coreboot or the port > (see the 5.000 € steps in the top). Possible are also SSL > certificates for coreboot infrastructure, promising to run a 32-bit > userspace build host, redesigning the Web site, implementing CBMEM > time stamp support in SeaBIOS and GRUB, supporting Google’s > verified boot, …. > > 9. Reasons for contributing > > ?) server, cluster companies; administrators Do hosting/server > companies besides coreinfo [5] with AMD based offers exist? That > means, is there a chance of getting big contributions? > > What about the Free Software Foundation (FSF), FSF Europe (FSFE), > Electronic Frontier Foundation (EFF)? What about governments? > > ?) free software enthusiasts I hope with the FSF, FSFE and EFF some > big organizations will be able to motivate a lot of people to > donate. ?) private “normal” people This is my main problem. > Alexandru Gagniuc uses(?)/used(?) the board as a workstation, but > the normal user will nev
Re: [coreboot] coreboot ported to the ASUS KGPE-D16 (Libreboot: blobless, fully functional!)
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 29/04/15 22:46, The Gluglug wrote: > You should crowd-fund the $35,000 figure, there are lots of people > who will be interested in this. I personally will chip in, and I'd > ask others to as well. > What about simply pushing the code as-is (make your non-upstream tree publicly available for people to git-clone), and let the community upstream it in their own time? -BEGIN PGP SIGNATURE- Version: GnuPG v1 iQEcBAEBAgAGBQJVQVOhAAoJEP9Ft0z50c+UbNYH/0+haygy3GNs2qF9wEcV3ws7 RZZPLBT5XZ7++QUS0vwaOGBbFCdTcWue9QdRJ3G+007+r4syNV0CMOn1XHFBgKq7 OhngpNvwN37p6y87vrOdMlsLDOHbj17AZyPiUJbncyCDD2Fb12QNsSHgmSIrk6QI h1ZqhS8l60Nyxf10ym/TDqjd4WvH7PIx74couSqFJxKiYBu4p4akM3BxTEzJAAzU LaZDR1wLwxeEi4iiN9IWjG37rfsxtM1W0Lu+HnvsHzCa09YjX50G7TkWJjRRaWGo QHKg/CMEPA3kwbVTcCHSLMeuUOe2Sp1p0VEktpTnYr3U4C0eQ1p7ZrOTM0lkdlE= =p0kv -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] coreboot ported to the ASUS KGPE-D16 (Libreboot: blobless, fully functional!)
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 You should crowd-fund the $35,000 figure, there are lots of people who will be interested in this. I personally will chip in, and I'd ask others to as well. -BEGIN PGP SIGNATURE- Version: GnuPG v1 iQEcBAEBAgAGBQJVQVE1AAoJEP9Ft0z50c+UGrAIALFkmjysSsczVYKS1JDoOKuo PEu5dpWjUijjK1Bd/mCNfpzV/30KXO+V+gqhV4uIse0zj0zMDfGq5uaahyRIZimT p1c7o3+SXdBa5cvb2UjmLItbGJNM3uvs+v0IrDYwenR9EeMDaV2oOeDCTzojq2Vf drDq5Lt/WUwxC0XYUo25ZrGcaXJ5q1ni5e6SINw9TirW+XMoE6ye65/yZ923SFnK D/eKQgYd9+oOCM7CJUCk4VXAaMHcgd6Wi08e5fsCeCnhQos5x7pvTYcpp4wqMLu/ i23SnAnM9JUAc3pYJ/DsAWoB46QeNsWk01fqp6lx8gvs+MBnm1WpCKKmEROsxB4= =RIe1 -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] force https on review.coreboot.org
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Hi Alexander, On 16/04/15 14:57, Alexander Couzens wrote: > Hi, > > review isn't forcing https. Can we please do this? Otherwise > stealing cookies is posibble. Review supports https. There is atm > an CACert based certificate and CaCert isn't included in the > default root keychain. Thus a normal user will shown a big fat > warning, not to connect to review.coreboot.org, because the > certificate is unknown and untrusted. I don't have a problem with > that and I like CaCert. But if CaCert is the reason not enabling > https-only, than let us change to StartSSL or someother SSL > authority. > > Best lynxis > > PS. Same issue on www.coreboot.org, but stealing review is much > more worse than stealing wiki cookies. PPS. Please write a +1 if > you're supporting this opinion. > > > "Let's Encrypt" is interesting; https://letsencrypt.org/ It's not ready yet, but it's supposed to be an "automated" (most likely gratis) certificate authority, and they are working hard to get it recognized to work around the issue where the user would otherwise get warnings in their browser. Run by the EFF. Definitely something to look into. I'm waiting for it to become available, so that I can start using it on my sites/services. Seth Schoen did a talk about it recently, watch from 59 minutes in: http://mtjm.eu/releases/lp2015/lp-123-1426949592.ogv (there were slides during the talk, but they didn't capture them) Regards, Francis Rowe. -BEGIN PGP SIGNATURE- Version: GnuPG v1 iQEcBAEBAgAGBQJVME08AAoJEP9Ft0z50c+UaoMH/Rk/M+z+LIEtWISe88fi1pxL 0Trp1TRQGs8ggMZs0tYqpwczkSYWf5HiMTfA85zGI0jpHHNhDBSLZnO62N2nq2Dl zSqMGnWQgfRpdmtgCrU9ctfGbqvONjWO3DlA4zDGqUXAelQe7NKF6OkUijCln+DL 9GucY9x+fVNo4TaokJz9zxVF+Y10flFwk+DTMz7FoIXgaJhKJ5QFfqX7ybT9U7P1 53Uci5J9qQMio1IFuPcVxqpchYvaEhVF2NPEXtHCCQG0izGrpjMvFwbrh/fXWNfp KCxoQyEfoB98lFBjkBj0uXlfAJsOI8+t02P1JN+hyxpnGeoWk30rmNGAvwHAY8M= =Vj0R -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Kernel hang issue "All ACPI Tables successfully acquired"
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 X60/T60 couldn't boot on 3.19/higher without acpi=off. See: https://bugzilla.kernel.org/show_bug.cgi?id=93171 This patch fixed it: https://bugzilla.kernel.org/show_bug.cgi?id=93171#c25 And it's being merged: https://bugzilla.kernel.org/show_bug.cgi?id=93171#c32 That probably won't help you, so you'll have to open your own bug report. I used Qemu myself very recently, but I haven't tested GNU/Linux much on it (I use it mostly for testing payloads). On 15/04/15 07:37, Ajoy Das wrote: > Its qemu-system-i386. > > On Tue, Apr 14, 2015 at 11:17 PM, The Gluglug > wrote: > > what computer is this? > > On 14/04/15 03:58, Ajoy Das wrote: >>>> Hi >>>> >>>> I am running coreboot on qemu with the following sequence. >>>> >>>> coreboot -> seabios -> GRUB -> kernel. >>>> >>>> The kernel booting hangs at *All ACPI Tables successfully >>>> acquired* >>>> >>>> coreboot-4.0 kernel 3.19 >>>> >>>> when I pass acpi=off to the kernel command line parameter >>>> the kernel boots fine in this scenario. >>>> >>>> >>>> Is there any specific coreboot option is there to be enabled >>>> for successful booting. or anyone knows of this issue. >>>> >>>> please help >>>> >>>> >>>> Thanks >>>> >>>> >>>> >> > > > -BEGIN PGP SIGNATURE- Version: GnuPG v1 iQEcBAEBAgAGBQJVLhpJAAoJEP9Ft0z50c+UI9gH/2WwcYzlgaWmc4TuO09BPVdV 3saFE27F1iClAe9p3MqcziEWySGjaL6p6Y8YhLJIKHF8N0ZyghdratcwLzL68LpX V5HOhw84d/ra24rq1ZMMC7hf6GsUlqgvrefIiVCuApdlPWdDoq5j9X3lEqgC+3Yy jNHh8hLQXbfmV6wJ5ewY+36VubtJ0qMhRPHMcUNrrZozbPBKD+jyZrdw6T/mLguq G2ZYWr8ruWNPH6bi5tBEN6xlmh58sC1O16sb8cUkB8NX5OYAhJ3CQEnGwVF6xvZY B9lz0iQsfqokRCmqUe5vDiq4n8HobbF9DbSu41+oMKOYPMdSDi75Kb+FsZx1BH4= =LesB -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] coreboot candidate: Dell Latitude E6400
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Hi, This is GM45, like the X200 which is supported in coreboot (and libreboot). The issue: DDR2 RAM (raminit in coreboot for GM45 only supports DDR3, doesn't it?) and EC needs some work. There are a lot of these laptops available online, so I think it's a good porting target for coreboot. It would also be an instant libreboot port, once in coreboot, being GM45. What does the community think about this? Worth it? Regards, Francis Rowe. -BEGIN PGP SIGNATURE- Version: GnuPG v1 iQEcBAEBAgAGBQJVLVNyAAoJEP9Ft0z50c+UZnIH/0BLbeaqLRXq70huwdgjq2H1 mpB9rrfJ4cxUTd5rvWMNe0NmNsrhBdv2BpZ5bryLZEEa21qbDfP7FsZA0FCuXHdL 4aFk5nsBk1MrCD+6K0yeJrevPviVFEuLr3rTrs9JusKf44AcewTbcLH4zmUJ9VXB eRnVBNz1N7QdahD/ML5aEKNY2EEQxD11i+fNjYBYO1LsHnbJfEsxQGbDC1olSmc1 34ZPhgq8lkYpWodUbYtI1LPvMLcbQYuFC8ySwRhP+ml+zDldqJk5Pcg/fq8DNQiS 4ZDxUluCWXynD1vDFH7KRrtI5aA2t1YFXkbYi3SX3asRl30V+LZeufrvTQyeapc= =OpCs -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Kernel hang issue "All ACPI Tables successfully acquired"
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 what computer is this? On 14/04/15 03:58, Ajoy Das wrote: > Hi > > I am running coreboot on qemu with the following sequence. > > coreboot -> seabios -> GRUB -> kernel. > > The kernel booting hangs at *All ACPI Tables successfully > acquired* > > coreboot-4.0 kernel 3.19 > > when I pass acpi=off to the kernel command line parameter the > kernel boots fine in this scenario. > > > Is there any specific coreboot option is there to be enabled for > successful booting. or anyone knows of this issue. > > please help > > > Thanks > > > -BEGIN PGP SIGNATURE- Version: GnuPG v1 iQEcBAEBAgAGBQJVLVK0AAoJEP9Ft0z50c+U9hEH/1ioHK9/hZCrKZqDYc+4rPCR 2jcPsaq2OPMX8zq5o6ljP3+Z5gHPyF8hDIMFyJHk5hi19vvxbVmPXMy9dTj1y8rs WGdAqHx/xbbdHh/CWXJ+JzgdZryfD7FN9L5RAXzVBMDjjRouUaI9eTObspSstRLD /LjlaAZdfWWK9doHPCJoeTZ7dJGE6e4GahxDJzCX0sJot2NtiukaTn6cbvPgt47V kStrxyVXxIJykZoxFI5+M1qo38IB6h6oZFOeUpL3MQXQxHnh0Ckmz3F30ySdMyir 7lN64p8utc4kroZtbmSlQVLpHbR7fpcu1opHWPwz0XTqhnwK1G1Oa0i0MAxvbFA= =L/lM -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] GRUB2 is too big as a payload in ThinkPad X201
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 30/03/15 12:04, Alexandru Gagniuc via coreboot wrote: > They probably already did, but didn't document it. That sounds about right. -BEGIN PGP SIGNATURE- Version: GnuPG v1 iQEcBAEBAgAGBQJVKv0CAAoJEP9Ft0z50c+UflsH/RdshBMg5mTd6dSXLQo4Jbc9 ocOoAYTfgJbBfRGn73c2pseA5ZK/B7sjFzP1c8GHfQ8Ufofd+13vWofWs1biyWI/ +xhbQD14lO42LNrorH9C1rO+cveFTq4mrV6d+c8/SQiXW8lyVHIfe8WBv8QsFsIs 5vOzsvhL99QujF/dmCs2gJSeP5Es+zgfxlVc7cxQKRWxn9DHndqAfVdQhnY4R4VP h4eh/uEAjeUMxqpp762b1z0DntCc5j7lh/efmbFsGekSdVukLs4oe/98EB9HjoDo wz4wfV7atJ+0PnDrlSGapQqz/nvtUB1FP+uww8ikCERA81X+VWepnGw9MpG4sFc= =o4VO -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] GRUB 2 is a great payload!
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 uh I mean grub.cfg in memdisk inside grub.elf, which loads grub.cfg from CBFS "grub.elf in cbfs" replace with "grub.cfg in cbfs" etc it's late On 13/04/15 00:27, The Gluglug wrote: > (also, that puts a grub.elf in memdisk inside the grub.elf, which > just jumps to grub.elf in CBFS) > > So just put a grub.elf in cbfs root. ROM images in libreboot have > a grub.cfg that you can use as a template (just extract the > grub.cfg) > > Another nice thing, it puts lots of keyboard layouts in the > grub.elf (it even has Dvorak support) > > On 13/04/15 00:23, The Gluglug wrote: > > >>> I'm not geek enough to build GRUB2. Last time I did it, I was >>> telepathically controlled by Vladimir via IRC. > > >> Use the libreboot build system, it basically automates >> everything. Just use GRUB from it: > >> ./download all install GRUB build dependencies ./build module >> grub > >> Then cd to resources/utilities/grub-assemble/ > >> There are files in there with the list of modules used. Then run >> the "gen.sh" script in there to generate a grub.elf file. > > -BEGIN PGP SIGNATURE- Version: GnuPG v1 iQEcBAEBAgAGBQJVKv/yAAoJEP9Ft0z50c+UpbMH/i0ghrIHY3d/Naz1e76UxoYO vnmMKGSdlcUGZJBp1txha3yDVm2ZYGnTE8wUimX6L1S/E1pn6bEvwbJiaAJY8rCZ +i8BNhVa4/P6iWz/WNXsazIRuGUrhmqO+Ia67LpmDYyLFZ+F5J1YWKxKilCHoU+W ZROHkbwdo9NW3oYxkTtOycoNeQ1RraAuPt0ONV0u90On+sN18KpzXkLZCqUjyP2o IPGtGtT3dh6Ll1aqWuZAl0lBa1/Ek1Vz/32nZTUv+VLXlpQxPBdcVBh1MJaHBW6a aI3At864rpL9q6mjdqlOn0XHTAB52eK0UFotocInDiQRrVp6tYHTHcqzvPTSl3c= =k7Ap -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] GRUB 2 is a great payload!
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 (also, that puts a grub.elf in memdisk inside the grub.elf, which just jumps to grub.elf in CBFS) So just put a grub.elf in cbfs root. ROM images in libreboot have a grub.cfg that you can use as a template (just extract the grub.cfg) Another nice thing, it puts lots of keyboard layouts in the grub.elf (it even has Dvorak support) On 13/04/15 00:23, The Gluglug wrote: > > >> I'm not geek enough to build GRUB2. Last time I did it, I was >> telepathically controlled by Vladimir via IRC. > > > Use the libreboot build system, it basically automates everything. > Just use GRUB from it: > > ./download all install GRUB build dependencies ./build module grub > > Then cd to resources/utilities/grub-assemble/ > > There are files in there with the list of modules used. Then run > the "gen.sh" script in there to generate a grub.elf file. > -BEGIN PGP SIGNATURE- Version: GnuPG v1 iQEcBAEBAgAGBQJVKv92AAoJEP9Ft0z50c+U4UQIAJd8EGQcTXTIP/6JjL7/ofTM c5SJzPzURd2s9y9HmaI+5QWt13luONWftvBVjhJUIkqfxNRKf5vDgnVyCtlHv8EG WJH+Bm7SgXNC+pRskRJWW19ZH34HL+dEXzm1D92FxxLRVgxBAMkYSQsIpF6Sx1FF eSZnJPlIP5fB0jC+4aTEQpF9lONpHJ98ULz2zM95q90IEMkkji/pJNyLocV1YGaI ie43BPmOKs7z5q+nHsvDH245O9m6MZ5EhTWmnKro82CK5OCuPt7FXfoWhq2lsDSB 4h78EnhYLv3/IrNmu8eh+Ezb0hjzua5Td38i0pK6S9yqbhIeR/ivJB0TDsk9nDQ= =yUFe -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] GRUB 2 is a great payload!
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 > I'm not geek enough to build GRUB2. Last time I did it, I was > telepathically controlled by Vladimir via IRC. > Use the libreboot build system, it basically automates everything. Just use GRUB from it: ./download all install GRUB build dependencies ./build module grub Then cd to resources/utilities/grub-assemble/ There are files in there with the list of modules used. Then run the "gen.sh" script in there to generate a grub.elf file. -BEGIN PGP SIGNATURE- Version: GnuPG v1 iQEcBAEBAgAGBQJVKv52AAoJEP9Ft0z50c+UcoQIAL1IuCRilvhY2iAq3qUonHAA wcMBVhAHkzSEl1Z+yHP8ghM+spqnzNpQLqqr0csFBN8EC3SqVKjU8qRD8TCIKWt1 SPTNPBwl4XKZvdeu1yfH3dQENlK/AFE06mJk2OxJctR9s9rAc31cg9qvkhAN5GfD Udir5H0hh562L/e5q4lmBCTw8ZUeoyTlHKRCpIsGJpVOhaKddN5xqCRw4HolDbdH 4YjNLiKP5RdJ2Lj0I0yWQvZR4G2WuV8a/ILgghkVH21HEjOKzIf2F5obr0HP/Bd3 Sx86HiuEfkXPaaPxtqIJ+l2uegZyYSOllawDIZtjFnHsCcGBQoTlyWRAb42YKeM= =tLpn -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] BB-xM spi
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Has anyone here used the BB-xM for SPI flashing before? -BEGIN PGP SIGNATURE- Version: GnuPG v1 iQEcBAEBAgAGBQJU2t53AAoJEP9Ft0z50c+Ul2kIAJ40A8ovTgtxCOmg1wpprOOy Xp8RbAiaGeBzfGz9vVGIhbqNmz3TGDWbldNSn1VFe9ZJA51cyWNDl9oKxar4kr8o voE0h1p41KSgSHzZNM48MQEy1CN24HOTThlAioUiGqQP+z5clByhabZNlKppBqRl 5Mj/BJx7++dr4rZWWCHf5aIcgvLSL/8lG7rYAxtnoQ5sVv0IqjSqRfeT+5Nemj9N ag01DxU8Et6xCmzqbvReMjC8AiQDXd+CgbXeTRVBlfL9gP537z+dGZJQoRa0Zlh/ 3No54ya9+yTmy2eYzq1kDmfiqL87YIgHjMiD42u6r6jPsVzwR9Puk8GfkRHBBnM= =QJtr -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] T410S support
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Hi, I found this patch on http://review.coreboot.org/#/c/7975/ but I was surprised to see a lack of testers. Is there someone out there with this machine that would still be willing to test it? Regards, Francis Rowe. -BEGIN PGP SIGNATURE- Version: GnuPG v1 iQEcBAEBAgAGBQJUwquyAAoJEP9Ft0z50c+Uk+kH/i6EYfGSRVO5dgyJAYgBnQYz mIPDhgd3mcXdeqcKAFQvubZ9j9/rDeMxM+SrmJWybIE8WtrwoxkO6vFxl6JivzYp gH1bMgl9YVSZZZxvvZmHJzyBFa2VocApSztPfC9PkIdvEDfH4CnHGkO6ulGfVVKC ESr6+ZP8jK3uN6dtLJqX0NcEhuxw7ZRt5nUtIWxpuwjSaavxYfuFhw6NCWfsI6ay nzSWSP6P7jG5WSacVAvxqQfraMcSuPu0q3y+kIhVxspOqKpWmwsasGtgZu777zy6 thGgtHbJPhYULLfZcizWIwJ1MAXGzB8XVz6VVaV0DoYPh3WEIBkviDg89iDC7MY= =GwaO -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] text-mode graphics on gm45
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 When text-mode graphics (disable "Keep VESA Framebuffer") is selected, backlight turns on at payload stage (GRUB tested) but no graphics are shown (black screen). Graphics do work after payload stage, when booting a GNU/Linux distribution. (tested on X200). I attempted a fix, but still couldn't get it to work (non-working patch here: http://review.coreboot.org/#/c/8018/) What am I doing wrong? -BEGIN PGP SIGNATURE- Version: GnuPG v1 iQEcBAEBAgAGBQJUpD2BAAoJEP9Ft0z50c+U4AQIAI81Dpfe1zeVAbA0uZbmGrsV cBEzEmZyoOHNUQd5AsYtPs5QVw1DJ9Fu4Q9td/AsWAOB6DeddY6eFfHFUXXPgsc6 /48M5KhXsEPHEj6xdCeAiCr05PwNAdKEvcfPnkGLO5n+EvD1sxZFgoXTPCwJ6TYy t2FmltaMlZsnmCYXD5sisA3nArEgrViXuH03bBYTh6VTE3RKaUoLWdlvuIIPfx6F /sJJhJH+5p52oAsvt0usiZBVOwSuG1AUPcFtYWfSBXp+4e35jwajhzfw4KmWtR+Q WbeytLAWMTDUXvjGpyaQKwSwUqDFmWr6VjPS5x8/flH9H49v24FSVSQEKu+ijNA= =Q2Pa -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] roda rk9
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 disregard. someone reached out on IRC. thanks! On 02/12/14 09:28, The Gluglug wrote: > Hi, > > Does anyone here have this board? If so, please contact me > off-list (ME related work); I need the 4K descriptor region from a > factory.bin dump. > > Regards, Francis Rowe. > -BEGIN PGP SIGNATURE- Version: GnuPG v1 iQEcBAEBAgAGBQJUfYmvAAoJEP9Ft0z50c+UpSsIAMVxEUlAPfT7Xp/B8GKi8Nms qulGLGy3N7NOC2u/q9IGdSIkYlRjrfsPrPgduunl7MzW9rxcWTohmjQebMOhehIK oxIwVdsZ3hOldtK9f8K33iS7UeWaM58a6b4K45hJiNfb8uB9qipduztJkrXo0j3a gDKEmj+FOrcWKuwxTS9K0A9faTvcapNyQGZgfq3Tsi/x4ZNDj6V1bZ5oAwCedfHf IMpkGr00VGm4r+HWduU4TFxPf/9gabGDxNQZ8ORccV2lIcyrQZmfccof9EuwqaHG DYXTimNZxac9d9lZMuSeMOW66f9gg+CJ1MznIwoRd7HDbCU/cLGIZGdHvSgconE= =4y+d -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] roda rk9
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Hi, Does anyone here have this board? If so, please contact me off-list (ME related work); I need the 4K descriptor region from a factory.bin dump. Regards, Francis Rowe. -BEGIN PGP SIGNATURE- Version: GnuPG v1 iQEcBAEBAgAGBQJUfYZLAAoJEP9Ft0z50c+UchcH/iu6avKAxOtsnKcn8qWd6Kn5 xr8jn+seRLvHgL+4PIQnk74jxYdfy+i+4kWogBmhm2Pu8KI0MoZDl4heb/I+x4Mk pk0Rp87RDTp62YbPIbdKZelMUK+P8vEUtUmENVNN435FOQLGgK3Yp4mTFYARqizp LjA5vxpsXdp/4CqQeC8uJNpjSFiH6Q+tuPFMXYvA0iuI1uRl2iUS+kFJwRue2KeW OFKYHqS9nV0bgQhJdERVUmZS0Hnv5DBjBrTe2VtWBoHm0t7sClV/VMPD236wj2aQ sL+km8QGzfHBOiR4GSgJmuPTHGVDEbTjZJi9rsrwkxPD6rnbq019/qNQf7XE1uk= =FLXI -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] cbfstool build issue in gcc 4.6.3
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 you mean force cbfstool make to use coreboot's crossgcc? On 21/11/14 12:31, Idwer Vollering wrote: > 2014-11-21 6:03 GMT+01:00 The Gluglug : > >> One possible solution is to simply upgrade GCC, which I will, but >> I would also like to get cbfstool to build again for this version >> of GCC. The patch in the gerrit link works, but is not accepted >> for upstream. >> >> Does anyone know a better way of doing it? > > Yes, we should use CC_x86_32 and co. from .xcompile instead. Can > you make that work? > > Idwer > -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) iQEcBAEBAgAGBQJUbzsBAAoJEP9Ft0z50c+UPDwH+QHm02d7Wr7rRJxyAGfOlW7F J5zFl9JNXvdbQDrHCmbYEQJ1h3GBXxiyfkoPx92S5B2Un+uy0AJfADRFk/X4LDAG Kt2gKFZwrWz4w3ztdKOB/JUN/+DsO9t/u/JJCJ8Hp90oymgBDncsrmYC+KjGU2sV lzX4EkOrSE47m01hPacyGRI8EoAJeedj+zuTaXwowNuhX5E7UGq6fMBXOSxIs3Wu EEIjGRBJB3x/c8+8y1Q4o1oIGm7bldHGoZj/2AMldEY7ouESORrImQ0FWfEb1FLS f7dpL4maCidqRXa2Kgi9qzKu9BFGkxRhqRWc61EEQldZ8yvVeXajA45boCUkkDM= =R/vs -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] cbfstool build issue in gcc 4.6.3
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
thanks. that worked. I'll update the gerrit and see what people think.
On 21/11/14 05:40, Scott Duplichan wrote:
> DEBUG("Ignoring program segment at %llx\n", ph_start);
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[coreboot] cbfstool build issue in gcc 4.6.3
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Hi, cbfs-mkstage.c: In function ‘is_phdr_ignored’: cbfs-mkstage.c:45:84: error: cast to pointer from integer of different size [-Werror=int-to-pointer-cast] The fix was made in http://review.coreboot.org/#/c/7545/ but some people were unhappy about the use of extra type casting. One possible solution is to simply upgrade GCC, which I will, but I would also like to get cbfstool to build again for this version of GCC. The patch in the gerrit link works, but is not accepted for upstream. Does anyone know a better way of doing it? Regards, Francis Rowe. -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) iQEcBAEBAgAGBQJUbsexAAoJEP9Ft0z50c+UGU4H/3nXZpc3OlaLNg+Otfv16Xw1 Cu9lj59jqYZ4BKCWIl/ZFeZ2Dgpjgc2hJcYk+V5VcQwAWzAt/UquQJQLFBcR0gMd eZycL6z3iJS9vGh3wqpT0y1xnOXk+CckrU+3wUpGcwYuVRw2PnTllrhBDirTFObJ bOGuns8b8+wdRkuEc9kIyGgOqzSC2pLKNaPI9uYo2bAIz7J2O8IO0T6vLrfnYMqu ytV1fArz/CViF685KDB4IXbqHKlKmnVLwRWZw5mEtic0TGrcKElrHry3KgnK3Z4z eYgQ2SZ6AyA0fs7gjkC3JN9M7peWiKZ+q1DPugBnx8HBoDXIYs65QzDDFOE4yRw= =caB/ -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] ME4/5
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 What systems in coreboot use intel ME 4 and which ones use ME 5? (I know X200 uses ME4 already.) -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) iQEcBAEBAgAGBQJUbGYBAAoJEP9Ft0z50c+UhEEH/1tp2im/ojNYAKx+93Q4tqki /DhMUis4KnVm5D4rMUMTFelJLfDsJR04RbM8CpoNu97owdi20H0LIqWwg02KB6TQ VYatvZRjeco9+hq4wJQ5H4jOYtss2hthwSZlgk6DJ31ldVt+cXGjda3MuQhdln0G mz0+DoPwjVsA+7e4wDiC6Cyk/TAupnKK9hcz1zx4f1nU1uuj5mlUiNr+ZBDSTjXp Tlmqhh2gTVyn7D8bztwQZ+T/mYNGw1ycrFyzMnnkwOckGdrGWR59uBhmTgEnFA7y tskAuu6lHf7O0I7Abt3QzfrgXBWJUL67HQtOXrSapuCE57S1oaQUagMorWL2J6A= =Id6A -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] vortex86ex
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Does anyone have a vortex86ex board with coreboot? -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) iQEcBAEBAgAGBQJUaTV4AAoJEP9Ft0z50c+UgzwH/3/Jx914Y6e0pFTaSE256oxs eKHigGpiMVpjseYCtMTK8ZulAIydvumY+jclwAzydY0P8IlcTW9teKF5JNxvnf0D EyaOel/pbxhIexOzs/ei8ALSil3+fPIhC2rqVs00l0MrO5DvBwa/fxF4qjWbnuuW KS+k68z2sLbD7UI+LDlJaj/ecZ1lzS/YaN1a7r2Wem1ZPda3ATjV0xMjFChvBkbo kFauxuLeVlBxqJfhkRZijpFrD0cpljCL6LWn/738HZbzXGVlqqKsCQcMBtcUsiEq o8yEI97BesJfXvFGXPsw05swoWxrVF/yJDR8ALM9Dy7Uabqumg/vhRK95EHbtF0= =g3MX -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] coreboot.org updates
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Small issue. The links are absolute: they have http://coreboot.org/ in the links. This means that when using https://coreboot.org/ and clicking the links, it takes me back to http://coreboot.org On 20/10/14 22:44, Marc Jones wrote: > Hi! > > coreboot.org is getting a little makeover. Check it out. > http://coreboot.org > > You can read about why in the following blog post: > http://blogs.coreboot.org/blog/2014/10/17/coreboot-org-website-updates/ > > > > Please let us know if you see any issues or misbehaving links with > the reorganization. > > Regards, Marc > > > -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) iQEcBAEBAgAGBQJURcDLAAoJEP9Ft0z50c+UmU4H/jN52+zeqDHpAxOH99L+jpsb dP32mksw2Nq/ZvBCbGW1Djk5fS+CLvZhi7Z4/CpTAS939bpHsCrh7HwPJExvp25J +aESEgpq0dWDepYEn4gk4lLDOE3x7/7G3Od+SRLl+W4aVt6r5lHxiqnj8CIv94qg cuGKbvr2SQJFOYWHhSf6jlNg4GYvBEfVVkVSY1ZKTya32UhXGRJPFrxMIndVRU2z mhs12I4YvN6WkoBDGKk3pY6ERxcViabk/63gO8E9DrCL8xFOLbp/R9cfX1FXKk0A FSNmpoVl/qS6dJiUKrkK43taknVpo3XJqj8CPdVfe+wYsR61pUSnhSx/yvJ0zm0= =DJEd -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] i945 (x60) with and without 6804
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 vladimir requested this. commit 0a66991a345f437e957ecc0ddeed70bc304d2a43 Author: Vladimir Serbinenko Date: Sun Oct 5 14:34:17 2014 +0200 acpi: Remove explicit pointer tracking in per-device ssdt. It's useless and error-prone. acpidump outputs: Without 6804: http://paste.debian.net/plain/125704 Then I cherry-pick changeset 6804 from gerrit, on top of 0a66991a345f437e957ecc0ddeed70bc304d2a43. With 6804: http://paste.debian.net/plain/125703 Attached is a copy of my .config for X60 -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) iQEcBAEBAgAGBQJUOUg3AAoJEP9Ft0z50c+U2J4H/3s9exVYRuf1IPSpF4VP0oqa kQUviPaBhRpY2MMyCB1SAScn5VBYLwRwWT0ykyBOSmU4ZN9YhbSM9+O+7dD2ZXkJ WWuR3by+kC4fcocQZ1zGE+BOPk7Hs6rSfypIVRen5zm5zBJv1Qu4wEUR50I1TiLa uEiyglI/R72bvFC/CSoeN5aNXbXTgPR6KonaXHazjgI1qmesjSTSQ7TIhoS9ZyOG y6g3G5bWPZVR6vNnNMBopJLvliRVJsJ1WPN8qEXXwtUgkr/VhwgCeMQ57Whc2lLm yLmY3T37JjKI0LnVKKkPMls8Z2Sy3zgGLm9w1rQKlialja5+npKurBrzdXSf5MU= =nSis -END PGP SIGNATURE- # # Automatically generated file; DO NOT EDIT. # coreboot configuration # # # General setup # CONFIG_EXPERT=y CONFIG_LOCALVERSION="7BETC7WW (2.08 )" CONFIG_CBFS_PREFIX="fallback" CONFIG_COMPILER_GCC=y # CONFIG_COMPILER_LLVM_CLANG is not set # CONFIG_ANY_TOOLCHAIN is not set # CONFIG_CCACHE is not set # CONFIG_SCONFIG_GENPARSER is not set CONFIG_USE_OPTION_TABLE=y CONFIG_COMPRESS_RAMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y CONFIG_EARLY_CBMEM_INIT=y # CONFIG_BROKEN_CAR_MIGRATE is not set CONFIG_DYNAMIC_CBMEM=y # CONFIG_COLLECT_TIMESTAMPS is not set # CONFIG_USE_BLOBS is not set # CONFIG_COVERAGE is not set # # Mainboard # # CONFIG_VENDOR_AAEON is not set # CONFIG_VENDOR_ABIT is not set # CONFIG_VENDOR_ADLINK is not set # CONFIG_VENDOR_ADVANSUS is not set # CONFIG_VENDOR_ADVANTECH is not set # CONFIG_VENDOR_AMD is not set # CONFIG_VENDOR_AOPEN is not set # CONFIG_VENDOR_APPLE is not set # CONFIG_VENDOR_ARIMA is not set # CONFIG_VENDOR_ARTECGROUP is not set # CONFIG_VENDOR_ASI is not set # CONFIG_VENDOR_ASROCK is not set # CONFIG_VENDOR_ASUS is not set # CONFIG_VENDOR_A_TREND is not set # CONFIG_VENDOR_AVALUE is not set # CONFIG_VENDOR_AXUS is not set # CONFIG_VENDOR_AZZA is not set # CONFIG_VENDOR_BACHMANN is not set # CONFIG_VENDOR_BCOM is not set # CONFIG_VENDOR_BIFFEROS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BROADCOM is not set # CONFIG_VENDOR_COMPAQ is not set # CONFIG_VENDOR_CUBIETECH is not set # CONFIG_VENDOR_DIGITALLOGIC is not set # CONFIG_VENDOR_DMP is not set # CONFIG_VENDOR_EAGLELION is not set # CONFIG_VENDOR_ECS is not set # CONFIG_VENDOR_EMULATION is not set # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_GIZMOSPHERE is not set # CONFIG_VENDOR_GOOGLE is not set # CONFIG_VENDOR_HP is not set # CONFIG_VENDOR_IBASE is not set # CONFIG_VENDOR_IBM is not set # CONFIG_VENDOR_IEI is not set # CONFIG_VENDOR_INTEL is not set # CONFIG_VENDOR_IWAVE is not set # CONFIG_VENDOR_IWILL is not set # CONFIG_VENDOR_JETWAY is not set # CONFIG_VENDOR_KONTRON is not set # CONFIG_VENDOR_LANNER is not set CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_LINUTOP is not set # CONFIG_VENDOR_LIPPERT is not set # CONFIG_VENDOR_MITAC is not set # CONFIG_VENDOR_MSI is not set # CONFIG_VENDOR_NEC is not set # CONFIG_VENDOR_NEWISYS is not set # CONFIG_VENDOR_NOKIA is not set # CONFIG_VENDOR_NVIDIA is not set # CONFIG_VENDOR_PACKARDBELL is not set # CONFIG_VENDOR_PCENGINES is not set # CONFIG_VENDOR_RCA is not set # CONFIG_VENDOR_RODA is not set # CONFIG_VENDOR_SAMSUNG is not set # CONFIG_VENDOR_SIEMENS is not set # CONFIG_VENDOR_SOYO is not set # CONFIG_VENDOR_SUNW is not set # CONFIG_VENDOR_SUPERMICRO is not set # CONFIG_VENDOR_TECHNEXION is not set # CONFIG_VENDOR_TECHNOLOGIC is not set # CONFIG_VENDOR_TELEVIDEO is not set # CONFIG_VENDOR_TI is not set # CONFIG_VENDOR_THOMSON is not set # CONFIG_VENDOR_TRAVERSE is not set # CONFIG_VENDOR_TYAN is not set # CONFIG_VENDOR_VIA is not set # CONFIG_VENDOR_WINENT is not set # CONFIG_VENDOR_WYSE is not set CONFIG_BOARD_SPECIFIC_OPTIONS=y CONFIG_MAINBOARD_DIR="lenovo/x60" CONFIG_MAINBOARD_PART_NUMBER="ThinkPad X60 / X60s / X60t" CONFIG_IRQ_SLOT_COUNT=18 CONFIG_MAINBOARD_VENDOR="Lenovo" CONFIG_MAX_CPUS=2 CONFIG_RAMTOP=0x20 CONFIG_HEAP_SIZE=0x4000 CONFIG_RAMBASE=0x10 CONFIG_VGA_BIOS_ID="8086,27a2" CONFIG_DRIVERS_PS2_KEYBOARD=y # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set # CONFIG_VGA_BIOS is not set # CONFIG_CONSOLE_POST is not set # CONFIG_UDELAY_IO is not set CONFIG_DCACHE_RAM_BASE=0xffdf8000 CONFIG_DCACHE_RAM_SIZE=0x8000 CONFIG_ACPI_SSDTX_NUM=0 CONFIG_MMCONF_BASE_ADDRESS=0xf000 CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO" # CONFIG_PCI_64BIT_PREF_MEM is not set CONFIG_UART_FOR_CONSOLE=0 CONFIG_ID_SECTION_OFFSET=0x80 CONFIG_STACK_SIZE=0x1000 CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 CONFIG_CBFS_SIZE=0x20 CONFIG_POST_IO=y CONFIG_POST_DEVICE=y CONFIG_BOARD_LENOVO_X60=y # CONFIG_BOARD_LENOVO_X200 is not set # CO
Re: [coreboot] 7042: cannot load payload
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Disregard. I tried another grub.elf and it worked. On 11/10/14 04:09, The Gluglug wrote: > To clarify, this is a ThinkPad X60. > > GRUB2 payload (my own grub.elf, which I know is fine), native > graphics. Microcode removed. > > On 11/10/14 04:08, The Gluglug wrote: >> I tried with latest master which has 7042 merged. Current commit >> here is 0a66991a345f437e957ecc0ddeed70bc304d2a43 > >> Is this related? > >> coreboot-4.0-7016-g0a66991-7BETC7WW (2.08 ) Sat Oct 11 03:53:37 >> BST 2014 starting... > >> Mobile Intel(R) 82945GM/GME Express Chipset (G)MCH capable of up >> to FSB 800 MHz (G)MCH capable of up to DDR2-667 Setting up >> static southbridge registers... GPIOS... done. Disabling >> Watchdog reboot... done. Setting up static northbridge >> registers... done. Waiting for MCHBAR to come up...ok PM1_CNT: >> 1c00 SMBus controller enabled. Setting up RAM controller. >> This mainboard supports Dual Channel Operation. DDR II Channel 0 >> Socket 0: x16DS DDR II Channel 1 Socket 0: x8DDS Memory will be >> driven at 667MHz with CAS=5 clocks tRAS = 15 cycles tRP = 5 >> cycles tRCD = 5 cycles Refresh: 7.8us tWR = 5 cycles DIMM 0 side >> 0 = 512 MB DIMM 0 side 1 = 512 MB DIMM 2 side 0 = 1024 MB DIMM 2 >> side 1 = 1024 MB tRFC = 43 cycles Setting Graphics Frequency... >> FSB: 667 MHz Voltage: 1.05V Render: 250MHz Display: 200MHz >> Setting Memory Frequency... CLKCFG=0x00010023, CLKCFG=0x00010043, >> ok Setting mode of operation for memory channels...Dual Channel >> Assymetric. Programming Clock Crossing...MEM=667 FSB=667... ok >> Setting RAM size... C0DRB = 0x20202010 C1DRB = 0x60606040 TOLUD = >> 0x00c0 Setting row attributes... C0DRA = 0x0033 C1DRA = 0x0033 >> DIMM0 has 8 banks. DIMM2 has 8 banks. one dimm per channel >> config.. Initializing System Memory IO... Programming Dual >> Channel RCOMP Table Index: 3 Programming DLL Timings... Enabling >> System Memory IO... jedec enable sequence: bank 0 jedec enable >> sequence: bank 1 bankaddr from bank size of rank 0 jedec enable >> sequence: bank 4 bankaddr from bank size of rank 1 jedec enable >> sequence: bank 5 bankaddr from bank size of rank 4 >> receive_enable_autoconfig() for channel 0 find_strobes_low() >> set_receive_enable() medium=0x3, coarse=0x5 set_receive_enable() >> medium=0x1, coarse=0x5 set_receive_enable() medium=0x1, >> coarse=0x5 find_strobes_edge() set_receive_enable() medium=0x1, >> coarse=0x5 add_quarter_clock() mediumcoarse=15 fine=a1 >> [1;63r[63;1H set_receive_enable() medium=0x3, coarse=0x5 >> find_preamble() set_receive_enable() medium=0x3, coarse=0x4 >> set_receive_enable() medium=0x3, coarse=0x3 add_quarter_clock() >> mediumcoarse=0f fine=21 normalize() set_receive_enable() >> medium=0x0, coarse=0x4 receive_enable_autoconfig() for channel 1 >> find_strobes_low() set_receive_enable() medium=0x3, coarse=0x5 >> set_receive_enable() medium=0x1, coarse=0x5 find_strobes_edge() >> set_receive_enable() medium=0x1, coarse=0x5 add_quarter_clock() >> mediumcoarse=15 fine=b2 set_receive_enable() medium=0x3, >> coarse=0x5 find_preamble() set_receive_enable() medium=0x3, >> coarse=0x4 set_receive_enable() medium=0x3, coarse=0x3 >> add_quarter_clock() mediumcoarse=0f fine=32 normalize() >> set_receive_enable() medium=0x0, coarse=0x4 RAM initialization >> finished. Setting up Egress Port RCRB Loading port arbitration >> table ...ok Wait for VC1 negotiation ...ok Setting up DMI RCRB >> Wait for VC1 negotiation ...done.. Internal graphics: enabled >> Waiting for DMI hardware...ok Enabling PCI Express x16 Link >> SLOTSTS: Disabling PCI Express x16 Link Wait for link to >> enter detect state... ok Setting up Root Complex Topology CBMEM: >> root @ bf7ff000 254 entries. Trying CBFS ramstage loader. CBFS: >> loading stage fallback/ramstage @ 0x10 (286780 bytes), entry >> @ 0x10 coreboot-4.0-7016-g0a66991-7BETC7WW (2.08 ) Sat Oct 11 >> 03:53:37 BST 2014 booting... BS: Entering BS_PRE_DEVICE state. >> CBMEM: recovering 4/254 entries from root @ bf7ff000 Moving GDT >> to bf7dc000...ok BS: Exiting BS_PRE_DEVICE state. BS: >> BS_PRE_DEVICE times (us): entry 7279 run 2979 exit 0 BS: >> Entering BS_DEV_INIT_CHIPS state. BS: Exiting BS_DEV_INIT_CHIPS >> state. BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 3324 exit 0 >> BS: Entering BS_DEV_ENUMERATE state. Enumerating buses... Show >> all devs...Before device enumeration. Root Device: enabled 1 >> CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 DOMAIN: : >> enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:02.0: ena
Re: [coreboot] 7042: cannot load payload
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 To clarify, this is a ThinkPad X60. GRUB2 payload (my own grub.elf, which I know is fine), native graphics. Microcode removed. On 11/10/14 04:08, The Gluglug wrote: > I tried with latest master which has 7042 merged. Current commit > here is 0a66991a345f437e957ecc0ddeed70bc304d2a43 > > Is this related? > > coreboot-4.0-7016-g0a66991-7BETC7WW (2.08 ) Sat Oct 11 03:53:37 > BST 2014 starting... > > Mobile Intel(R) 82945GM/GME Express Chipset (G)MCH capable of up to > FSB 800 MHz (G)MCH capable of up to DDR2-667 Setting up static > southbridge registers... GPIOS... done. Disabling Watchdog > reboot... done. Setting up static northbridge registers... done. > Waiting for MCHBAR to come up...ok PM1_CNT: 1c00 SMBus > controller enabled. Setting up RAM controller. This mainboard > supports Dual Channel Operation. DDR II Channel 0 Socket 0: x16DS > DDR II Channel 1 Socket 0: x8DDS Memory will be driven at 667MHz > with CAS=5 clocks tRAS = 15 cycles tRP = 5 cycles tRCD = 5 cycles > Refresh: 7.8us tWR = 5 cycles DIMM 0 side 0 = 512 MB DIMM 0 side 1 > = 512 MB DIMM 2 side 0 = 1024 MB DIMM 2 side 1 = 1024 MB tRFC = 43 > cycles Setting Graphics Frequency... FSB: 667 MHz Voltage: 1.05V > Render: 250MHz Display: 200MHz Setting Memory Frequency... > CLKCFG=0x00010023, CLKCFG=0x00010043, ok Setting mode of operation > for memory channels...Dual Channel Assymetric. Programming Clock > Crossing...MEM=667 FSB=667... ok Setting RAM size... C0DRB = > 0x20202010 C1DRB = 0x60606040 TOLUD = 0x00c0 Setting row > attributes... C0DRA = 0x0033 C1DRA = 0x0033 DIMM0 has 8 banks. > DIMM2 has 8 banks. one dimm per channel config.. Initializing > System Memory IO... Programming Dual Channel RCOMP Table Index: 3 > Programming DLL Timings... Enabling System Memory IO... jedec > enable sequence: bank 0 jedec enable sequence: bank 1 bankaddr from > bank size of rank 0 jedec enable sequence: bank 4 bankaddr from > bank size of rank 1 jedec enable sequence: bank 5 bankaddr from > bank size of rank 4 receive_enable_autoconfig() for channel 0 > find_strobes_low() set_receive_enable() medium=0x3, coarse=0x5 > set_receive_enable() medium=0x1, coarse=0x5 set_receive_enable() > medium=0x1, coarse=0x5 find_strobes_edge() set_receive_enable() > medium=0x1, coarse=0x5 add_quarter_clock() mediumcoarse=15 fine=a1 > [1;63r[63;1H set_receive_enable() medium=0x3, coarse=0x5 > find_preamble() set_receive_enable() medium=0x3, coarse=0x4 > set_receive_enable() medium=0x3, coarse=0x3 add_quarter_clock() > mediumcoarse=0f fine=21 normalize() set_receive_enable() > medium=0x0, coarse=0x4 receive_enable_autoconfig() for channel 1 > find_strobes_low() set_receive_enable() medium=0x3, coarse=0x5 > set_receive_enable() medium=0x1, coarse=0x5 find_strobes_edge() > set_receive_enable() medium=0x1, coarse=0x5 add_quarter_clock() > mediumcoarse=15 fine=b2 set_receive_enable() medium=0x3, > coarse=0x5 find_preamble() set_receive_enable() medium=0x3, > coarse=0x4 set_receive_enable() medium=0x3, coarse=0x3 > add_quarter_clock() mediumcoarse=0f fine=32 normalize() > set_receive_enable() medium=0x0, coarse=0x4 RAM initialization > finished. Setting up Egress Port RCRB Loading port arbitration > table ...ok Wait for VC1 negotiation ...ok Setting up DMI RCRB Wait > for VC1 negotiation ...done.. Internal graphics: enabled Waiting > for DMI hardware...ok Enabling PCI Express x16 Link SLOTSTS: > Disabling PCI Express x16 Link Wait for link to enter detect > state... ok Setting up Root Complex Topology CBMEM: root @ bf7ff000 > 254 entries. Trying CBFS ramstage loader. CBFS: loading stage > fallback/ramstage @ 0x10 (286780 bytes), entry @ 0x10 > coreboot-4.0-7016-g0a66991-7BETC7WW (2.08 ) Sat Oct 11 03:53:37 > BST 2014 booting... BS: Entering BS_PRE_DEVICE state. CBMEM: > recovering 4/254 entries from root @ bf7ff000 Moving GDT to > bf7dc000...ok BS: Exiting BS_PRE_DEVICE state. BS: BS_PRE_DEVICE > times (us): entry 7279 run 2979 exit 0 BS: Entering > BS_DEV_INIT_CHIPS state. BS: Exiting BS_DEV_INIT_CHIPS state. BS: > BS_DEV_INIT_CHIPS times (us): entry 0 run 3324 exit 0 BS: Entering > BS_DEV_ENUMERATE state. Enumerating buses... Show all devs...Before > device enumeration. Root Device: enabled 1 CPU_CLUSTER: 0: enabled > 1 APIC: 00: enabled 1 DOMAIN: : enabled 1 PCI: 00:00.0: enabled > 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 1 PCI: 00:1b.0: > enabled 1 PCI: 00:1c.0: enabled 1 PCI: 00:1c.1: enabled 1 PCI: > 00:1d.0: enabled 1 PCI: 00:1d.1: enabled 1 PCI: 00:1d.2: enabled 1 > PCI: 00:1d.3: enabled 1 PCI: 00:1d.7: enabled 1 PCI: 00:1f.0: > enabled 1 PNP: 00ff.1: enabled 1 PNP: 00ff.2: enabled 1 PNP: > 164e.2: enabled 1 PNP: 164e.3: enabled 1 PNP: 164e.7: enabled 1 >
[coreboot] 7042: cannot load payload
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 I tried with latest master which has 7042 merged. Current commit here is 0a66991a345f437e957ecc0ddeed70bc304d2a43 Is this related? coreboot-4.0-7016-g0a66991-7BETC7WW (2.08 ) Sat Oct 11 03:53:37 BST 2014 starting... Mobile Intel(R) 82945GM/GME Express Chipset (G)MCH capable of up to FSB 800 MHz (G)MCH capable of up to DDR2-667 Setting up static southbridge registers... GPIOS... done. Disabling Watchdog reboot... done. Setting up static northbridge registers... done. Waiting for MCHBAR to come up...ok PM1_CNT: 1c00 SMBus controller enabled. Setting up RAM controller. This mainboard supports Dual Channel Operation. DDR II Channel 0 Socket 0: x16DS DDR II Channel 1 Socket 0: x8DDS Memory will be driven at 667MHz with CAS=5 clocks tRAS = 15 cycles tRP = 5 cycles tRCD = 5 cycles Refresh: 7.8us tWR = 5 cycles DIMM 0 side 0 = 512 MB DIMM 0 side 1 = 512 MB DIMM 2 side 0 = 1024 MB DIMM 2 side 1 = 1024 MB tRFC = 43 cycles Setting Graphics Frequency... FSB: 667 MHz Voltage: 1.05V Render: 250MHz Display: 200MHz Setting Memory Frequency... CLKCFG=0x00010023, CLKCFG=0x00010043, ok Setting mode of operation for memory channels...Dual Channel Assymetric. Programming Clock Crossing...MEM=667 FSB=667... ok Setting RAM size... C0DRB = 0x20202010 C1DRB = 0x60606040 TOLUD = 0x00c0 Setting row attributes... C0DRA = 0x0033 C1DRA = 0x0033 DIMM0 has 8 banks. DIMM2 has 8 banks. one dimm per channel config.. Initializing System Memory IO... Programming Dual Channel RCOMP Table Index: 3 Programming DLL Timings... Enabling System Memory IO... jedec enable sequence: bank 0 jedec enable sequence: bank 1 bankaddr from bank size of rank 0 jedec enable sequence: bank 4 bankaddr from bank size of rank 1 jedec enable sequence: bank 5 bankaddr from bank size of rank 4 receive_enable_autoconfig() for channel 0 find_strobes_low() set_receive_enable() medium=0x3, coarse=0x5 set_receive_enable() medium=0x1, coarse=0x5 set_receive_enable() medium=0x1, coarse=0x5 find_strobes_edge() set_receive_enable() medium=0x1, coarse=0x5 add_quarter_clock() mediumcoarse=15 fine=a1 [1;63r[63;1H set_receive_enable() medium=0x3, coarse=0x5 find_preamble() set_receive_enable() medium=0x3, coarse=0x4 set_receive_enable() medium=0x3, coarse=0x3 add_quarter_clock() mediumcoarse=0f fine=21 normalize() set_receive_enable() medium=0x0, coarse=0x4 receive_enable_autoconfig() for channel 1 find_strobes_low() set_receive_enable() medium=0x3, coarse=0x5 set_receive_enable() medium=0x1, coarse=0x5 find_strobes_edge() set_receive_enable() medium=0x1, coarse=0x5 add_quarter_clock() mediumcoarse=15 fine=b2 set_receive_enable() medium=0x3, coarse=0x5 find_preamble() set_receive_enable() medium=0x3, coarse=0x4 set_receive_enable() medium=0x3, coarse=0x3 add_quarter_clock() mediumcoarse=0f fine=32 normalize() set_receive_enable() medium=0x0, coarse=0x4 RAM initialization finished. Setting up Egress Port RCRB Loading port arbitration table ...ok Wait for VC1 negotiation ...ok Setting up DMI RCRB Wait for VC1 negotiation ...done.. Internal graphics: enabled Waiting for DMI hardware...ok Enabling PCI Express x16 Link SLOTSTS: Disabling PCI Express x16 Link Wait for link to enter detect state... ok Setting up Root Complex Topology CBMEM: root @ bf7ff000 254 entries. Trying CBFS ramstage loader. CBFS: loading stage fallback/ramstage @ 0x10 (286780 bytes), entry @ 0x10 coreboot-4.0-7016-g0a66991-7BETC7WW (2.08 ) Sat Oct 11 03:53:37 BST 2014 booting... BS: Entering BS_PRE_DEVICE state. CBMEM: recovering 4/254 entries from root @ bf7ff000 Moving GDT to bf7dc000...ok BS: Exiting BS_PRE_DEVICE state. BS: BS_PRE_DEVICE times (us): entry 7279 run 2979 exit 0 BS: Entering BS_DEV_INIT_CHIPS state. BS: Exiting BS_DEV_INIT_CHIPS state. BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 3324 exit 0 BS: Entering BS_DEV_ENUMERATE state. Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 DOMAIN: : enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 1 PCI: 00:1b.0: enabled 1 PCI: 00:1c.0: enabled 1 PCI: 00:1c.1: enabled 1 PCI: 00:1d.0: enabled 1 PCI: 00:1d.1: enabled 1 PCI: 00:1d.2: enabled 1 PCI: 00:1d.3: enabled 1 PCI: 00:1d.7: enabled 1 PCI: 00:1f.0: enabled 1 PNP: 00ff.1: enabled 1 PNP: 00ff.2: enabled 1 PNP: 164e.2: enabled 1 PNP: 164e.3: enabled 1 PNP: 164e.7: enabled 1 PNP: 164e.19: enabled 1 PNP: 002e.0: enabled 0 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 0 PNP: 002e.3: enabled 1 PNP: 002e.7: enabled 1 PNP: 002e.a: enabled 0 PCI: 00:1f.1: enabled 1 PCI: 00:1f.2: enabled 1 PCI: 00:1f.3: enabled 1 I2C: 00:69: enabled 1 I2C: 00:54: enabled 1 I2C: 00:55: enabled 1 I2C: 00:56: enabled 1 I2C: 00:57: enabled 1 I2C: 00:5c: enabled 1 I2C: 00:5d: enabled 1 I2C: 00:5e: enabled 1 I2C: 00:5f: enabled 1 Compare with tree... Root Device: enabled 1
Re: [coreboot] broken boards
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 The issue is that on affected machines, it's very hard to know what's happening because serial output doesn't even work. On 11/10/14 01:42, ron minnich wrote: > "It broke" is not a very useful diagnosis. Anyone care to report > what's going on? > > Thanks! > > Ron > -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) iQEcBAEBAgAGBQJUOH1VAAoJEP9Ft0z50c+ULhcH/3+WvN09RZmdGCMbbLxpC53r nKNRGWR4SQNIfmGrUGiWQeMqgeCG3iOzKsogPoaATyEaRB4npzJxw25NRZZTgHdU CGDpFB3yhcJBp0xWKCO4yv5QtjTPDgRq6Kt9fgq+Rg52EiKHiJch5nN2fTJ2hsdH jnptoNFbxUh4T7muqqS3ZPhJTJBujlfooB2+y0746RO/AmBGFn60RcEHngUzvDBW eC2662L1QgmdXRscCMdz10+6WSONWu65HcTuem54yS1QjgLupMu5hzs22bj/6Wcf 3nQOp76XppsFJzijEaxDOFxa1n+x1dWMW//RZAE8WXDtlqhVC1iAdpo/i7yXd6E= =hRFZ -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] broken boards
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 http://review.coreboot.org/#/c/7041/ This reverts a commit that was intended to help for non-x86 targets, related to finding cbmem tables. The commit that 7041 reverts caused X60, X201 and Google/panther (Haswell) not to boot. T60, X60 Tablet and macbook21 are probably also affected. Other boards may also be affected. Can everyone who has a recovery/unbricking method test the latest master -without- 7041 to see whether it fails to boot - the behaviour is: no image on screen, no serial output, machine fails to boot (it doesn't even reach the payload). Then if it does fail, try again with 7041 included and report back. -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) iQEcBAEBAgAGBQJUOHxqAAoJEP9Ft0z50c+Uei8IAMGn0g1wXwA/iMGHY1CYu6sx TDDXL/B7JZ3FxoBEQde/xETR2HoxhqSeoSxvxC58z9n08gx9w1tY2afoM/VYeo57 BEPCYGbBpVo8Sp5JsdEWZ3eWgVEUBEL7vKm4GagpLcnYdQk0o+Mm61x6pm/UJ7lt c+AYhiFsgsqO9aO1HH8qG1uTsJ1W+BK9EPxNBQrJYsZhguJjgTzYogshZ7TnFPje 0qXouMa58rvHouYMw1Cvnv0tnV39wYEVAbyAqhYM7xhktLRtgSe3KCUUAE0DVCES rX/bTF4FPiNMuxZngD8zASFBxHJ6xbSsk2ubJkWIEdIfC24SvyGp9bw3iLuQvlc= =3nVL -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] commit 6b330f2a bricked my x60; a296f9e3 was working.
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 I addded this to the commit message on 7041. Thanks! On 11/10/14 00:38, Matt DeVillier wrote: > same issue here on Google/panther (Haswell), reverting the commit > fixed things > > On 10/10/2014 4:09 PM, The Gluglug wrote: Based on advice from > Alexander I did: git revert 35382a6e > > Made my X60 boot, where without the revert I had the same issue as > Andrew Engelbrecht that the machine > didn't boot; not even serial output worked. > > I pushed the revert commit to gerrit for others to look at: > http://review.coreboot.org/#/c/7041/ > > Thanks to Alexander for the bisect! > > On 10/10/14 21:08, Alexander Couzens wrote: >>>> Hi Andrew, >>>> >>>> on my x201t I got the same problems. I bisect it to cbmem >>>> console: Locate the preram console with a symbol instead of a >>>> section. (commit 35382a6e, Change-Id: I3257b981e). >>>> >>>> @Gabe: Do you tested the commit with SeaBios as payload? >>>> >>>> @Andrew: You can also use a raspberry pi or a beaglebone >>>> black. They are a lot faster than a buspirate (30min -> >>>> 5min). >>>> >>>> Best, Alex >>>> >>>> cfg: >>>> http://lynxis.crew.c-base.org/coreboot.config.762d53d41_without_cbmem >>>> >>>> >>>> >>>> >> > -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) iQEcBAEBAgAGBQJUOG98AAoJEP9Ft0z50c+UDmwH+wUHiUNK1IcVksyhnuchBMr0 5aafjMD7QXtQ9Rs3FtXRRyCIYRbTIwOBMIx7yz9zRe2xYEfpq9GQ6G8yuUa+GfFA m3t/mwHtCJg34g9rXgqUf1s9fnP0Nb1A6L9ss4zqAvrV1TW4jDxKbSEKm/StCArG H6Y6qjXLhAYf/RVkf7xf9q4v51amJ/hbM72m/MOLbsqKz0yPJoDOKvP+ADFs+5b0 E93wJni/qkuRzHDSP7dsZVxAMb+bKaun9EFd+ZQftNV4Oz1pIr5s3whKhDiKHIuh NMmUY/miuXO07gqdQVjZYSg6xQFBqcNFg8q7qZEk2U+ZoN8bdx/F2zKVKML0ixc= =nGcR -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] commit 6b330f2a bricked my x60; a296f9e3 was working.
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Based on advice from Alexander I did: git revert 35382a6e Made my X60 boot, where without the revert I had the same issue as Andrew Engelbrecht that the machine didn't boot; not even serial output worked. I pushed the revert commit to gerrit for others to look at: http://review.coreboot.org/#/c/7041/ Thanks to Alexander for the bisect! On 10/10/14 21:08, Alexander Couzens wrote: > Hi Andrew, > > on my x201t I got the same problems. I bisect it to cbmem console: > Locate the preram console with a symbol instead of a section. > (commit 35382a6e, Change-Id: I3257b981e). > > @Gabe: Do you tested the commit with SeaBios as payload? > > @Andrew: You can also use a raspberry pi or a beaglebone black. > They are a lot faster than a buspirate (30min -> 5min). > > Best, Alex > > cfg: > http://lynxis.crew.c-base.org/coreboot.config.762d53d41_without_cbmem > > > > -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) iQEcBAEBAgAGBQJUOEr5AAoJEP9Ft0z50c+U0MsH/jh1preGRFV5QXyeybJcxC+k xhJAz+NoLdD57PAPP4y858Z4u+yV/ShWw+VlR+gQbf/1K8goCgV7w66eosWCg3OO 6OryX7Eq/gNuLe2Z8Ei0fhduYHUhipwZFRlHJ1AF2qKzqoAoIodcm3UAoj/MK6R6 e7UeHLmgQRe2YsUBD9eDHPxTkYleCoHt9gHGayWZE7tRnCWXglyDUkY96EFdToi8 CxsEr6FmE6sDIskgWAYeHfgpWq/u0TyYasaP+FkWKrAVt9E7U7SK00/PZtFizUqR GKtFKnAB1faR8Y+3DgtXXq0+KmtQ392Kmp1goN3BaSB87IF2E4zY9jyQLIXdU6w= =504N -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] fully encrypted install: Parabola/Arch with GRUB payload
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 http://libreboot.org/docs/howtos/encrypted_parabola.html Can also be done with Arch, with coreboot and grub payload. -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQEcBAEBAgAGBQJUFlaUAAoJEP9Ft0z50c+UhmwIAMS8XeYUp/44loaKmK2jReuj I+aXbTmhg7HaMzqVgzc/Y834oPWXJJL2nHvmSGysEdicKu8W72ZO163KpBwOxQSm /gvPeXp2UJWlFbdhgJIjGhZ3xAZ7t4CUAMzikO1iNX9TbwLJnO52kQINolYVJg61 POQakIRQqrhF0JK5hkOLBh5OazCu1dtqzu8ZB0ROdHBYxAF+6EChvjnN/74OKfQV EfJt5zSLrmzLM19aD7NlUvTxLaX3xEurRTeVj2JDjQQEt4FPmRjK4trolci2E/gM WE70r7xyPsBe5hiOwVFVJ0+1k7UlbQNhA1WOnRbcOL3cTRIbAZnVsJEk8yVThQE= =SPWF -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] i945: 6718 PTE (page table error) report
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 A while ago I was asked by Paul to check if PTE errors still exist on i945 (X60 tested here) related to i945 native graphics, when including 6718. That patch is now merged and I can confirm that they do still exist. Posting to list because it may be useful for others. http://dev.libreboot.org/docs/future/dumps/pte_x60_6718/dmesg http://dev.libreboot.org/docs/future/dumps/pte_x60_6718/kern.log Snippet from kernel log: Aug 31 22:50:24 minifree kernel: [1.180448] vgaarb: device changed decodes: PCI::00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem Aug 31 22:50:24 minifree kernel: [1.180450] i915: render error detected, EIR: 0x0010 Aug 31 22:50:24 minifree kernel: [1.180452] i915: page table error Aug 31 22:50:24 minifree kernel: [1.180454] i915: PGTBL_ER: 0x0012 Aug 31 22:50:24 minifree kernel: [1.180457] [drm:i915_report_and_clear_eir] *ERROR* EIR stuck: 0x0010, masking Aug 31 22:50:24 minifree kernel: [1.180463] [drm:i915_irq_handler], pipe B underrun Aug 31 22:50:24 minifree kernel: [1.180469] i915: render error detected, EIR: 0x0010 Aug 31 22:50:24 minifree kernel: [1.180471] i915: page table error Aug 31 22:50:24 minifree kernel: [1.180473] i915: PGTBL_ER: 0x0012 -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQEcBAEBAgAGBQJUA5tTAAoJEP9Ft0z50c+UnLwH/1YAzwI9qsuYj2Xb1jq4MuLe /y6fcILc/GElv2S9TcWU8hYM6vrALMDD9gBctgIpfpdNE586Z7924SypmxseRyZF oEFC5QU2FlBaYHWCiLHPt8xMJhW93GuXFdxTbfyi9P7Ey5HxlJ/so7bOluojBarv bGWQeEL5V44l/ysOy09So5es9m2kq/4IVleokdTSzPWWL3Mb7Fl3E6Dz2JUvacaK 126V7WkBHpy9r835TCCUJk+0+42nqppqcwmZ03k5P4x7moAVCKzDOFtrJkD30dYp ijnyj6lGS+pID2ywXR3+3JDM0YFPfol8nCsDs5pBkiaGIkyNcwwP3+cQeDdJhCI= =1aL5 -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] bug report: i945 text-mode native graphics initialization: graphical corruption with starting Debian/Trisquel net installer.
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
Here is some further notes that I collected:
There are issues with i945 text mode graphics initialization:
http://www.coreboot.org/pipermail/coreboot/2014-August/078468.html
look into it, follow up on that post and try to fix it.
Trisquel isolinux menu doesn't show up in seabios (seavgabios)
with text-mode, it just says 'Error setting up gfxboot', but it works
in text-mode with the extract vbios. Looking at gma.c, it looks like
this isn't setup in text-mode by native init, but obviously when using
the extracted vbios, it is setting everything up properly?
Debian/Trisquel net-install shows graphical corruption (see
mailing list link) when booting directly from GRUB in text-mode, but
works just fine when using the extracted vbios instead of seavgabios.
Are these using text-mode or trying to use graphics? (graphical
installers work just fine in native init or with extracted vbios)
Debian net-installer (graphical one) fails (trisquel graphical
installer is ok) in native graphics and text-mode (works fine in
vesa/cbfb, or in text-mode plus extracted vbios):
Scrolling/flickering text in a loop (segmentation fault):
Xorg (xorg_backtrace+0x49) [0xb7***] (numbers change)
Xorg (0xb75**) [0xb7***] (numbers change
(vdso) (__kernel_rt_sigreturn+0x0) [0xb7**] (numbers change)
/lib/libc.so.6 (cfree+0x49) [0xb7**] (numbers change)
Xorg (xf86DeleteMode+0x51) [0xb7**] (numbers change)
Segmentation fault at address 0xb720
Fatal server error:
Caught signal 11 (Segmentation fault). Server aborting
phcoder says that there are limitations in native graphic: for
example, he says native init doesn't provide int10h at all, and that
it lacks VBT. Are there other issues? He says that there are also lots
of ACPI issues in general.
On 26/08/14 02:06, The Gluglug wrote:
> The same issue does not occur when using coreboot with the vga rom
> extracted from factory bios.
>
> On 25/08/14 16:50, The Gluglug wrote:
>> Using 6725 to enable text-mode gfx init on X60 when using native
>> graphics initialization.
>
>> Affected machines: X60, T60. It may also affect:
>> macbook21/macbook11, X60 Tablet
>
>> This relies on the (merged) patch 6723 that enables text-mode
>> graphics initialization on i945 platforms. The code is there.
>
>> I then disabled "Keep VESA framebuffer" in menuconfig, to enable
>> text-mode.
>
>> error: no video mode activated This is what I see when I try to
>> use the net install iso for Debian with the isolinux parser in
>> grub. I also saw the same thing when trying to start Trisquel 6
>> isolinux menu from SeaBIOS (with SeaVGABIOS added at
>> vgaroms/vgabios.bin from seabios's rom that I built).
>
>> See attached image of what happens when I try to boot the net
>> install from Debian (same thing happens with the Trisquel net
>> install), using the following: linux (usb0)/install.386/vmlinuz
>> initrd (usb0)/install.386/initrd.gz boot
>
>> As you can see, there is quite a lot of flicker and parts of the
>> screen are missing or corrupt. I think this is related to the
>> issue above ("error: no video mode activated").
>
>> The net install for Debian and Trisquel both work when using
>> corebootfb initialization method, but they fail (as seen in the
>> image) for text-mode method.
>
>> In case the attachment was scrubbed by the mailing list, I also
>> put it here: http://dev.libreboot.org/x60txtmode.jpg
>
>> Trisquel graphical install works (I wasn't able to figure out
>> how to boot the Debian graphical install).
>
>> I also enabled it for T60 (adding the keep/drop vesa fb option
>> for t60/Kconfig, based on 6725, and cherry picking 5345) and the
>> same behaviour was observed there.
>
>> What does work in text-mode init (tested): memtest86+ and grub
>> invaders.
>
>
>
>
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Re: [coreboot] bug report: i945 text-mode native graphics initialization: graphical corruption with starting Debian/Trisquel net installer.
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
The same issue does not occur when using coreboot with the vga rom
extracted from factory bios.
On 25/08/14 16:50, The Gluglug wrote:
> Using 6725 to enable text-mode gfx init on X60 when using native
> graphics initialization.
>
> Affected machines: X60, T60. It may also affect:
> macbook21/macbook11, X60 Tablet
>
> This relies on the (merged) patch 6723 that enables text-mode
> graphics initialization on i945 platforms. The code is there.
>
> I then disabled "Keep VESA framebuffer" in menuconfig, to enable
> text-mode.
>
> error: no video mode activated This is what I see when I try to use
> the net install iso for Debian with the isolinux parser in grub. I
> also saw the same thing when trying to start Trisquel 6 isolinux
> menu from SeaBIOS (with SeaVGABIOS added at vgaroms/vgabios.bin
> from seabios's rom that I built).
>
> See attached image of what happens when I try to boot the net
> install from Debian (same thing happens with the Trisquel net
> install), using the following: linux (usb0)/install.386/vmlinuz
> initrd (usb0)/install.386/initrd.gz boot
>
> As you can see, there is quite a lot of flicker and parts of the
> screen are missing or corrupt. I think this is related to the
> issue above ("error: no video mode activated").
>
> The net install for Debian and Trisquel both work when using
> corebootfb initialization method, but they fail (as seen in the
> image) for text-mode method.
>
> In case the attachment was scrubbed by the mailing list, I also put
> it here: http://dev.libreboot.org/x60txtmode.jpg
>
> Trisquel graphical install works (I wasn't able to figure out how
> to boot the Debian graphical install).
>
> I also enabled it for T60 (adding the keep/drop vesa fb option for
> t60/Kconfig, based on 6725, and cherry picking 5345) and the same
> behaviour was observed there.
>
> What does work in text-mode init (tested): memtest86+ and grub
> invaders.
>
>
>
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Re: [coreboot] x60 : trying to boot to a debian in less than 2 seconds
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 25/08/14 04:25, Charles Devereaux wrote: > Hello > > I'm still trying to improve boot time. > > After some further optimizations (previous results : 2.2s for the > kernel, 0.6s for the daemons), I believe it should be possible to > get a command line in less than 2 seconds, since most of the time > is spend re-initializing the video chip (almost a full second) > while there are some features to prevent just that. > > It seems that coreboot is spending some time initializing the video > chip for grub, then linux spends some time again - even when grub > option "set gfxpayload=keep" is set (which should prevent that) and > when coreboot is compiled with CONFIG_FRAMEBUFFER_KEEP_VESA_MODE > > in kernel 3.10.45 : [0.291014] [drm] GMBUS [i915 gmbus panel] > timed out, falling back to bit ban ging on pin 3 [0.321926] > [drm] initialized overlay support [0.384013] [drm] GMBUS [i915 > gmbus vga] timed out, falling back to bit bangi ng on pin 2 [ > 0.570068] fbcon: inteldrmfb (fb0) is primary device [1.230010] > Console: switching to colour frame buffer device 128x48 [ > 1.258981] i915 :00:02.0: fb0: inteldrmfb frame buffer device [ > 1.258984] i915 :00:02.0: registered panic notifier [ > 1.258992] [drm] Initialized i915 1.6.0 20080730 for :00:02.0 > on minor 0 > > I'm currently trying a recent kernel since some i915 patches have > been backported (cf > http://blog.ffwll.ch/2014/04/neat-drmi915-stuff-for-315.html), > introducing the i915.fastboot option to do just that, but it does > not help. > > I must be doing something terribly wrong, but I just don't realize > what exactly. > > Has anyone succeeded in keeping the vesa mode? > > Charles > > > Do you get those same errors in 3.10.45 when booting factory bios or coreboot+vgarom? -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQEcBAEBAgAGBQJT+7f9AAoJEP9Ft0z50c+UBxoH/0LJoojt+KLktA3lXWO+wPTs 1u2dRykqxzT0vkcCvi53WiEq3tO3rLJE+PudopjfBZk1kbH08VLKKLKkXO+Q4Fp+ VwZiV6F2R+2gKsTlyGXgnm/2qqPdH16nZ+oEV25wJtPkGcLYJaBmwuYzI5fr8NSa cTmCzpmzT+0bl4SPo0PtlwcIFYzCPTCgs8QTd2Ly8tutnmDqV9iib9Wy7K1+igAT e+hiqGz9Npn54gd1drNr+cc7QYZiuMx65V6rAipl8LeuaybkSmQxy+N6qWHS3IlE ioG3/2r3J4Q7KzJiX3M9RD0+NSPoSkN4XkkzEdOtXLFjjoe+3l3F1rneIE1Fuss= =dLQ7 -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] IBM x60t test - DSDT is in fact incomplete
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 > Ideally, the DSDT should be fixed within coreboot, but this goes > beyond my present abilities. Alternatively, I plan to release a > patched x60t DSDT for use with libreboot. > Please submit it to upstream (coreboot). The same applies for any other patch. Libreboot is a distribution and not a fork of coreboot. -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQEcBAEBAgAGBQJT+zGIAAoJEP9Ft0z50c+US2cH/2WZuCYg2NN210Q5x7JFQ2RP UvQ/OCmnY3KeVyt2Rxwa81xVf0qHH9VkfyxZhmYMVRN3OUCjlryBMYAcKcC5jV88 ohTHNTXj10Zej0RB5iQ+wkDHKKviAHKFpJXve5ns2CVVI5n6UFq1KQmPEvJVwU5z bcJjHByaRW7Ej/pg4rGvMkvcNTiBPsliasOmuKzRtKtYRIdpcG21geCamJLGkf2L eLHx/tn8/hqSJwJMt4K6RsHoBhr302eLRfVPFXyRaIdlBf6OD4DqnK0OppUhT/Hu 4Jkr7F7BuB0YRTOAB5PwXUzqaZUdLp+L1HktuyquQCn8zf8CVF4G5tLMKO0gUUU= =a/XJ -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] X60: ethernet LED still on when machine is powered off or suspended
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 21/08/14 23:41, ron minnich wrote: > On Thu, Aug 21, 2014 at 2:10 PM, The Gluglug > wrote: >> -BEGIN PGP SIGNED MESSAGE- Hash: SHA1 >> >> >> >> On 21/08/14 22:08, The Gluglug wrote: >>> A little quirk I noticed. If I put the machine in suspend >>> while an ethernet cable is plugged in to a switch (or if >>> plugging it in after suspending), the green light from the >>> ethernet/eth0 is still active. >>> >>> Any ideas? >>> >> >> The same thing also happens while the machine is powered off, if >> I leave the AC adapter/charger connected. > > > and only on coreboot? > > I can't recall but I did have laptops that would light the LED even > when off, I always assumed it was the ME > > ron > Haven't tried it on factory.bin. Will let you know. i945 doesn't have ME/AMT, as far as I know. -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQEcBAEBAgAGBQJT9ps5AAoJEP9Ft0z50c+UWKsIAJn5w/+6RxZ6oyhqaHSuJoBq 2/YHDL5TYM7EW0XoBstcB2NS7W/lWtWfwpCvNvM9R3ynliqPoAjErMZIuTwPM4p9 wBFvNdSWJGHOgxi8KEDA1n2Af0Dhfoys6Wb+uI3hflGGunJHz05QWiMEos0dWkmU JsZVr2HCrjIKTGooXJxZXfRlD6SY2S3PNY7myDcfeAaTnx6kCsySFCqBkfIUTIhf Mtg1NosYrbmNAXqROwrHf5LO3oAJ41zODZraMspYy+QDE8XvO2wbzkDBtglV4rBn V7qO7PaS1l1jfOlERTd3A6ZEXI4ltzr8BTwe3ZTZod+zrs9R9/May4JasN4lKe4= =on0Y -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] X60: ethernet LED still on when machine is powered off or suspended
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 21/08/14 22:08, The Gluglug wrote: > A little quirk I noticed. If I put the machine in suspend while an > ethernet cable is plugged in to a switch (or if plugging it in > after suspending), the green light from the ethernet/eth0 is still > active. > > Any ideas? > The same thing also happens while the machine is powered off, if I leave the AC adapter/charger connected. -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQEcBAEBAgAGBQJT9mBIAAoJEP9Ft0z50c+UmxwH/Rn7Gdxk+Vp9uqdp8XD3AeoV D2Lr5YC3j6bnF3sg9I0dDE+UJatXUHXlgF8lemsyrSfHx/4CFXKvT6FtTgkW08lt E01q5Z71mgB6rGkjX4gLf3wQPldtPj4QElCGaHB1K/vO2vuYg/YqdR83B38VkVdH uSoakYvlw6Q4EWRTkTcya0mo9JQu3DCpfd+m5HTSR/aTYxpIExWsb6OiC8DKdYrO sSWReZIPBYKbnyIg6dDJu3reqiQG0uNBI9fkWX6dHJQse+WMQAAMLHPadgLt67+p 5pKurKiJdyYDuzwntiXESXN1cF3SnWWnTEfJoiR6oWGqFnL5s+HAhtwtTxahv9I= =Hqca -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] X60: ethernet LED still on when machine is powered off or suspended
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 A little quirk I noticed. If I put the machine in suspend while an ethernet cable is plugged in to a switch (or if plugging it in after suspending), the green light from the ethernet/eth0 is still active. Any ideas? -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQEcBAEBAgAGBQJT9l/NAAoJEP9Ft0z50c+UaF4H/jqCZlmVadTnM0YZidrhRL2Q 6V6dUaskvg9CjXr6H4p8LvFVsBek3A2id9yRvqidbR98+O3Q2OUSgqhdMNNN9Kqh eWAhJ6Pni2qV4OmVkHhTIWZxVQwbVJGbQP1RLQ1hRsPfBxVcQIr/uhyYqZCov5BB VXCRGJD9n5gysr2QN9ccuKhqWXqqdUi00tGwXgqO3SIQ61piNJGgUZlWObDeEB23 whZV3Sqf0zn9wT61euTtEghspisM4ihi8oDe78Aav9SthmagVr6DSz3wr/Ww+cti BIFTtbK9y+RHRvlLH35F8OFGr+X2le5QQtEhonqh4yoRuIAEN1w13lm55Y6XlpU= =T1KC -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] f2a85m and e350m1 dmidecode
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Can someone with one of these boards attach their dmidecode output (from factory bios)? -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQEcBAEBAgAGBQJT8XS7AAoJEP9Ft0z50c+U268H/RmIiirFcC9GadB8v/94mkq6 beiXEMqwOPTb7+vC4JF2AsQ7n7pFLY8GRoox2LlcbyPdJMt5UEun1mlpndB381Sb SNaNzUZjxfnGVZPxsNx5PaAlzBfBC2ZjwJrW/Mk8iTdZrsVRINulMOooI6ohW66X iN+mtzz4ns/csGKrXKzcr0B01zMIbqVVPSGdHJzq29o+tUbMRL4LCVU7/vSOLn4V 8OwkwlZETJEBxDFGH/vR75wOFb+uX6BGPf3E18Cegz/N90f6fYScVkeovMetXaum cGyb8lH/04QJX90C08tx1IMjlOlEDenn2CUn6idvfXftuvCCpvyXD8XAgSZgmWQ= =JpFo -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] why is firmware 32 bit as opposed to 64 bit
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 What about 32-bit-only machines, or people that want to use a 32-bit OS? On 10/08/14 22:37, ron minnich wrote: > One of the reasons I"m working to implement paging for 32-bit mode > is for our eventual change to 64-bit mode for coreboot. It's gone > on the back burner for a bit as I'm doing a few other coreboot > things first. > > I'd love to have the help, if you have time. > > ron > > On Sun, Aug 10, 2014 at 1:02 PM, Vladimir 'φ-coder/phcoder' > Serbinenko wrote: >> On 10.08.2014 21:06, John de la Garza wrote: >>> I understand that the calling functions in 32 bit C uses the >>> stack and this is why coreboot needs to use cache as RAM. >>> Doesn't 64 bit C use registers to pass arguments to functions? >>> If this is the case why not run in 64 bit mode? >>> >>> Also, even if cache as RAM is used and a stack is available, >>> why not just build a 64 bit binary? What are the advantages >>> to using a 32 bit binary? >>> >>> >> long mode (64-bit) needs paging table in RAM. So no 64-bit for >> preram binary. For rest it's theoretically possible but it's too >> much hassle for no benefit. >> >> >> >> >> -- coreboot mailing list: coreboot@coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot > -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQEcBAEBAgAGBQJT5+iiAAoJEP9Ft0z50c+U2CsH/i5aWRH4VB4Kwa9k9P4Dl1sf NhnHlg+YBmr82oRKpCR2Dtq78J0JQKOZbc5rfy0IaROxdX6Fkr4CcTxmyqWOLEhW 8RFx03NLqjOgfyVZx8JBz21RfFOJt3YVdbGtMfrRlacucUrL09JD680iwB65Zeqy zooNe2RddsXUvTHflR13MJQoxTUCESlL7XSkNAnzjSBNkwcHisgI8oOlZBvxbzD0 WLul+mvCD15IvyeJuBOSIld1UWdRWMGqK0nUqGdaPMKqeRdwvLYPzpmEbd81YXAr 3cUXnC2sWW9h7xGv1N+IKvMjrjXwaD0czPCmZ/7wAvVlhEAzM3rOabmuvukgOuk= =l8NY -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] high-pitched whine on x60/t60
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 So far we have workarounds (idle=halt or processor.max_cstate=2 kernel parameter, or 'powertop --auto-tune'). I am fully aware that these are workarounds, not solutions. A libreboot user also reported that the following programme can be used (in the same way as powertop): https://wiki.archlinux.org/index.php/TLP Might be worth looking into. -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQEcBAEBAgAGBQJTzmktAAoJEP9Ft0z50c+UhT8H/2xXUdcJANCmZkauI6iy5ZeO DGdPp5aDoDIDP5MOkju4dMQG4tziMkdiRUcA+ZwIDND4wB3s3rmt4Q+B/h2wyF9L hCXR2u5Zv5CjXntcoNbBxO7Lcl8zyc/f9o4o1JopKkO5e1W1TTCk0bDyegD7zqAy pLQXHOhFBhbtIFkfgi8XTUVqMy0+8umXn/NcHpRxrw9s85ntY372DIbYnoVq6Gz9 Pt1b9+VtQ+ERCaaJa7nZCsSuS3FYv594FRnDLkIJiSf5hViBOQqe7JIYNca4cvi6 5phTpYp0aSeRuyOWcKneiP5/wCGRB0OYzBGfxi8gMsz4Y2QtiGs3A2HqmUz3BIo= =t9yl -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] 15.4" T60 (Intel GPU) tester needed
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Dear coreboot community, If you have one with an Intel (GMA 950) GPU and it is the 15.4" (widescreen) T60, I need testers for libreboot 6 (see details on libreboot.org homepage). Looking forward to replies! Regards, Francis Rowe. -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQEcBAEBAgAGBQJTw7d2AAoJEP9Ft0z50c+Us6IIALh/VlMVwunNhaYufm7UUZQ1 SOTsGYoGRQIWpE4gHDiXeAyqPDQ/yO3Cb6LkIvIi6vvG0o2UUl9FzDjyizbhnwkl gS2PpaZKXgW9YMPbHIf/KpEREEonMHVeGKJfHfriTEm5TWi2NHSADqSoSb57qKPg xCr0+gePNdK56LLbJ6UnTcTr2PRPl4lkhZbybNripO7Aam4gS30TenzNNiJsECUe Ewwu8ib++2gYc4XJb9au9c+LOSekVV6Sn8bb++CAMP8nBu9AH731Bj5zI/Bh60iw 88UJO5dtMM0P6B/j7ikGCNy2as7BmmOHMlQHptW90DF21M/HMiAvu+R23SWId5k= =EC3g -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] installing Coreboot to T60(MX25L1605AM2C flash chip)
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 .model_id 0x14 .probe probe_spi_res1 .write spi_chip_write_1 On 08/07/14 15:26, Peter Stuge wrote: > Martin T wrote: >> What is the correct definition of my flash chip in flashchips.c >> file? >> >> .name = "MX25L1605D/MX25L1608D", > > This one. > > >> I wasn't able to find the exact data sheet. > > Look for MX25L1605D. > > > //Peter > -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQEcBAEBAgAGBQJTvAplAAoJEP9Ft0z50c+U+gEH/jnEUD8mxiipwdHAw2hTx8TN dlnjEzNtRnjCg4zSiFPf7AUmzTyE89H47H00VOZ3nxWwfAmmKtOys5w0uzEV5kCT 34MkMv8Ogyf6dZRqeGPZcVpQOrZ4iAsdy81bSfBOIeHXMvl3q1M+PS+EeKnIgHG8 UNTptn6OAq2yXFKp46jqjJ+Ubp47ICEbOKa9qntzMbdE3MOAvnKYwSLAbt4MYfUH DVdB8dMPGLYeeSfxjM1Z9t7gDgSUBiyC0PvP5PLDURRq69lnQlFDgFjC+AJISMxq 3ZYkOtUY4V/G7B/y2zDYsCjAcCt7ybVC8W4WW5QE7ABwLyl6gDDnpndisE87LR4= =tlVy -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] PAE status/ 8Gb of ram on X60
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 What about the (rare) X60's that support 64-bit processors (T5500, T5600, T7200 and L7400) On 07/07/14 13:46, Peter Stuge wrote: > ron minnich wrote: >> Chips that could hoist memory in the, e.g., 3g-4g range up above >> 4G have been around since before the i945. Anybody know for sure >> that the i945 can or can not do this? I"m not familiar enough >> with it. > > It only has a 32-bit interface to the processor, it can't do more > than 4GB. > > i965 is the first in that series with a 64-bit interface. > > > //Peter > -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQEcBAEBAgAGBQJTupjEAAoJEP9Ft0z50c+UjNAH+gNnZBdEKhLw6gO949fCPfQO 1l0R0c3aPRIAwfFMJFA1UGEqOXRo+6HAl2GKNKNyKray/9sWZpWAjcmvrQIxgMsn 6QHA3B5WHac2GUV/l6errcmmO8ynvJaG+APvH+C9k1jKqlcGbs72LEy9o3avIHKD X9AHhGkKFwsd55Cl5KWry1UfKVypDBpHF+ZU5Ier4fXaLKcT2G4Na2JJ/ZuKzeXo qjim1r+sEurScrvgUpEMwQ0gMAxkOuvwIaeog68iSC3pK7GmA3OhfosMfTXNzj1D 8WK3u8PJz/jtY/yWkxnJZnvJiJcPiKyK6YjMRvsw5TPHNlBC8oO1vOnj+GISbYE= =Ak6Z -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [RFH] Sponsor for Lenovo X60 wanted
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 23/06/14 21:48, Paul Menzel wrote: > Dear coreboot folks, > > > in the last weeks I started working a little on the Lenovo X60 > support [1]. There are several issues like non-working 3D support > with Linux 3.12+ [2]. Also Linux 3.11+ (or earlier) is unable to > initialize the graphics device itself. > > Unfortunately I do not own such a device. Francis Rowe helped me a > lot with testing, but asking others to test does not scale, so I > am contacting you if there are some interested people to sponsor a > Lenovo X60 (preferably with a docking station for easier > debugging). I cannot give any promises of course, but am optimistic > that I can hold up to testing coreboot and Linux regressions and > hopefully get some of those fixed. > > Please contact me if you want to support that endeavor. > > > Thanks, > > Paul > > > [1] http://review.coreboot.org/5927/ [2] > http://www.coreboot.org/Board:lenovo/x60#Problems_in_native_graphics_code_exposed_by_recent_kernels > > > > Hi Paul, I still want to do the git bisect that you requested (and other tasks), I just haven't had the time lately. I am happy to send you an X60 with dock if you like. (I have plenty of spares). Regards, Francis Rowe. -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQEcBAEBAgAGBQJTqYB4AAoJEP9Ft0z50c+U5NUIAKPvOYVY3r3kdkokajFk/gXM GyWS7Uvh9Lrh9xPmyHGRmmSzrItdJ143TCApkhCc/C1BtCe8EEdVlBFrnJTieFTE ngZONhem6Z44LXvUKj0wxRccb2UBjliZtMmDYei8AnvNEq3sIWnJImzMLhOrhdIk zV1j85URY1lKYyxnf2G3vJaXdZ37uJqw1AKWSoAr/csEru+DfLOSP5LtWMmDPWuo XSSwgO9ZOxpmnP5FQCistZpv7K9oTwXus1NNBI2YtJF2Sva+DITViuEgrpIp8JQK vtAbmQtYGis0lKSh89geFijgvLd3s9sG/2+f+uiKHpdV66b2vX+OZUTwTncjJxU= =N31d -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Investigating the high pitched noise on the x60 tablet
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 sudo powertop Go to tunables. Turn everything in "tunables" to "Good" and the noise goes away. Do this without idle=halt or processor.max_cstate=2 options. This plus backlight support (see http://libreboot.org/howto.html#x60_native_notes) you can get battery life as high as on lenovo bios without any of that noise. On 09/06/14 22:56, Peter Stuge wrote: > Charles Devereaux wrote: >> I would like to investigate the whining noise issue. >> >> I have a spare motherboard that I'm setting up for studying this >> noise issue by pinpointing from which component it comes from > .. >> by default going into a power saving mode that make this noise. > > The noise is not created by a particular state. > > The noise is created by switching between states. > > I expect that the noise comes from power supply circuitry. > > Use an oscilloscope in clever ways to find the source. > > idle=halt skips all C-states. > > uhci_hcd requires the CPU to run every ms. > > Factory BIOS and coreboot have different noise. > > Thermal shutdown is fairly easy to induce when running coreboot, > but not with factory BIOS. X60 has notoriously poor thermal design, > but still there is no thermal shutdown with factory BIOS. Find > why. > > Understanding the thermal issue might be helpful for the noise > issue. > > Learn how the factory BIOS manages the CPU power states. > > You will not be able to find the documentation you may want for > this. > > > //Peter > -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQEcBAEBAgAGBQJTlqTOAAoJEP9Ft0z50c+UD40H/2JyyZshBQ+eAx0J8IkM8TCH 2obiHcIpCq5TMrJtM1DF3xOWH9lTn9edw5ooFQNUJXS1fgtWub83f4GY3mebgddW /52vtJst0SZHwbmmL8NKYzvUmdV+QYoCg75SoS2sU7mLrtclpKxYKfBINS8ykZqV vxhDBVBq0Yhn1blJkoQzxZjRL/NTej5Nn7WXiIXnEBluGa12y1xxhVAczEfUaoDZ 89U8ytMVZviYlWidxt/q7LtndYZooztpK8EdMqePx5wwlKg/Q3kL+CM3rL7ChSYe MSj/PEw8AtqYYWCNna9WnJJe4ntcCLGC4eSTyLtPyucMHZ3fh2HM+wVGTZ9MVP4= =1pFt -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Testers needed -native gpu init + backlight controls - X60 Tablet (1400x1050) and T60 14" (Intel GPU) 1400x1050
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 title says all -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQEcBAEBAgAGBQJTeI/pAAoJEP9Ft0z50c+U9KYIAL/N8z+XOWqSyemCPAiqWzdL hLa6Ye9Y7Z7SUxSlkIbarFnk1qPYO2IoFWGYGUNHG90sQT2lMAqMXuGkF9FvoXKn PtkWS73wtbhVXckafC0QkbMWyrPJ/kp9GORjaSWHGAXZn02AwrgtqwTdGWCfp+3S nbE7xpVFNikpr+6earHdUs44BVK3e3Q0Grcb/G+PTTHP4bow8vu89qcSe9mV+Gb7 DOwJEb5wLHUhAjhupQhy2zeSEjy+szUlGOEAYZITaPs0lAxt58lbmWt92iHME9uC vaYVYMGLnreUcbsmA1ZtFAEhCIUC6csSTlndG4U7i2gVBvwqI61fk2w5WnSmAHw= =8PXB -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] results (testing 5345 with oprom trace)
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Testing 5345 for phcoder. I bricked the T60. I can't see anything. 2002 git clone http://review.coreboot.org/coreboot 2003 git fetch http://review.coreboot.org/coreboot refs/changes/45/5345/1 && git checkout FETCH_HEAD 2004 cd coreboot 2005 git fetch http://review.coreboot.org/coreboot refs/changes/45/5345/1 && git checkout FETCH_HEAD 2006 wget http://minifree.org/vgarom.bin 2007 ls -l 2008 make menuconfig 2009 make (that url is where i put it to transfer it to my X60, which i used to compile the rom) then i added grub.elf to the coreboot directory here is my .config: http://paste.debian.net/100059/ (from IRC) -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQEcBAEBAgAGBQJTdn5LAAoJEP9Ft0z50c+UkL0IALo7eXnqo43QbK6/1ZSgaPHw 7yRmfoaZIqPha4O7SZfO+G8Jz8MldpAg2vvR3grsiXx2S8GCFAX5Ykuvh0+wlTQy A61qj33nAH1irCq3BOpp7ukBDv0Xn1wIcB9S5XPkGLX1FQcZEgLK7a5OJ29Dx40v JtcRpTQmvrK5gCNrBF0Ab8t+JqBjKtATCkPnGybg/64caJ3snklmDPLktSrFSJGo rzwAgxXgsB2YrjKZ3TtXwoHGDR19cYYrCllL3d19ZLylTyKrP3dyqFveNht6DAqp YyLUoHUtqKoW0NPYvUxo4s2VZHCC0fcfAYVooUlX/io2+hAXS7pb1fm93utPBGs= =YD6x -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] backlight controls working on X60 without vga option ROM (using native graphics instead)
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 tested also on X60t (1024x768). Works. samnob: can you test coreboot (with change 5320 from gerrit) and then run that command on your X60t: sudo devmem2 0xe4361254 w 0x879F879E And tell me if backlight controls (using the Fn keys) work or not? On 16/05/14 00:10, The Gluglug wrote: > phcoder and moosbart, could you also try this on your macbook21's > ? > > On 16/05/14 00:02, The Gluglug wrote: >> For T60 (Intel GPU. Mine is 15" version): sudo devmem2 >> 0xe4361254 w 0x58BF58BE > >> I read from that address using this command: sudo >> devmem2 0xe4361254 w I did that on my T60 running >> Lenovo BIOS and get this: 0x I did that on my >> T60 (same one) running coreboot with vgarom and get this: >> 0x58BF58BE With libreboot on a T60 (when native graphics >> is made to work, which at the moment it doesn't) you will instead >> do this: sudo devmem2 0xe4361254 w 0x58BF58BE >> Same address, different value (for making backlight controls work >> on the T60/intelGPU) > >> On 15/05/14 22:09, The Gluglug wrote: >>> Tested in current libreboot. should work in coreboot (using >>> changeset 5320 or a rebase). > >>> hey you! I just got backlight controls >>> working PERFECTLY on an X60, running libreboot with >>> native graphics init instead of vga oprom Fn keys, >>> that is. it'll also work in coreboot (using change set >>> 5320) how i did it: run coreboot on X60 with >>> vgarom do that to read from that address at each >>> brightness level: sudo devmem2 0xe4361254 w >>> it came back with 0x879F879E every time so then I >>> tried: sudo devmem2 0xe4361254 w 0x879F879E >>> writing 0x879F879E to address 0xe4361254 and then I >>> try the Fn keys for brightness controls on the X60 now >>> it works. brightenss controlls work this is >>> amazing. > >>> Yay! > >>> So: that address should be written with that value, by >>> coreboot, at boot time. > > > -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQEcBAEBAgAGBQJTdVm9AAoJEP9Ft0z50c+UZ9EH/jgInza5ACp/y0s30Bygcc2S TdOv4wB6XARBV4P6/YlM49YdwYcehPT80F1RLGtJg2vT+f4F7CpU3Av7SXVX3Tit p5IMrNu4wr9XdAVk8JCBYhMehZ+6dv2oOZbtYkeKeD72vrgvy5uK0IFjEgxIC2BC VyGYG/raEYjlnRbC1PStJRsCA663Wixu84GCx/nzpxTY5gLkDrrYBYwZGoV5ls8X ShGfLoO0NCGDPiO9AoqzYmqnKTXk6RlQiW4jQzVLa69sRIY+uNohPZAxcBqJG4Ci fZvpBKM91d5t5YWnoz2ebz9BgXvA3yurKjz4foWSsSdY39I6Vp7ZYwa8qsLHEhs= =mqxk -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] backlight controls working on X60 without vga option ROM (using native graphics instead)
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 phcoder and moosbart, could you also try this on your macbook21's ? On 16/05/14 00:02, The Gluglug wrote: > For T60 (Intel GPU. Mine is 15" version): sudo devmem2 0xe4361254 > w 0x58BF58BE > > I read from that address using this command: sudo > devmem2 0xe4361254 w I did that on my T60 running Lenovo > BIOS and get this: 0x I did that on my T60 (same > one) running coreboot with vgarom and get this: 0x58BF58BE > With libreboot on a T60 (when native graphics is made to work, > which at the moment it doesn't) you will instead do this: > sudo devmem2 0xe4361254 w 0x58BF58BE Same address, > different value (for making backlight controls work on the > T60/intelGPU) > > On 15/05/14 22:09, The Gluglug wrote: >> Tested in current libreboot. should work in coreboot (using >> changeset 5320 or a rebase). > >> hey you! I just got backlight controls working >> PERFECTLY on an X60, running libreboot with native >> graphics init instead of vga oprom Fn keys, that is. >> it'll also work in coreboot (using change set 5320) >> how i did it: run coreboot on X60 with vgarom >> do that to read from that address at each brightness >> level: sudo devmem2 0xe4361254 w it came back >> with 0x879F879E every time so then I tried: >> sudo devmem2 0xe4361254 w 0x879F879E writing 0x879F879E >> to address 0xe4361254 and then I try the Fn keys for >> brightness controls on the X60 now it works. >> brightenss controlls work this is amazing. > >> Yay! > >> So: that address should be written with that value, by coreboot, >> at boot time. > > -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQEcBAEBAgAGBQJTdUlYAAoJEP9Ft0z50c+UPsoH/jPo4MRBOCJhFWpn/VhFIYq4 ZCpAZA2mkOiDzmtMww+dH2Er2+Oe1sua90dTFVHOAc9V/2n8m7MKJCufXzcAl26j l0Kmr47vTJm0N5WA0SAIw8J7UJDgJOz68Qy441hDIJrpK5YnNoBHcvmUf92jRphC XZbx9/8gaaVdx016s/WnvjLuSfTYx8RhiWuNo5JQnJJzy+4ebxsS8+EChcrjDWqM zZt9IfP4+Lj7m9/jhQ8xvB+tT0YmrI6hmvJPBf7MMpjZ91vMfVPjbYr3b+idw6C4 vPiynI3zfwD4Ij/iMgC5uJDYWcOT8Ph49lPEkHFK4pNUidd+a61ELSgJXOK3X1Q= =A9tA -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] backlight controls working on X60 without vga option ROM (using native graphics instead)
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 For T60 (Intel GPU. Mine is 15" version): sudo devmem2 0xe4361254 w 0x58BF58BE I read from that address using this command: sudo devmem2 0xe4361254 w I did that on my T60 running Lenovo BIOS and get this: 0x I did that on my T60 (same one) running coreboot with vgarom and get this: 0x58BF58BE With libreboot on a T60 (when native graphics is made to work, which at the moment it doesn't) you will instead do this: sudo devmem2 0xe4361254 w 0x58BF58BE Same address, different value (for making backlight controls work on the T60/intelGPU) On 15/05/14 22:09, The Gluglug wrote: > Tested in current libreboot. should work in coreboot (using > changeset 5320 or a rebase). > > hey you! I just got backlight controls working > PERFECTLY on an X60, running libreboot with native > graphics init instead of vga oprom Fn keys, that is. > it'll also work in coreboot (using change set 5320) > how i did it: run coreboot on X60 with vgarom > do that to read from that address at each brightness > level: sudo devmem2 0xe4361254 w it came back > with 0x879F879E every time so then I tried: sudo > devmem2 0xe4361254 w 0x879F879E writing 0x879F879E to > address 0xe4361254 and then I try the Fn keys for > brightness controls on the X60 now it works. > brightenss controlls work this is amazing. > > Yay! > > So: that address should be written with that value, by coreboot, > at boot time. > -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQEcBAEBAgAGBQJTdUeMAAoJEP9Ft0z50c+UVysH/jXBWLuPqnkDpWYcwYbqxuUC NsgLkkKXI8LH4q1vukx5qXrBwLsqAftFHy1n3ez8o3j0b2Uoniv18gdD5CSjymOm gBXX40f/En9MLQ93ZAHG92CH6VWumzfOtXvKRQ2yraHuaWcwHusbPUBMx0SdzSH1 k2OSTSHIi1bbbZ5VQiyJ5THIsZyG7d1uyIMI9cDcXGHaiSiYv2rHKscnZJmTFL// v6FXGZOlC+CmRb3L8aqChOC+sCS/0qGXgjuCRJjPaTJ2x1IxkjmMHHrRUidRNNxL kZ0s1cil0rTZzdj5EE8kc0a1tVpEhy7DkovEXRKijFc0ctqd8NPoChUKH/Ww3Ew= =jpXc -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] backlight controls working on X60 without vga option ROM (using native graphics instead)
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Tested in current libreboot. should work in coreboot (using changeset 5320 or a rebase). hey you! I just got backlight controls working PERFECTLY on an X60, running libreboot with native graphics init instead of vga oprom Fn keys, that is. it'll also work in coreboot (using change set 5320) how i did it: run coreboot on X60 with vgarom do that to read from that address at each brightness level: sudo devmem2 0xe4361254 w it came back with 0x879F879E every time so then I tried: sudo devmem2 0xe4361254 w 0x879F879E writing 0x879F879E to address 0xe4361254 and then I try the Fn keys for brightness controls on the X60 now it works. brightenss controlls work this is amazing. Yay! So: that address should be written with that value, by coreboot, at boot time. -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQEcBAEBAgAGBQJTdS0UAAoJEP9Ft0z50c+UdmkH/3G+I7NzMEWoTofSKVu3fUv4 DtoYhozX5GW7lnHGSoddgtn7SmYAtbbDucAZniXwfluRSpl/g44yTwKbvMh0So5O +zM3LED/f6NNifgmH3jTn8Shz2EsqN3medC8kKi912EpEhMhbvUlW3FoRkXMrCOM 7QXkJFbnh/zN0sJ3ffDJ0B1ZFkPSHIAfdkIljDL83RCHz+TZ9vXzjS2BKcFgXwOp 6MrdHaMrO1PtRl+XHCg4k0a/ego00LUjE5fP8cZRfL1vXTPya7KibCiOomlhs5/w kAPMHXy4G+nfrB1x/NtCW0LysmadasXylxPlNGwrrCKAsiI6BrpowQMOiSWcVIc= =Aaz0 -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] x60 unbricking guide
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 14/05/14 20:49, The Gluglug wrote: > http://libreboot.org/tutorial/x60_unbrick.html > > Based on the one at: > http://libreboot.org/tutorial/x60_unbrick.html > > Suggestions are welcome... > er; based on www.coreboot.org/Board:lenovo/x60/Installation#Recovery -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQEcBAEBAgAGBQJTc8jXAAoJEP9Ft0z50c+U8XQH/3gMPzh6UFZXudmhN8U+ik20 oEtIuljbo4QAkJ8RhSSR6YpOpAwpAFd/+E9YAEQ4DWha1W9SqnCOfaL2mpIxrRXV 8vFxOqnCe40Howbin1bQ1dRVbXnk3hkcVphTcHGjfuSxvfos06pl9YZQ1b6tFzRt 0iQbb5xXahN9wUcY+80vTv4o+NavvaENQOFukAwVy5Z9xWhYk/Wn1L8TvxejFFU1 yxmJmp0nDFoyCr/ARiP54vpTIAIK9EGQ9EluzQRkyfmQ1pqH48aqMbWp15bTcdZQ AlVVoN5i7Jg31SKAw3+HxWTQCoT4yK2vjktaFJZd8d+rMgrUqXSUgIPAsMNSCxk= =rxS3 -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] x60 unbricking guide
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 http://libreboot.org/tutorial/x60_unbrick.html Based on the one at: http://libreboot.org/tutorial/x60_unbrick.html Suggestions are welcome... -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQEcBAEBAgAGBQJTc8i4AAoJEP9Ft0z50c+Umv8H/0DI2a8dnh8LbW3H86gqhhn4 jQb0JioPfXpniFkLikOXi654vQA5j93/ruzgyy4psU9535d3X8hiUrXZKpBlnt1L VlZn8CwKfG5NioO07XmakIqHMFHnsjVwxR/MHbDSUBHx+M18+tfeql2GfcoArGlp s5YlgLSOs95eH4Y52JTLsGt77Wlr5c4CGSJM67HFt/EsxoXMQ6gh1ltO+thfTSxl HCl+e+ThVMXLKH+YndKkptA66ct4GHMqqfA8g5wp1zuJ003PR+pYJ7sQlK4gPB3d dXNAk+dYF8woLr+S55u0+M0MbxpA5ZBc9KJXMgjUWhxE8NFoAo4caMv2YOHOf0Y= =YJuq -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Thinkpad X61
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 If you already have an X61, you can swap out the motherboard. Find a motherboard for the X60s, if you have an X61s. Find a motherboard for the X60 or X60s, if you have an X61. (if using X60s board in X61 chassis, make sure to use the bigger X60/X61 heatsink/fan). Then you have an X60/X60s, albeit with an X61/X61s case. On 13/04/14 22:50, Carl-Daniel Hailfinger wrote: > Hi mad, > > someone who has experience porting chipsets could add support for the > i965 chipset with maybe 6-12 months of fulltime work. This is of course > under the (unlikely) assumption that full documentation is available. If > you're doing it as a hobby and have to learn firmware development first, > I expect 4 years of spare time, maybe more. > After that porting to the Thinkpad x61 would be relatively easy. > > For more info see > http://www.coreboot.org/pipermail/coreboot/2011-July/065973.html > > Regards, Carl-Daniel > -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQEcBAEBAgAGBQJTTAbOAAoJEP9Ft0z50c+UFJAH/2tf8YDtm+TFUPkwEch3fDg/ oAXFcg1t2DHMYgr+Sj5nyzR2PBbZqiwTa8eW6M4Cp3w/M7xLD+Tb27EEBGGUMJ9U AFz17585QyY8D5xt7Ic/ex2ePTVbkAd410gASYx2ti8Qkp/9ZjnacNFrYEv5pgw5 eMJ+yKdeLQC25TjGRe6Gz3iyGDBU4MYAi+74YLQ5kJclxdfRKahRih90ymGgJZJe XPlbAvNo9x+4Sh5Bteh5HXL14UYolUnGycB/kUQfSaWJQfBbSl3xqoVe9l6tBVzQ UTapyLisruF27lYQvuqPn6IGIT2/eyoWxGmCDh638XqDEBrsbTd/2cSTXY2xQ8M= =hT0q -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Miniboot
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 - --> alternatively: ship coreboot without anything in src/mainboard. have git repositories for each vendor/mainboard. user downloads what they need, and a default .config for the board of their choosing. On 25/03/14 23:29, The Gluglug wrote: > This is focussed on users (non-developers). > > Most coreboot users only have perhaps a few machines that they are > building for. Maybe even just one. > > Yet they are downloading the entire coreboot source tree and > selecting which board they want, configuring it, etc. > > My idea: --> a small set of source files (such as from > src/mainboard/vendor/board) --> a script (perhaps a simple git > checkout) which fetches the needed parts of the source from the > main branch, for building that board --> default/"sane" > configurations pre-defined for that board. > > Advantages: --> less headache for developers (user already has most > of what they need, less likely to request support) --> less to > download (less waiting required, especially for people with slow > connections) > > Essentially, I have in mind a more "modular" coreboot. > -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQEcBAEBAgAGBQJTMhIzAAoJEP9Ft0z50c+UHuYH/12yONytbAEMfmJ2erNUYLSG yimowCAGTAMndkrTC6NP5yOjUEZhUIFZD4zB6PvjVyIAo8OMilphrTpwTU/ZJB0r gqGPS7mieLbt6SfX3rA5n9B9Nqf5ijvHob2p9/1XPiVqyb1mmur0W+LEXd3ESWv3 Jtpo7jSqYg73NB4QBlHDNqYBH1bxIaqGNOSXjvgpnQgORTkC2yob7eTi8GV9gYBE UvdLFz0BfOgmzrtGpXLiDy0UFbU1BVeOTMrBJLiiZvjzNmhZAlp7XCFrWz8uH+yC hF+j3LCgrejGHPmakONia00hjctSocUZzec+ALVMqs96B2CEUiRbgGP0AwUyMk0= =938K -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Miniboot
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 This is focussed on users (non-developers). Most coreboot users only have perhaps a few machines that they are building for. Maybe even just one. Yet they are downloading the entire coreboot source tree and selecting which board they want, configuring it, etc. My idea: --> a small set of source files (such as from src/mainboard/vendor/board) --> a script (perhaps a simple git checkout) which fetches the needed parts of the source from the main branch, for building that board --> default/"sane" configurations pre-defined for that board. Advantages: --> less headache for developers (user already has most of what they need, less likely to request support) --> less to download (less waiting required, especially for people with slow connections) Essentially, I have in mind a more "modular" coreboot. -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQEcBAEBAgAGBQJTMhFiAAoJEP9Ft0z50c+UTjYIAMXvzhJFEcrNACgqssRfZpzf Xa3C1WaAI/EByzVl11i2eSFaKipqqzCD/DkHwqroXbszNATqgKXMoYGTy/lSM7zr j/254QlxMEwd5MA6hmzrJEFFRUW2t/wYGsS48NP5R3YSJlE9Fga1ogvQJg4qgduP pFmy1i48R+I5O7/SRmaPz1Tprw+q0KaaSF5+elh8Ymq5Zq6zJTu/DSI/mNM6FUjs VOP+bmq2Yiik8DmgVUjhKKpShd2GIhXatRYSjD5otnBgO9kOss+HXvNnGmRd01YU I9Fbne1VhOruI3qS8tMmKWcLvbipyoaQ9QgpL+OuotiBdAqufMjvfT7cC9idv0g= =5YKe -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [announce] coreboot for the 21st century
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Regarding name for community branch (for maintaining old boards). On 20/03/14 21:33, Stefan Reinauer wrote: > Suggested name: “coreboot-community-2014” or “coreboot-v4.0”. Oldboot. -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQEcBAEBAgAGBQJTLj14AAoJEP9Ft0z50c+UFHoH/3jQI8NoQig3c/awn75AZlLb D0WHy0IHsrVdi23+SpAB4rwo5rQe0/c+cjAxujGjpuHDfxXHABnI235as8An1q83 JYQ55dRtTB+bOLsf+Oa3/xKhR/VRUm7JKNmo7HM9bL+K0u9xMJfxWt9uwJ2rNssE rX55Z66jN1groIVqK56I+dydVy0dn66sxaeUPxzF10nbFLUiH+LcITLn0fzLNwHS GO7+zVGCvI5mU7AwD4Dr8pJ4HJLk6kJBQJv461KEhjq26SZrND2LDuneNFSt2Emv 2hL1kT9BXhJdbECUToBGbTy3AVYbfJV2jXmVfKQgKxWYy0vPhr7Ble/YF/odIws= =G+E3 -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] T60 - what went wrong?
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Hi Marcus On 07/03/14 23:28, The Gluglug wrote: >> >>>> Is there perhaps a prebuild image for initial flashing >>>> available, that I could use? >> >> Not really no. :\ >> >> >> //Peter >> samnoble.org/thinkpad (there are some pre-built ROM's there for T60). (these are not built by me) (these use the VGA ROM. Something to keep in mind) I'll be completing those tests that phcoder wanted me to do with his patch for native graphics (VGA ROM replacement), and compiling a detailed log of my findings. (I plan on uploading my own T60 images to libreboot.org) Regards, Francis Rowe. -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQEcBAEBAgAGBQJTGldXAAoJEP9Ft0z50c+UTyoH/Rg8sUgJebVNSetNbzGhsMNh /FUcQ+2vOv3l2sZQ/nZT2sdx118OCf5rUCvcDlbOXwhEKj34gwiYK4szhgP72dnr qdEt33ieGAhJKx3Gi/WkiNCgII1ItPtkHOLhuRSHh0QGkJ1JmR15JLrljQAbo+CM SBjduP+QR27rbazacPtoObdqWXumgN0x5UID7vyKmgZ+e6OdkTkVJ3Nizy3jw5th emUrW/UahLkqSGr7x/QYXuBduLTzbZHrFN/aQklS6xI0tl3/QGECHIpeo0Q8fMBg ziwq8BhCzk/OoF7RqTEd5CPnnlVTmwHW3FpvyM6DGA0Iv8HD6CfYbLr196XnpPY= =nN+m -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] T60 - what went wrong?
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Note: those ROM's on samnoble.org are not dd'd as per coreboot wiki. Only flash them as-is if you already have coreboot, with bucts set to 0. Otherwise, dd them as per coreboot wiki: dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x1] count=64k dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x2] count=64k | hexdump dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s coreboot.rom) - 0x2] count=64k conv=notrunc On 07/03/14 23:33, The Gluglug wrote: > Hi Marcus > > On 07/03/14 23:28, The Gluglug wrote: >>> >>>>> Is there perhaps a prebuild image for initial flashing >>>>> available, that I could use? >>> >>> Not really no. :\ >>> >>> >>> //Peter >>> > > samnoble.org/thinkpad (there are some pre-built ROM's there for > T60). (these are not built by me) > > (these use the VGA ROM. Something to keep in mind) > > I'll be completing those tests that phcoder wanted me to do with > his patch for native graphics (VGA ROM replacement), and compiling > a detailed log of my findings. (I plan on uploading my own T60 > images to libreboot.org) > > Regards, Francis Rowe. > -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQEcBAEBAgAGBQJTGlg3AAoJEP9Ft0z50c+UGTkIAIgz4iFfkBoxI5myc5iPHuHH z9qXFoT5NCkXLv80Pn657kn+wNDIMB2yzZoVEPrjztz7CpXZMZV4sGzLdObtkT6+ tz5OW0bLy/1V6gC31GwXS2rS6PrDkuhVatlj79Kur01kF+SHpWsnA742PIUgeWuX a9TZRg6E+sSkjF4bM6Z/D9wiLIQOQEuz/AZ350dCWRHMkGhTEyKWRb9CLvZhwfyD PwOLRdCqdhhwMohTbfL5lgec+nyE/SqOhQYS/S5U+8BCPlwW73scKe7jAD0x3BRh 23rimvqPEWxl++HIfoR9Osb6Dl0uljzJ4sJ50JYu7+hO6zg9OEbLox0HzfJN1GQ= =woeN -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] stylus support on x60 tablet
Hi, I'm gathering information as per request on behalf of an existing x60t user (he does not yet have coreboot). He wonders, if work is being done to support the stylus function on an x60 tablet machine. If no work is currently being done (and noone is interested) he wonders who would be able to implement it regardless (he is happy to pay for this to be done). The wiki mentions that this is "WIP" but does not seem to link to any relevant information. It does link here http://forum.bongofish.co.uk/index.php?topic=2307.0 and here http://www.thinkwiki.org/wiki/Wacom_Serial_Tablet_PC_Stylus which seems to contain some information. The first link seems to show some datasheets/schematics. Who should I contact regarding further development? -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] 2508-A65 X60s
Basically: to let coreboot community know of this edge case. I have reasons to believe coreboot will work, and that after coreboot is installed flashrom will work (but that for this revision, external flashing is initially required). I will let the community know of my findings. On 13/01/14 05:26, Peter Stuge wrote: The Gluglug wrote: Is it an X60s? Apparently so, but flashrom does not seem to support it. So why post to the coreboot list? Did you look into the flashrom source? I changed the entries accordingly for either Macronix or SST. Lenovo site says X60s, DMI (according to flashrom) says it's a T43p. Neither is a very reliable source. What does the mainboard say? //Peter -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] 2508-A65 X60s
root@user-ThinkPad-X60:~# lspci -tvnn -[:00]-+-00.0 Intel Corporation Mobile 945GM/PM/GMS, 943/940GML and 945GT Express Memory Controller Hub [8086:27a0] +-02.0 Intel Corporation Mobile 945GM/GMS, 943/940GML Express Integrated Graphics Controller [8086:27a2] +-02.1 Intel Corporation Mobile 945GM/GMS/GME, 943/940GML Express Integrated Graphics Controller [8086:27a6] +-1b.0 Intel Corporation NM10/ICH7 Family High Definition Audio Controller [8086:27d8] +-1c.0-[02]00.0 Intel Corporation 82573L Gigabit Ethernet Controller [8086:109a] +-1c.1-[03]00.0 Intel Corporation PRO/Wireless 3945ABG [Golan] Network Connection [8086:4227] +-1c.2-[04-0b]-- +-1c.3-[0c-13]-- +-1d.0 Intel Corporation NM10/ICH7 Family USB UHCI Controller #1 [8086:27c8] +-1d.1 Intel Corporation NM10/ICH7 Family USB UHCI Controller #2 [8086:27c9] +-1d.2 Intel Corporation NM10/ICH7 Family USB UHCI Controller #3 [8086:27ca] +-1d.3 Intel Corporation NM10/ICH7 Family USB UHCI Controller #4 [8086:27cb] +-1d.7 Intel Corporation NM10/ICH7 Family USB2 EHCI Controller [8086:27cc] +-1e.0-[15-18]--+-00.0 Ricoh Co Ltd RL5c476 II [1180:0476] | +-00.1 Ricoh Co Ltd R5C552 IEEE 1394 Controller [1180:0552] | \-00.2 Ricoh Co Ltd R5C822 SD/SDIO/MMC/MS/MSPro Host Adapter [1180:0822] +-1f.0 Intel Corporation 82801GBM (ICH7-M) LPC Interface Bridge [8086:27b9] +-1f.1 Intel Corporation 82801G (ICH7 Family) IDE Controller [8086:27df] +-1f.2 Intel Corporation 82801GBM/GHM (ICH7-M Family) SATA Controller [AHCI mode] [8086:27c5] \-1f.3 Intel Corporation NM10/ICH7 Family SMBus Controller [8086:27da] (on the 2508-A65) root@computer:~# lspci -tvnn -[:00]-+-00.0 Intel Corporation Mobile 945GM/PM/GMS, 943/940GML and 945GT Express Memory Controller Hub [8086:27a0] +-02.0 Intel Corporation Mobile 945GM/GMS, 943/940GML Express Integrated Graphics Controller [8086:27a2] +-02.1 Intel Corporation Mobile 945GM/GMS/GME, 943/940GML Express Integrated Graphics Controller [8086:27a6] +-1b.0 Intel Corporation NM10/ICH7 Family High Definition Audio Controller [8086:27d8] +-1c.0-[01]00.0 Intel Corporation 82573L Gigabit Ethernet Controller [8086:109a] +-1c.1-[02]00.0 Qualcomm Atheros AR9285 Wireless Network Adapter (PCI-Express) [168c:002b] +-1c.2-[03]-- +-1c.3-[04]-- +-1d.0 Intel Corporation NM10/ICH7 Family USB UHCI Controller #1 [8086:27c8] +-1d.1 Intel Corporation NM10/ICH7 Family USB UHCI Controller #2 [8086:27c9] +-1d.2 Intel Corporation NM10/ICH7 Family USB UHCI Controller #3 [8086:27ca] +-1d.3 Intel Corporation NM10/ICH7 Family USB UHCI Controller #4 [8086:27cb] +-1d.7 Intel Corporation NM10/ICH7 Family USB2 EHCI Controller [8086:27cc] +-1e.0-[05-09]--+-00.0 Ricoh Co Ltd RL5c476 II [1180:0476] | +-00.1 Ricoh Co Ltd R5C552 IEEE 1394 Controller [1180:0552] | \-00.2 Ricoh Co Ltd R5C822 SD/SDIO/MMC/MS/MSPro Host Adapter [1180:0822] +-1f.0 Intel Corporation 82801GBM (ICH7-M) LPC Interface Bridge [8086:27b9] +-1f.1 Intel Corporation 82801G (ICH7 Family) IDE Controller [8086:27df] +-1f.2 Intel Corporation 82801GBM/GHM (ICH7-M Family) SATA Controller [AHCI mode] [8086:27c5] \-1f.3 Intel Corporation NM10/ICH7 Family SMBus Controller [8086:27da] (on an 1702-37G) On 13/01/14 03:08, The Gluglug wrote: Is it an X60s? Apparently so, but flashrom does not seem to support it. sudo ./flashrom -p internal -V Internal programmer initialization failed (see [1], no modifications made to flashrom). I changed the entries accordingly for either Macronix or SST. Lenovo site says X60s, DMI (according to flashrom) says it's a T43p. (testing now with external programmer) [1] flashrom v0.9.7-r on Linux 3.2.0-38-generic-pae (i686) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.1.8, GCC 4.6.3, little endian Command line (3 args): ./flashrom -p internal -V Calibrating delay loop... OS timer resolution is 2 usecs, 1021M loops per second, 10 myus = 12 us, 100 myus = 109 us, 1000 myus = 1076 us, 1 myus = 9577 us, 8 myus = 9 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "LENOVO" DMI string system-product-name: "2508A65" DMI string system-version: "ThinkPad T43p" DMI string baseboard-manufacturer: "LENOVO" DMI string baseboard-product-name: "2508A65" DMI string baseboard-version: "Not Available" DMI string chassis-type: "Notebook" Laptop detected via DMI.
[coreboot] 2508-A65 X60s
Is it an X60s? Apparently so, but flashrom does not seem to support it. sudo ./flashrom -p internal -V Internal programmer initialization failed (see [1], no modifications made to flashrom). I changed the entries accordingly for either Macronix or SST. Lenovo site says X60s, DMI (according to flashrom) says it's a T43p. (testing now with external programmer) [1] flashrom v0.9.7-r on Linux 3.2.0-38-generic-pae (i686) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.1.8, GCC 4.6.3, little endian Command line (3 args): ./flashrom -p internal -V Calibrating delay loop... OS timer resolution is 2 usecs, 1021M loops per second, 10 myus = 12 us, 100 myus = 109 us, 1000 myus = 1076 us, 1 myus = 9577 us, 8 myus = 9 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "LENOVO" DMI string system-product-name: "2508A65" DMI string system-version: "ThinkPad T43p" DMI string baseboard-manufacturer: "LENOVO" DMI string baseboard-product-name: "2508A65" DMI string baseboard-version: "Not Available" DMI string chassis-type: "Notebook" Laptop detected via DMI. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
