Re: [coreboot] how to assign irq to a device
External PCI network adaptor? If it is plugged in PCI slot so it is internal. Is it a LAN card plugged into USB slot? On Wed, Oct 10, 2012 at 2:41 PM, WANG Siyuan wangsiyuanb...@gmail.com wrote: hi, i am debugging a mainboard with an external pci network adapter. the adapter share irq with usb. it seems not correct, so i want to assign an irq for this adapter. how to do that? thank you. /proc/interrupt eth1 is an external pci network adapter. i want to assign irq 21 for it. CPU0 CPU1 CPU2 CPU3 CPU4 CPU5 CPU6 CPU7 0: 59 0 0 0 0 0 0 0 IO-APIC-edge timer 1: 0 0 1 0 1 1 0 0 IO-APIC-edge i8042 7: 1 0 0 0 0 0 0 0 IO-APIC-edge 8: 0 0 0 0 0 0 0 0 IO-APIC-edge rtc0 9: 0 0 0 0 0 0 0 0 IO-APIC-fasteoi acpi 12: 0 0 0 1 1 0 1 1 IO-APIC-edge i8042 14: 0 0 0 0 0 0 0 0 IO-APIC-edge pata_atiixp 15: 0 0 0 0 0 0 0 0 IO-APIC-edge pata_atiixp 16: 93 95 80 91 96 94 98 97 IO-APIC-fasteoi ohci_hcd:usb3, ohci_hcd:usb4 17: 1 0 1 0 0 0 0 0 IO-APIC-fasteoi ehci_hcd:usb1 18: 4 4 4 4 4 4 2 4 IO-APIC-fasteoi ohci_hcd:usb5, ohci_hcd:usb6, ohci_hcd:usb7 19: 1 1 0 0 0 0 0 0 IO-APIC-fasteoi ehci_hcd:usb2, eth1 22:672685691692693683 687681 IO-APIC-fasteoi ahci 296:119 99127 87125 96 121105 PCI-MSI-edge eth0-rx-0 297: 0 0 0 0 0 0 0 0 PCI-MSI-edge eth0-tx-0 298: 1 0 0 0 0 0 0 0 PCI-MSI-edge eth0 299:123125105138 93135 106132 PCI-MSI-edge eth2-rx-0 300: 2 4 4 0 1 2 1 3 PCI-MSI-edge eth2-tx-0 301: 0 0 1 0 0 0 0 2 PCI-MSI-edge eth2 NMI: 0 0 0 0 0 0 0 0 Non-maskable interrupts LOC: 4050 1673 3943 2348 2519 2963 3093 1644 Local timer interrupts SPU: 0 0 0 0 0 0 0 0 Spurious interrupts PMI: 0 0 0 0 0 0 0 0 Performance monitoring interrupts IWI: 0 0 0 0 0 0 0 0 IRQ work interrupts RTR: 0 0 0 0 0 0 0 0 APIC ICR read retries RES: 5454 4177 5477 3690 5121 3822 5342 3630 Rescheduling interrupts CAL: 44 58 52 57 46 56 50 59 Function call interrupts TLB:291391291336274344 237395 TLB shootdowns TRM: 0 0 0 0 0 0 0 0 Thermal event interrupts THR: 0 0 0 0 0 0 0 0 Threshold APIC interrupts MCE: 0 0 0 0 0 0 0 0 Machine check exceptions MCP: 6 6 6 6 6 6 6 6 Machine check polls ERR: 1 MIS: 0 -- WANG Siyuan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] First ROM Image
Your host developing machine can be a modern i5. but Coreboot uses a special gcc for the BIOS code. Just add the necessary paths as a prefix in .xcompile file like AS:=/root/bios/coreboot/util/crossgcc/xgcc/bin/i386-elf-as But i wrote assembly language from scratch and i used gcc -march and -mtune options for Pentium III and it worked well. On Sat, Sep 15, 2012 at 10:35 AM, Rex O'Regan rexorega...@yahoo.com.au wrote: I have a MSI MS-6163 based rig that is currently not doing much except collecting dust and I am looking at putting coreboot on it as I want to get involved with this project in some way. The mobo is not supported as such, however the models either side of it are and the northbridge, southbridge and super I/O are all supported. Northbridge: Intel 82443BX Southbridge: Intel 82371EB Super I/O: Winbond W83977EF I have a few questions regarding the compilation and flashing of the coreboot image. Can I compile it on a newer faster computer?(i5 rather than PIII) How do I set the Northbridge, Southbridge and Super I/O for compilation? The BIOS chip is in a socket so if I brick the machine all I need to do is remove the chip and program it again from a separate computer? That's all for now... Cheers, Rex -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] memory
If the CPU wb (write back) cache is enabled for the memory range, ramstage() is OK. But CPU can not work with UC(uncached) memory type in Coreboot code. If i define the whole memory un-cached right before jumping to ramstage code ( cbfs_and_run()), CPU does not execute C_start.S and it is actually restarted! Any clue or idea will be much appreciated. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] List of possible porting targets
There may be no need to have socketed flash chip! My board did not have but one company managed to remove PLCC chip and soldered a PLCC socket for me easily and cheaply. On 4/30/12, Paul Menzel paulepan...@users.sourceforge.net wrote: Dear coreboot folks, since it is also quite a lot of work to find an appropriate board to port coreboot easily to (socketed flash chip, no embedded control), I think it would be a good to have such a list. The Wiki is probably a good place, but not all people want to request an account just for this. Therefore I think a thread on this list is good enough for this purpose. So if you find some board and you make some discoveries please reply to this message and report your findings. Thanks, Paul -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] ASUS M2V problems
As far as I know Coreboot can not drive VGA and monitor by itself. There is not enough code to do that and nothing is displayed on monitor when you run Coreboot only. It only sets up some parameters regarding to VGA which will be used by Linux kernel later. When you use FILO as a payload, your key-presses may be detected like ESC button though i did not test it myself but I found some keyboard manipulating code On Mon, Apr 23, 2012 at 5:16 PM, G tjmad...@gmail.com wrote: On Mon, Apr 23, 2012 at 12:33 PM, ali hagigat hagigat...@gmail.com wrote: You'd better buy a debug card and plug into the PCI slot and see what numbers it will display. It has two seven segment components. Besides you can disable coreboot post codes and insert your own post codes to see how far the program runs. I did the same for my motherboard... Thanks, but as I wrote on April 13th, I have managed to get some output over serial, but still nothing on VGA or any response to keyboard events. Details, and serial log and config file, can be found in my April 13th message. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] ASUS M2V problems
You'd better buy a debug card and plug into the PCI slot and see what numbers it will display. It has two seven segment components. Besides you can disable coreboot post codes and insert your own post codes to see how far the program runs. I did the same for my motherboard... On Wed, Apr 11, 2012 at 1:18 PM, G tjmad...@gmail.com wrote: On Tue, Apr 10, 2012 at 5:26 PM, Marc Jones marcj...@gmail.com wrote: On Tue, Apr 10, 2012 at 7:37 AM, G tjmad...@gmail.com wrote: Hi, I'm trying to get coreboot onto my old ASUS M2V (rev. 1.01g) motherboard, but so far I've had no luck. I'm currently trying to get the coreinfo payload running, as that seems like the simplest test case (I've also tried seabios, and failed). After flashing, when I boot, nothing happens. No beeps, the monitor remains in power-save mode, the keyboard doesn't respond to any keypresses (not even holding down several keys for a long time generates any beeps), no blinking status LEDs, nothing on the serial port. Nothing. I've tried with two different revisions, one from 2010-11-24 (the one that adds S3 support for ASUS M2V), and one from 2012-02-21 (all later revisions fail to compile with lots of different CBMEM problems). In the 2010-11-24 revision, I've had to add reg++; reg--; in src/northbridge/amd/amdk8/raminit_f_dqs.c:setup_mtrr_dqs() and regm3++; regm3--; in src/southbridge/via/vt8237r/vt8237_ctrl.c:vt8237_cfg() to get rid of warnings about unused variables. Flashing is done by simply running: ./flashrom -V -w coreboot.rom -c W39V040C Does anyone here have any idea what might be wrong? Anyone got a working .config, tips to use a certain known working revision, a know working version of flashrom (although flashing two different versions of ASUS's BIOS using flashrom works well, so I'm guessing neither flashrom nor my usage of it is to blame), a working coreboot.rom they can share, or anything else that might help me move forward? Using Debian unstable to build, if that's any help. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot Hi, You will need to capture some output from coreboot to find where your system is having problems. http://www.coreboot.org/FAQ#How_do_I_use_a_null-modem_cable_to_get_coreboot_debugging_output_over_a_serial_port.3F Thanks for the reply, but unfortunately, as I wrote in my original mail, I get nothing on the serial port. When I boot the standard ASUS M2V BIOS, with a null-modem cable plugged in, then exactly as I power on the M2V system, minicom on the other end briefly (less than a second) switches from Offline to Online, and then back to Offline, and then the system continues to boot. Booting coreboot, minicom switches from Offline to Online exactly when I power on the M2V system, and then the minicom status on the other machine remains Online, but nothing ever arrives in the minicom terminal window, and nothing else happens (no beeps, not LEDs, nothing on the screen, just plain nothing). I have tested that the minicom connection over null-modem cable between my M2V computer and the other machine works after booting the standard ASUS M2V BIOS, although I then have HW flow control enabled, which is then disabled before trying to boot the coreboot BIOS. And yes, I have checked the serial port settings in the coreboot config and they are set to the correct values. So, anyone got a working .config and/or working coreboot.rom I can try? A known working coreboot revision I should download and compile? Or any other tips/pointers? -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] porting Coreboot to a new motherboard....
Thank you, Ron, for the reply. I have checked RAM by one assembly code i developed, the whole code has been written by myself(it is not Coreboot). I tested RAM , particularly the first 5 mega bytes by read/write cycles and mov instructions. I even had a serial port code in EPROM , i copied that to RAM and jumped to execute it and it was OK. Besides I checked RAM by ramcheck() function of Coreboot. I will test it finally by memtest(). But i am believing that the problem is some where else. I remember when i ported my RAM initialization code, hardwaremain() could not be run. The problem was not RAM, it was CPU! i chaned c_start() a bit to solve the problem. What do you mean by earlyprintk(), do you suggest to change linux kernel to monitor it? Regards -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Fwd: porting Coreboot to a new motherboard....
- Forwarded message --
From: ali hagigat hagigat...@gmail.com
Date: Wed, Mar 28, 2012 at 4:58 PM
Subject: Re: [coreboot] porting Coreboot to a new motherboard
To: Kyösti Mälkki kyosti.mal...@gmail.com
Dear Kyösti
I just added 10 nop assembly command(no operation)!
10 because the number of the Pentium III pipeline stages is 10.
Very simple and strange. After adding that, each time hardwaremain()
got executed and the code continued loading FILO.
Now another strange thing (and a similar work i saw before when i was
working on hardwaremain()):
I add some nop like:
asm(nop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop);
to the start_linux() function of FILO ( in linux_load.c) and switch.S
as follows:
static int start_linux(uint32_t kern_addr, struct linux_params *params)
{
struct segment_desc *linux_gdt;
struct context *ctx;
#ifdef VGA_CONSOLE
extern int cursor_x, cursor_y;
#endif
#ifdef PCMCIA_CF
uint32_t cf_bar;
int i;
#endif
asm(nop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop);
ctx = init_context(phys_to_virt(STACK_LOC), 4096, 0);
asm(nop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop);
/* Linux expects GDT being in low memory */
linux_gdt = phys_to_virt(GDT_LOC);
asm(nop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop);
memset(linux_gdt, 0, 13*sizeof(struct segment_desc));
asm(nop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop);
/* Normal kernel code/data segments */
linux_gdt[2] = gdt[FLAT_CODE];
asm(nop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop);
linux_gdt[3] = gdt[FLAT_DATA];
asm(nop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop);
/* 2.6 kernel uses 12 and 13, but head.S uses backward-compatible
* segments (2 and 3), so it SHOULD not be a problem.
* However, some distro kernels (eg. RH9) with backported threading
* patch use 12 and 13 also when booting... */
linux_gdt[12] = gdt[FLAT_CODE];
asm(nop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop);
linux_gdt[13] = gdt[FLAT_DATA];
asm(nop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop);
ctx-gdt_base = GDT_LOC;
asm(nop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop);
ctx-gdt_limit = 14*8-1;
asm(nop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop);
ctx-cs = 0x10;
asm(nop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop);
ctx-ds = 0x18;
asm(nop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop);
ctx-es = 0x18;
asm(nop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop);
ctx-fs = 0x18;
asm(nop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop);
ctx-gs = 0x18;
asm(nop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop);
ctx-ss = 0x18;
asm(nop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop);
/* Parameter location */
ctx-esi = virt_to_phys(params);
asm(nop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop);
/* Entry point */
ctx-eip = kern_addr;
asm(nop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop);
debug(eip=%#x\n, kern_addr);
asm(nop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop);
printf(Jumping to entry point...\n);
asm(nop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop);
#ifdef VGA_CONSOLE
/* Update VGA cursor position.
* This must be here because the printf changes the value! */
params-orig_x = cursor_x;
asm(nop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop);
params-orig_y = cursor_y;
#endif
#ifdef PCMCIA_CF
cf_bar = phys_to_virt(pci_read32(PCI_ADDR(0, 0xa, 1), 0x10));
for( i = 0x836 ; i 0x840 ; i++){
*(unsigned char *)(cf_bar+i) = 0;
}
#endif
/* Go... */
asm(nop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop);
ctx = switch_to(ctx);
/* It's impossible but... */
printf(Returned with eax=%#x\n, ctx-eax);
return ctx-eax;
}
__switch_context:
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
/* Save everything in current stack */
pushfl /* 56 */
pushl %ds /* 52 */
pushl %es /* 48 */
pushl %fs /* 44 */
pushl %gs /* 40 */
pushal /* 8 */
subl $8, %esp
movw %ss, (%esp) /* 0 */
sgdt 2(%esp) /* 2 */
#if 0
/* Swap %cs and %eip on the stack, so lret will work */
movl 60(%esp), %eax
xchgl %eax, 64(%esp)
movl %eax, 60(%esp)
#endif
/* At this point we don't know if we are on flat segment
* or relocated. So compute the address offset from %eip.
* Assuming CS.base==DS.base==SS.base.
*/
call 1f
1: popl %ebx
subl $1b, %ebx
/* Interrupts are not allowed... */
cli
/* Current context pointer is our stack pointer */
movl %esp, %esi
/* Normalize the ctx pointer */
subl %ebx, %esi
/* Swap it with new value */
xchgl %esi, __context(%ebx
Re: [coreboot] porting Coreboot to a new motherboard....
My RAM code was OK(I remember all the members of this mailing list said:your RAM initialization is not OK, if RAM is not OK how romstage, ramstage and now filo are being executed!! Hey, you'd better take a closer look at the source code!!). The reason, hardwaremain() could not be executed, returns to CPU. Now ramstage part is copied into RAM and executed and i have added FILO 0.5.6 as a payload. main() function of FILO is executed and tried to read vmlinuz and initrd from harddisk and copy them to 0x10. Every thing is OK, IDE is initialized correctly and it seems that those files are read and copied well. (/boot and all its files and folders are recognized even lost+found !!) But finally the kernel seems not to become executed and after a few seconds delay hardwaremain() seems to get executed at last!!(strange) and in the middle of hardwaremain() CPU stops!!, hope this time you guys help me find what would be the cause of the problem(I have Fedora 8 and 2.6.23 as the kernel), the serial port shows the followings: coreboot-4.0-1959-g950f20a-dirty Wed Mar 14 18:57:56 IRST 2012 booting... clocks_per_usec: 1003 Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: : enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:1e.0: enabled 1 PCI: 00:1f.0: enabled 1 PNP: 002e.0: enabled 1 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.5: enabled 1 PNP: 002e.6: enabled 0 PNP: 002e.7: enabled 1 PNP: 002e.8: enabled 1 PNP: 002e.9: enabled 1 PNP: 002e.a: enabled 1 PNP: 002e.b: enabled 1 PCI: 00:1f.1: enabled 1 PCI: 00:1f.2: enabled 1 PCI: 00:1f.3: enabled 1 PCI: 00:1f.4: enabled 1 PCI: 00:1f.5: enabled 1 PCI: 00:1f.6: enabled 0 Compare with tree... Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: : enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:1e.0: enabled 1 PCI: 00:1f.0: enabled 1 PNP: 002e.0: enabled 1 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.5: enabled 1 PNP: 002e.6: enabled 0 PNP: 002e.7: enabled 1 PNP: 002e.8: enabled 1 PNP: 002e.9: enabled 1 PNP: 002e.a: enabled 1 PNP: 002e.b: enabled 1 PCI: 00:1f.1: enabled 1 PCI: 00:1f.2: enabled 1 PCI: 00:1f.3: enabled 1 PCI: 00:1f.4: enabled 1 PCI: 00:1f.5: enabled 1 PCI: 00:1f.6: enabled 0 scan_static_bus for Root Device APIC_CLUSTER: 0 enabled Finding PCI configuration type. PCI: Using configuration type 1 PCI_DOMAIN: enabled PCI_DOMAIN: scanning... PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [8086/1130] enabled PCI: 00:01.0 [8086/1131] enabled PCI: 00:1e.0 [8086/244e] bus ops PCI: 00:1e.0 [8086/244e] enabled PCI: 00:1f.0 [8086/2440] bus ops PCI: 00:1f.0 [8086/2440] enabled PCI: 00:1f.1 [8086/244b] ops PCI: 00:1f.1 [8086/244b] enabled PCI: 00:1f.2 [8086/2442] ops PCI: 00:1f.2 [8086/2442] enabled PCI: 00:1f.3 [8086/2443] bus ops PCI: 00:1f.3 [8086/2443] enabled PCI: 00:1f.4 [8086/2444] ops PCI: 00:1f.4 [8086/2444] enabled PCI: 00:1f.5 [8086/2445] ops PCI: 00:1f.5 [8086/2445] enabled do_pci_scan_bridge for PCI: 00:01.0 PCI: pci_scan_bus for bus 01 PCI: 01:00.0 [1002/5159] enabled PCI: pci_scan_bus returning with max=001 do_pci_scan_bridge returns max 1 do_pci_scan_bridge for PCI: 00:1e.0 PCI: pci_scan_bus for bus 02 PCI: pci_scan_bus returning with max=002 do_pci_scan_bridge returns max 2 scan_static_bus for PCI: 00:1f.0 PNP: 002e.0 enabled PNP: 002e.1 enabled PNP: 002e.2 enabled PNP: 002e.3 enabled PNP: 002e.5 enabled PNP: 002e.6 disabled PNP: 002e.7 enabled PNP: 002e.8 enabled PNP: 002e.9 enabled PNP: 002e.a enabled PNP: 002e.b enabled scan_static_bus for PCI: 00:1f.0 done scan_static_bus for PCI: 00:1f.3 scan_static_bus for PCI: 00:1f.3 done PCI: pci_scan_bus returning with max=002 scan_static_bus for Root Device done done Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 APIC_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources APIC_CLUSTER: 0 read_resources bus 0 link: 0 done PCI_DOMAIN: read_resources bus 0 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 done PCI: 00:1e.0 read_resources bus 2 link: 0 PCI: 00:1e.0 read_resources bus 2 link: 0 done PCI: 00:1f.0 read_resources bus 0 link: 0 PCI: 00:1f.0 read_resources bus 0 link: 0 done PCI_DOMAIN: read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 PCI_DOMAIN: child on link 0 PCI: 00:00.0 PCI_DOMAIN: resource base 0 size 0 align 0 gran 0 limit flags 40040100 index 1000 PCI_DOMAIN: resource base 0 size 0 align 0 gran 0 limit flags 40040200 index 1100 PCI: 00:00.0
[coreboot] porting Coreboot to a new motherboard....
I have initialized Intel 82815 SDRAM controller but for a special type
of RAM without reading SPD registers. I know that DRP register is :
0xCC. I added the code to Coreboot.
I tested much and concluded that RAM has a problem in a way as you
guys told me before. When i change the hardwaremain() , even adding
some code which are bypassed, the results of the post code numbers
become different!
I do not know what to do! c_start.S is OK and it is executed and the
program starts executing hardwaremain() but adding code to the
hardwaremain() any where seems to disorder printed post code values.
Is there any interrupt or timer set immediately after hardwaremain()?
I checked coreboot_ram in build/. The assembly code of hardwaremian() seems OK.
void sdram_enable(void)
{
asm(pushal);
asm(push %eax);
asm(push %ebx);
asm(push %ecx);
asm(push %edx);
asm(push %esi);
asm(push %edi);
asm(push %esp);
asm(push %ebp);
asm(pushfl);
asm(jmp firstlbl);
asm(mov %ax, %ax);
asm(nop);
/* Cache disable */
asm(firstlbl:);
asm(mov %cr0, %eax);
asm(and $0x9fff, %eax);
asm(or $0x4000, %eax);
asm(mov %eax, %cr0);
/* Configure the RAM command. */
asm(mov$0x0cf8, %dx);
asm(mov$0x8050, %eax);
asm(out%eax, %dx);
asm(movw $0x0CFC, %dx);
asm(in %dx, %eax);
asm(and $0x1fff, %eax);
asm(or $0x0500, %eax);
asm(movw $0x0CFC, %dx);
asm(out%eax, %dx);
//general initialization
//50-53**
asm(mov $0x0cf8, %dx);
asm(mov $0x8050, %eax);
asm(out %eax, %dx);
asm(mov $0x0cfc, %dx);
asm(in %dx, %eax);
//Res mask
asm(and $0xF823, %eax);
//Bios = cas 2clk
asm(or $0x2fcc0140, %eax);
asm(mov $0x0cfc, %dx);
asm(out %eax, %dx);
//70,72-73**
asm(mov $0x0cf8, %dx);
asm(mov $0x8070, %eax);
asm(out %eax, %dx);
asm(mov $0x0cfc, %dx);
asm(movb $0xc0, %al);
asm(out %al, %dx);
asm(mov $0x0cfe, %dx);
asm(inw %dx, %ax);
//Res mask
asm(and $0x7704, %ax);
//Bios
asm(or $0x0012, %ax);
asm(mov $0x0cfe, %dx);
asm(out %ax, %dx);
//92-93
asm(mov$0x0cf8, %dx);
asm(mov $0x8090, %eax);
asm(out %eax, %dx);
asm(mov $0x0cfe, %dx);
asm(movw $0xff5c, %ax);
asm(out %ax, %dx);
//#94-95*
asm(mov $0x0cf8, %dx);
asm(mov $0x8094, %eax);
asm(out %eax, %dx);
asm(mov $0x0cfe, %dx);
asm(inw %dx, %ax);
//#Res mask
asm(and $0xffc0, %ax);
//#Bios
asm(or $0x001c, %ax);
asm(mov $0x0cfe, %dx);
asm(out %ax, %dx);
//#98-9B*
asm(mov $0x0cf8, %dx);
asm(mov $0x8098, %eax);
asm(out %eax, %dx);
asm(movw $0x0cfc, %dx);
asm(in %dx, %eax);
//#Res mask
asm(and $0x7F887F88, %eax);
//#Bios
asm(or $0x80238023, %eax);
asm(movw $0x0cfc, %dx);
asm(out %eax, %dx);
//#9c-9f***
asm(mov $0x0cf8, %dx);
asm(mov $0x809c, %eax);
asm(out %eax, %dx);
asm( movw $0x0CFC, %dx);
asm(in %dx, %eax);
//#Res mask
asm(and $0x7FFF, %eax);
//#Bios
asm(or $0x8000, %eax);
asm(movw $0x0CFC, %dx);
asm(out %eax, %dx);
//#2c-2f***
asm(mov $0x0cf8, %dx);
asm(mov $0x802c, %eax);
asm(out %eax, %dx);
asm(mov $0x0cfc, %dx);
asm(mov $0x80271043, %eax);
asm(out %eax, %dx);
//58-5b**
asm(mov $0x0cf8, %dx);
asm(mov $0x8058, %eax);
asm(out %eax, %dx);
asm(mov $0x0cfc, %dx);
asm(in %dx, %eax);
asm(and $0xcf7f, %eax);
asm(or $0x3000, %eax);
asm(mov $0x0cfc, %dx);
asm(out %eax, %dx);
//5c-5f**
asm(mov $0x0cf8, %dx);
asm(mov $0x805c, %eax);
asm(out %eax, %dx);
asm(mov $0x0cfc, %dx);
asm(in %dx, %eax);
asm(and $0x, %eax);
asm(or $0x, %eax);
asm(mov $0x0cfc, %dx);
asm(out %eax, %dx);
Re: [coreboot] FILO can not be built!!
When i get the source code of Coreboot it has, some files as the source codes of libpayload and filo. Should i use these codes or i should download them from Coreboot pages? Regards On Mon, Feb 6, 2012 at 7:40 PM, QingPei Wang wangqing...@gmail.com wrote: hi ali, maybe at least you can provide the code version and the details about the configuration what you did with libpayload/filo. most of the time, there is a small chance that the code can not even being built. i think the libpayload configuration/install may have some problem which caused your error. I would like to say, would please use a more gentle tile about your problems? it may scaring me by coreboot ** stop, filo can not be built. :) Best wishes QingPei Wang Phone: 86+018930528086 On Mon, Feb 6, 2012 at 11:56 PM, Peter Stuge pe...@stuge.se wrote: op -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] I can not add FILO as a payload
I want to add FILO as a payload. There are some errors. I got the Coreboot source by : git clone http://review.coreboot.org/p/coreboot Then inside the project I had: /root/bios/coreboot/payloads/libpayload, /root/bios/coreboot/payloads/filo I executed the some steps according to the following file: /root/bios/coreboot/payloads/filo/README cd payloads/libpayload/ /root/bios/coreboot/payloads/libpayload make defconfig /root/bios/coreboot/payloads/libpayload make /root/bios/coreboot/payloads/libpayload make DESTDIR=../filo/build install /root/bios/coreboot/payloads/libpayload cd ../filo /root/bios/coreboot/payloads/filo make menuconfig /root/bios/coreboot/payloads/filo make Found Libpayload /root/bios/coreboot/payloads/filo/build/libpayload/lib/libpayload.a. CC build/i386/context.o CC build/i386/segment.o CC build/i386/timer.o CC build/i386/sys_info.o CC build/i386/linux_load.o CC build/main/filo.o CC build/main/strtox.o CC build/main/elfload.o CC build/main/ipchecksum.o CC build/main/grub/grub.o CC build/main/grub/builtins.o CC build/main/grub/cmdline.o CC build/main/grub/char_io.o CC build/main/grub/completions.o CC build/main/grub/md5.o CC build/fs/blockdev.o CC build/fs/vfs.o CC build/fs/eltorito.o CC build/fs/fsys_ext2fs.o CC build/fs/fsys_fat.o CC build/fs/fsys_reiserfs.o CC build/fs/fsys_iso9660.o CC build/fs/fsys_cbfs.o CC build/fs/cbfs.o /root/bios/coreboot/payloads/filo/fs/cbfs.c:113:20: error: conflicting types for 'cbfs_find_file' /root/bios/coreboot/payloads/filo/build/libpayload/include/cbfs_core.h:175:7: note: previous declaration of 'cbfs_find_file' was here make: *** [/root/bios/coreboot/payloads/filo/build/fs/cbfs.o] Error 1 I am copying the .config files of filo and lipayload: /root/bios/coreboot/payloads/filo cat .config # # Automatically generated make config: don't edit # FILO version: 0.6.0 # Tue Feb 7 17:12:41 2012 # CONFIG_TARGET_I386=y # # Interface Options # CONFIG_USE_GRUB=y CONFIG_PROMPT=filo CONFIG_MENULST_FILE=hda3:/boot/filo/menu.lst CONFIG_MENULST_TIMEOUT=0 CONFIG_USE_MD5_PASSWORDS=y # CONFIG_ISOLINUX_PARSER is not set # # Drivers # CONFIG_IDE_DISK=y CONFIG_IDE_DISK_POLL_DELAY=0 # CONFIG_SLOW_SATA is not set # CONFIG_PCMCIA_CF is not set CONFIG_USB_DISK=y # CONFIG_FLASH_DISK is not set CONFIG_SUPPORT_PCI=y # CONFIG_PCI_BRUTE_SCAN is not set # CONFIG_SUPPORT_SOUND is not set # # Filesystems # CONFIG_FSYS_EXT2FS=y CONFIG_FSYS_FAT=y # CONFIG_FSYS_JFS is not set # CONFIG_FSYS_MINIX is not set CONFIG_FSYS_REISERFS=y # CONFIG_FSYS_XFS is not set CONFIG_FSYS_ISO9660=y CONFIG_ELTORITO=y # CONFIG_FSYS_CRAMFS is not set # CONFIG_FSYS_SQUASHFS is not set CONFIG_FSYS_CBFS=y # # Loaders # CONFIG_LINUX_LOADER=y # CONFIG_WINCE_LOADER is not set # CONFIG_ARTEC_BOOT is not set # # Debugging Experimental # # CONFIG_EXPERIMENTAL is not set # CONFIG_DEBUG_ALL is not set # CONFIG_DEBUG_ELFBOOT is not set # CONFIG_DEBUG_SEGMENT is not set # CONFIG_DEBUG_SYS_INFO is not set # CONFIG_DEBUG_BLOCKDEV is not set # CONFIG_DEBUG_VFS is not set # CONFIG_DEBUG_FSYS_EXT2FS is not set # CONFIG_DEBUG_PCI is not set # CONFIG_DEBUG_LINUXLOAD is not set # CONFIG_DEBUG_IDE is not set # CONFIG_DEBUG_USB is not set # CONFIG_DEBUG_ELTORITO is not set CONFIG_DEVELOPER_TOOLS=y /root/bios/coreboot/payloads/libpayload cat ./.config # # Automatically generated make config: don't edit # libpayload version: 0.2.0 # Tue Feb 7 17:08:09 2012 # # # Generic Options # # CONFIG_EXPERIMENTAL is not set # CONFIG_OBSOLETE is not set # CONFIG_DEVELOPER is not set # # Architecture Options # CONFIG_TARGET_I386=y # CONFIG_TARGET_POWERPC is not set # CONFIG_MEMMAP_RAM_ONLY is not set # CONFIG_MULTIBOOT is not set # # Standard Libraries # CONFIG_LIBC=y CONFIG_CURSES=y # CONFIG_TINYCURSES is not set CONFIG_PDCURSES=y CONFIG_CBFS=y CONFIG_LZMA=y # # Console Options # CONFIG_SERIAL_CONSOLE=y CONFIG_SERIAL_IOBASE=0x3f8 # CONFIG_SERIAL_SET_SPEED is not set # CONFIG_SERIAL_ACS_FALLBACK is not set CONFIG_VIDEO_CONSOLE=y CONFIG_VGA_VIDEO_CONSOLE=y # CONFIG_GEODELX_VIDEO_CONSOLE is not set CONFIG_COREBOOT_VIDEO_CONSOLE=y CONFIG_PC_KEYBOARD=y CONFIG_PC_KEYBOARD_LAYOUT_US=y # CONFIG_PC_KEYBOARD_LAYOUT_DE is not set # # Drivers # CONFIG_PCI=y CONFIG_NVRAM=y # CONFIG_RTC_PORT_EXTENDED_VIA is not set CONFIG_SPEAKER=y CONFIG_USB=y CONFIG_USB_UHCI=y CONFIG_USB_OHCI=y CONFIG_USB_EHCI=y CONFIG_USB_XHCI=y CONFIG_USB_HID=y CONFIG_USB_HUB=y CONFIG_USB_MSC=y What caused the problem then? -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] I can not add FILO as a payload
Hello Peter. Thank you very much for the reply. I have just copied part of README file from the Coreboot project: /root cat ~/bios/coreboot/payloads/filo/README BUG REPORTING If you have problem with FILO, set DEBUG_ALL in Config and send its console output to the coreboot mailinglist at coreboot@coreboot.org. So i did: /root/bios/coreboot/payloads/filo make Found Libpayload /root/bios/coreboot/payloads/filo/build/libpayload/lib/libpayload.a. CC build/i386/context.o CC build/i386/segment.o CC build/i386/timer.o CC build/i386/sys_info.o CC build/i386/linux_load.o CC build/main/filo.o CC build/main/strtox.o CC build/main/elfload.o CC build/main/ipchecksum.o CC build/fs/blockdev.o CC build/fs/vfs.o CC build/fs/eltorito.o CC build/fs/fsys_ext2fs.o /root/bios/coreboot/payloads/filo/fs/fsys_ext2fs.c: In function 'dump_super': /root/bios/coreboot/payloads/filo/fs/fsys_ext2fs.c:404:33: error: 'struct ext2_super_block' has no member named 's_log_frag_size' /root/bios/coreboot/payloads/filo/fs/fsys_ext2fs.c:406:26: error: 'struct ext2_super_block' has no member named 's_frags_per_group' /root/bios/coreboot/payloads/filo/fs/fsys_ext2fs.c: At top level: /root/bios/coreboot/payloads/filo/fs/fsys_ext2fs.c:411:24: warning: 'struct ext2_group_desc' declared inside parameter list [enabled by default] /root/bios/coreboot/payloads/filo/fs/fsys_ext2fs.c:411:24: warning: its scope is only this definition or declaration, which is probably not what you want [enabled by default] /root/bios/coreboot/payloads/filo/fs/fsys_ext2fs.c: In function 'dump_group_desc': /root/bios/coreboot/payloads/filo/fs/fsys_ext2fs.c:414:35: error: dereferencing pointer to incomplete type /root/bios/coreboot/payloads/filo/fs/fsys_ext2fs.c:415:35: error: dereferencing pointer to incomplete type /root/bios/coreboot/payloads/filo/fs/fsys_ext2fs.c:416:34: error: dereferencing pointer to incomplete type /root/bios/coreboot/payloads/filo/fs/fsys_ext2fs.c:417:32: error: dereferencing pointer to incomplete type /root/bios/coreboot/payloads/filo/fs/fsys_ext2fs.c:418:34: error: dereferencing pointer to incomplete type /root/bios/coreboot/payloads/filo/fs/fsys_ext2fs.c:419:32: error: dereferencing pointer to incomplete type /root/bios/coreboot/payloads/filo/fs/fsys_ext2fs.c: In function 'ext4fs_block_map': /root/bios/coreboot/payloads/filo/fs/fsys_ext2fs.c:640:18: error: conflicting types for 'i' /root/bios/coreboot/payloads/filo/fs/fsys_ext2fs.c:637:7: note: previous declaration of 'i' was here /root/bios/coreboot/payloads/filo/fs/fsys_ext2fs.c: In function 'ext2fs_dir': /root/bios/coreboot/payloads/filo/fs/fsys_ext2fs.c:861:23: warning: passing argument 1 of 'dump_group_desc' from incompatible pointer type [enabled by default] /root/bios/coreboot/payloads/filo/fs/fsys_ext2fs.c:411:1: note: expected 'struct ext2_group_desc *' but argument is of type 'struct ext2_group_desc *' /root/bios/coreboot/payloads/filo/fs/fsys_ext2fs.c:877:3: error: 'gdp' undeclared (first use in this function) /root/bios/coreboot/payloads/filo/fs/fsys_ext2fs.c:877:3: note: each undeclared identifier is reported only once for each function it appears in make: *** [/root/bios/coreboot/payloads/filo/build/fs/fsys_ext2fs.o] Error 1 I lack time but I will try to get it fixed. I hope so. Regards. On Tue, Feb 7, 2012 at 5:45 PM, Peter Stuge pe...@stuge.se wrote: ali hagigat wrote: cd payloads/libpayload/ /root/bios/coreboot/payloads/libpayload make defconfig /root/bios/coreboot/payloads/libpayload make /root/bios/coreboot/payloads/libpayload make DESTDIR=../filo/build install /root/bios/coreboot/payloads/libpayload cd ../filo /root/bios/coreboot/payloads/filo make menuconfig So far so good. /root/bios/coreboot/payloads/filo make .. CC build/fs/cbfs.o /root/bios/coreboot/payloads/filo/fs/cbfs.c:113:20: error: conflicting types for 'cbfs_find_file' /root/bios/coreboot/payloads/filo/build/libpayload/include/cbfs_core.h:175:7: note: previous declaration of 'cbfs_find_file' was here make: *** [/root/bios/coreboot/payloads/filo/build/fs/cbfs.o] Error 1 .. What caused the problem then? Look more closely at the error message. It is actually a very clear error message. Then you look at the source code pointed to by the error message. This process is the *very first* problem resolution process that *every* programmer in this world encounters. It is amazing that you seem to not know it. :\ FILO is probably not quite up to date with the latest libpayload API, so you now have an opportunity to fix this and make FILO better for everyone. //Peter -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] How to port core boot
Thank you Rudolf for the reply. 1M to 3M is OK please look at the serial port output: coreboot-4.0-1959-g950f20a-dirty Tue Feb 7 18:39:18 IRST 2012 starting... Testing DRAM : 0010 - 0090 DRAM fill: 0x0010-0x0090 0090 DRAM filled DRAM verify: 0x0010-0x0090 0090 DRAM range verified. Done. Loading image. Searching for fallback/coreboot_ram Check fallback/romstage Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x10 (180224 bytes), entry @ 0x10 Stage: done loading. Jumping to image. On Tue, Feb 7, 2012 at 3:07 AM, Rudolf Marek r.ma...@assembler.cz wrote: Seems there is a case or two of possible infinite while() loops within the uart8250 serial console code. This is a wild guess, but the uart Yeah I dont like that too. Maybe worth to do a timeout? Or Loop count? It is always better to boot than to have perfect serial output ;) But in this case I would think memory is not 100% OK. Worth to check if 1M-3M is OK (this is where coreboot ramstage goes) Thanks Rudolf -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] How to port core boot
Peter, It is an easy answer to say that RAM is not initialized correctly! While I am pretty sure that RAM is OK, I have an assembly language which can verify that. Peter, you do not make the problem clear. The problem is that the registers of RAM controller are initialized with some correct values, but the Intel board had 82810 as its GMCH. My GMCH is 82815. I guess Coreboot at some point extracts some information from the config registers of GMCH and sets some variables and this is exactly the point which the problem occurs. I do not have enough information about the source code of Coreboot but logically where Coreboot is specifying the top of memory? Coreboot needs to know the size of memory, right? Where it is specified? Does my words make sense? Regards On Tue, Feb 7, 2012 at 6:58 PM, Peter Stuge pe...@stuge.se wrote: ali hagigat wrote: Stage: loading fallback/coreboot_ram @ 0x10 (180224 bytes), entry @ 0x10 Stage: done loading. Jumping to image. .. When it wants to do a jump inside cbfs_and_run_core(), the processor halts some how. RAM is not initialized correctly. //Peter -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] How to port core boot
Rudolf, When i started to study Coreboot and BIOS , people always made me confused by nonsense words. I asked some useful questions but interpreted as simple.(now I have developed a project which can drive RAM, serial port and hard disk) The managers of this project even do not accept their own mistakes. Now FILO can not be compiled and when i report it as the README of the filo is saying, the manager emails me and tells me that you are not a programmer!! I thought i would be encouraged for that by a thank you. When i ask a question nobody talks about the details of the logic behind that except one person, Kyösti Mälkki. Hey folks, what is going on here? If you are a master of Coreboot why we have unrelated simple answers? On 2/7/12, Rudolf Marek r.ma...@assembler.cz wrote: Hi, DRAM range verified. Well the check is quite simple maybe it works for simple cases and fails for real usage. I guess you need to port something like http://pyropus.ca/software/memtester/ to ROMCC to romstage and try again. All it sounds like raminit problem. Also I don't like couple of things btw. You never showed any of your code. You only ask sometimes too simple question without bothering too much with them. Please try hard before asking and try to learn new stuff. You have chosen quite difficult area, maybe you should try some simpler stuff first to get in touch better with C and common toolchains and after that get back here in here. Thanks Rudolf Done. Loading image. Searching for fallback/coreboot_ram Check fallback/romstage Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x10 (180224 bytes), entry @ 0x10 Stage: done loading. Jumping to image. On Tue, Feb 7, 2012 at 3:07 AM, Rudolf Marekr.ma...@assembler.cz wrote: Seems there is a case or two of possible infinite while() loops within the uart8250 serial console code. This is a wild guess, but the uart Yeah I dont like that too. Maybe worth to do a timeout? Or Loop count? It is always better to boot than to have perfect serial output ;) But in this case I would think memory is not 100% OK. Worth to check if 1M-3M is OK (this is where coreboot ramstage goes) Thanks Rudolf -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] coreboot is being stopped!! help
# CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_ACPI is not set # CONFIG_LLSHELL is not set # CONFIG_TRACE is not set # CONFIG_AP_CODE_IN_CAR is not set # CONFIG_RAMINIT_SYSINFO is not set # CONFIG_ENABLE_APIC_EXT_ID is not set # CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set # CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set # CONFIG_POWER_BUTTON_FORCE_DISABLE is not set # CONFIG_POWER_BUTTON_IS_OPTIONAL is not set # # Deprecated # # CONFIG_BOARD_HAS_HARD_RESET is not set # CONFIG_BOARD_HAS_FADT is not set # CONFIG_HAVE_BUS_CONFIG is not set # CONFIG_PCIE_TUNING is not set CONFIG_ID_SECTION_OFFSET=0x80 On Mon, Feb 6, 2012 at 1:40 AM, Kyösti Mälkki kyosti.mal...@gmail.com wrote: On Sun, 2012-02-05 at 18:25 +0330, ali hagigat wrote: My motherboard is: Pentium III, 82815, ICH2. I configured coreboot for Intel, d810e2cb motherboard. The coreboot stops printing the following lines on the serial port: coreboot-4.0-1959-g950f20a-dirty Sun Feb 5 17:52:27 IRST 2012 starting... SMBus controller enabled No DIMM found in slot 0 No DIMM found in slot 1 DRP calculated to 0x00 BUFF_SC calculated to 0x Loading image. Searching for fallback/coreboot_ram Check fallback/romstage Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x10 (180224 bytes), entry @ 0x10 Stage: done loading. Jumping to image. Where is the problem. I just replaced sdram_enable() with a routine which I am sure that it initializes RAM correctly. The rest is the pure Coreboot code. Hi Enable most verbose logging (8 ?) and post new logs. Also readers on the list have currently no clue how You obtained and modified your local copy of Coreboot. Your posted serial log appears exactly as from the coreboot sources. Double-check you have really changed the call to sdram_enable(), recompiled, flashed correctly etc. If you are running closed-source assembly code copy-pasted and mixed within coreboot, don't expect much assistance until you have convinced us that at the minimum ram_check() passes without errors after sdram_enable() :) The following patch contains a replacement ram_check() that I consider more reliable or thorough: http://review.coreboot.org/294 Thanks, KM -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] How to port core boot
I have developed the assembly code by myself and I am sure that it is OK as I have written a simple code in assembly which initializes RAM, serial port and hard disk. Every thing is OK in my code but I want to add this RAM code to Coreboot. I have already done it but Coreboot fails Regards On Mon, Feb 6, 2012 at 3:07 PM, Patrick Georgi patr...@georgi-clan.de wrote: Am 05.02.2012 13:50, schrieb ali hagigat: My motherboard is Pentium III, Intel 82815 and ICH2. I want to port the Coreboot to this motherboard and I already have an assembly routine which initializes the RAM modules. Where is that assembly routine from? Regards, Patrick -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] How to port core boot
I can verify that by the assembly code i have. writing to any memory location and reading that. Also I tested it by ram_check() in Coreboot. Both are correct. The last post codes are 0x39, 0x80 and Coreboot seems to stop! Regards On Mon, Feb 6, 2012 at 6:15 PM, Peter Stuge pe...@stuge.se wrote: ali hagigat wrote: I have developed the assembly code by myself and I am sure that it is OK as I have written a simple code in assembly which initializes RAM, serial port and hard disk. How did you verify that your code works? //Peter -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] FILO can not be built!!
I received filo by the Coreboot site, and libpayload was made
successfully but making filo stops with the following error:
/root/bios/coreboot/payloads/filo make
Found Libpayload
/root/bios/coreboot/payloads/filo/build/libpayload/lib/libpayload.a.
CC build/i386/context.o
CC build/i386/segment.o
CC build/i386/timer.o
CC build/i386/sys_info.o
CC build/i386/linux_load.o
/root/bios/coreboot/payloads/filo/i386/linux_load.c:752:5: error:
expected identifier or '(' before numeric constant
make: *** [/root/bios/coreboot/payloads/filo/build/i386/linux_load.o] Error 1
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] How to port core boot
My motherboard is Pentium III, Intel 82815 and ICH2. I want to port the Coreboot to this motherboard and I already have an assembly routine which initializes the RAM modules. Considering that what files i should alter exactly to get it done? I know that ASUS, MEW-AM is close to my board and it can be used as a start... -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] coreboot is being stopped!! help
My motherboard is: Pentium III, 82815, ICH2. I configured coreboot for Intel, d810e2cb motherboard. The coreboot stops printing the following lines on the serial port: coreboot-4.0-1959-g950f20a-dirty Sun Feb 5 17:52:27 IRST 2012 starting... SMBus controller enabled No DIMM found in slot 0 No DIMM found in slot 1 DRP calculated to 0x00 BUFF_SC calculated to 0x Loading image. Searching for fallback/coreboot_ram Check fallback/romstage Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x10 (180224 bytes), entry @ 0x10 Stage: done loading. Jumping to image. Where is the problem. I just replaced sdram_enable() with a routine which I am sure that it initializes RAM correctly. The rest is the pure Coreboot code. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] xgcc folder is not made!
Thank you for the reply. First please consider the specifications of my machine: root@sky-desktop:~/coreboot/util/crossgcc# uname -r 2.6.32-36-generic-pae root@sky-desktop:~/coreboot/util/crossgcc# uname -m i686 root@sky-desktop:~/coreboot/util/crossgcc# uname -a Linux sky-desktop 2.6.32-36-generic-pae #79-Ubuntu SMP Tue Nov 8 23:25:26 UTC 2011 i686 GNU/Linux root@sky-desktop:~# head -n1 /etc/issue Ubuntu 10.04.3 LTS \n \l and then the error: root@sky-desktop:~/coreboot/util/crossgcc# make build-without-gdb bash ./buildgcc Welcome to the coreboot cross toolchain builder v1.07 (November 1st, 2011) Will skip GDB ... ok Downloading tar balls ... * gmp-5.0.2.tar.bz2 (cached) * mpfr-3.1.0.tar.bz2 (cached) * mpc-0.9.tar.gz (cached) * libelf-0.8.13.tar.gz (cached) * gcc-core-4.6.2.tar.bz2 (cached) * binutils-2.21.1.tar.bz2 (cached) * acpica-unix-20110922.tar.gz (cached) Downloaded tar balls ... ok Unpacking and patching ... Unpacked and patched ... ok Skipping GMP as it is already built grep: /root/coreboot/util/crossgcc/xgcc/include/gmp.h: No such file or directory Skipping MPFR as it is already built Skipping MPC as it is already built Skipping libelf as it is already built Skipping binutils as it is already built Skipping GCC as it is already built Skipping Expat (Python scripting not enabled) Skipping Python (Python scripting not enabled) Skipping GDB (GDB support not enabled) Building IASL 20110922 ... failed make: *** [build-without-gdb] Error 1 and the second scenario: root@sky-desktop:~/coreboot/util/crossgcc# make bash ./buildgcc -G Welcome to the coreboot cross toolchain builder v1.07 (November 1st, 2011) Downloading tar balls ... * gmp-5.0.2.tar.bz2 (cached) * mpfr-3.1.0.tar.bz2 (cached) * mpc-0.9.tar.gz (cached) * libelf-0.8.13.tar.gz (cached) * gcc-core-4.6.2.tar.bz2 (cached) * binutils-2.21.1.tar.bz2 (cached) * gdb-7.3.1.tar.bz2 (cached) * acpica-unix-20110922.tar.gz (cached) Downloaded tar balls ... ok Unpacking and patching ... Unpacked and patched ... ok Skipping GMP as it is already built grep: /root/coreboot/util/crossgcc/xgcc/include/gmp.h: No such file or directory Skipping MPFR as it is already built Skipping MPC as it is already built Skipping libelf as it is already built Skipping binutils as it is already built Skipping GCC as it is already built Skipping Expat (Python scripting not enabled) Skipping Python (Python scripting not enabled) Building GDB 7.3.1 ... failed make: *** [build] Error 1 Regards On Sat, Dec 31, 2011 at 10:18 PM, Stefan Reinauer stefan.reina...@coreboot.org wrote: On 12/31/11 5:00 AM, ali hagigat wrote: I downloaded the coreboot version 4 for a Ubuntu system. When i want to execute util/crossgcc/make It stops complaining that there is an error building GDB! If i want to make without GDB like by buildgcc, it stops , the error is that it can not find one h file in xgcc and iasl can not be made! xgcc folder is not filled! What is the problem? Regards (PS. Besides when i want to compile the source code of coreboot by its makefile, it stops and complains that one symbol has two contradict types. An error log would be helpful. Should i run `buildgcc` before making the Coreboot source code? ) yes. Please update your coreboot checkout to the latest version. GDB is no longer built per default due to problems with some Linux distributions. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] xgcc folder is not made!
I downloaded the coreboot version 4 for a Ubuntu system. When i want to execute util/crossgcc/make It stops complaining that there is an error building GDB! If i want to make without GDB like by buildgcc, it stops , the error is that it can not find one h file in xgcc and iasl can not be made! xgcc folder is not filled! What is the problem? Regards (PS. Besides when i want to compile the source code of coreboot by its makefile, it stops and complains that one symbol has two contradict types. Should i run `buildgcc` before making the Coreboot source code? ) -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Intel GMCH 82815
I am working with Pentium III, Intel GMCH, 82815 and Intel ICH2, 82801. I managed to initialize DRAM controller to recognize the first 640 K of the memory correctly in the real mode. When i switch to the protected mode, CPU writes to the first 64K only. Every other read/write from the higher addresses leads to CPU restart. Can anybody say what is going on? -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Intel GMCH 82815
); . = compstart + 0x8200; compstart = .; *(.realmode); . = compstart + 0x7df0; compstart = .; *(.reset); . = compstart + 0x10; } } Makefile all: as -march=pentiumiii -mtune=pentiumiii -o ram.o ram.S ld ram.o -o ram -T ram.ld objcopy -O binary ram ram.img On Wed, Nov 30, 2011 at 12:57 PM, Peter Stuge pe...@stuge.se wrote: ali hagigat wrote: I am working with Pentium III, Intel GMCH, 82815 and Intel ICH2, 82801. I managed to initialize DRAM controller to recognize the first 640 K of the memory correctly in the real mode. When i switch to the protected mode, CPU writes to the first 64K only. Every other read/write from the higher addresses leads to CPU restart. Can anybody say what is going on? Not unless you show your code. One explanation would be that you haven't done a proper switch into protected mode (setting up a descriptor table and initializing selectors) which would make the CPU triple fault and reset on accesses outside whatever the descriptors happen to be. If this is the case, I think that Intel's IA-32 architecture manuals have good info on what you need to do, and of course you can study both coreboot sources as well as some good old DOS extenders such as Tran's PMODE32, DOS4GW from Watcom or my personal favorite DOS32. //Peter -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] hi every one...
I have a motherboard, Pentium III, 815/ICH2. How the CPU can be put into the deep sleep state? Is it possible to do it while not having the board schematic? -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] System management mode for Intel processors
I wonder if anybody can explain the system management mode RAM addresses for Intel Pentium III/815/ICH2. I know that SMBASE is 3 after reset. But 815 can define TSEG (and HSEG ) and also AB segments some where else. Like TSEG can be 512k or 1M from the top of memory. Considering that SMBASE can not be any thing but 3 as the Intel manual is saying , from what addresses CPU instructions are fetched after SMI# interrupt at last? -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] a question about hardware and PCI
I have a general question about a PCI-to-PCI bridge. If the device has a positive decoder and receives an address in the range of the addresses it should respond. Then it claims the address and forwards it to the secondary interface. Now suppose no target on the secondary interface claims the transaction and master-abort happens for the second interface. What will happen to the primary interface then? Why PCI specifications do not explain the connection between the state machines of the primary and secondary interfaces? -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] where can i ask detailed technical questions about hardware?
I wonder if any one knows about some forums or sites for asking questions about the data sheets contents of mother board ICs. I am investing about Intel ICs. Though Intel has some forums but they are inactive and questions remain unanswered. Is there any active site to discuss Intel data sheets? Regards -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] where can i ask detailed technical questions about hardware?
Hello Peter, Thank you very much to respond. I have the necessary data sheets now but some lines of the documents are ambiguous and obscure. I do not want to take up your time much but I wonder if I can ask you these questions. I can send you the data sheets and specify the lines we are going to talk about. Regards PS. If anybody else can help me, please let me know and please specify if I contact you personally or by Coreboot mailing list. On Wed, Apr 6, 2011 at 3:49 PM, Peter Stuge pe...@stuge.se wrote: ali hagigat wrote: Is there any active site to discuss Intel data sheets? Not really. :\ The proper forum for those discussions would be with your assigned Intel FAE. Of course, then you need to have access to one, which basically requires a large quantity project to make it interesting for Intel to assign some resources. You'll also need to sign a couple of NDAs. Pretty few people in the world have access to the information that is required to write firmware for PCs with Intel components. //Peter -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] a question about ASUS, MEW-AM
Where the graphics card is initialized in the source code? Is it using Internal graphics card or external? I found some vga routines in pc80 and console folders. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Tiny bootblock vs Bigbootblock
I think i made a mistake. In big boot block, bootblock code is written once for coreboot.pre and the same is for tiny boot block. My source of confusion was the inclusion of the bootblock code in crt0. Regards On Wed, Mar 2, 2011 at 3:47 AM, Stefan Reinauer stefan.reina...@coreboot.org wrote: * ali hagigat hagigat...@gmail.com [110301 09:58]: What is the difference between tiny and big boot block? In big boot block mode, romstage (and thus ram init) is part of the boot block. In tiny boot block mode, romstage is an extra file in CBFS. My second question is that the code of bootblock is copied to romstage too. I mean we have a duplicate code in two different components. Is that right? That might be a mistake. Where did you see that? Stefan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Tiny bootblock vs Bigbootblock
I created a new source code tree for only one motherboard, ASUS, MEW_AM. There is no build/bootblock folder and CONFIG_TINY_BOOTBLOCK and CONFIG_BOOTBLOCK_SIMPLE are not set. What is the difference between tiny and big boot block? My second question is that the code of bootblock is copied to romstage too. I mean we have a duplicate code in two different components. Is that right? -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Seeing the output messages
How a program is traced in Coreboot? by serial port? or initialization of internal graphics cards? What about those boards with external graphics cards? When it does printk, to what device the message is actually sent? -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Seeing the output messages
Joe, I wonder if you can answer my questions if you really know about them. I do not have any mother board with Coreboot support now. I am reviewing the code statically. Regards On Wed, Feb 16, 2011 at 1:35 PM, Joseph Smith j...@settoplinux.org wrote: On Wed, 16 Feb 2011 12:37:15 +0330, ali hagigat hagigat...@gmail.com wrote: How a program is traced in Coreboot? by serial port? or initialization of internal graphics cards? What about those boards with external graphics cards? When it does printk, to what device the message is actually sent? Why don't you try it and find out! -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] receiving serial port bytes
I want to capture every single byte of the serial port, ttyS0(or com1) of my Linux (Fedora 12) box . I wonder if anybody knows about a good tool for it. Regards -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] coreboot.rom
How the file coreboot.rom is written on BIOS chip logically? Suppose
our BIOS chip is 1 mega bytes. We should read first byte from the
beginning of the file and write it to the address zero of BIOS chip
and continue this way?
I checked the content of build/coreboot.rom and the last byte was
0x0a!! Which is written probably on the top of our EEPROM. Right?
but src/arch/i386/init/ldscript.ld specifies the last byte as 0x00!!
SECTIONS {
_ROMTOP = 0xfff0;
. = _ROMTOP;
.resetvector . : {
*(.reset)
. = 15 ;
BYTE(0x00);
}
}
Please help me with this puzzle. Thank you.
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[coreboot] gcc in coreboot
If I want to run gcc, ld , as from elf32-i386 toolchain, should i change the file .xcompile in the root directory of Coreboot? and change the following line: CC:=gcc -Wa,--divide -fno-stack-protector -Wl,--build-id=none to: CC:=util/crossgcc/xgcc/i386-elf/bin/gcc -Wa,--divide -fno-stack-protector -Wl,--build-id=none Will that be enough? (no need to change the system header files paths? or other thing?) Sorry to take up the time of people of the mailing list and thank you all in advance. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] a question about reset16.lds
Thank you for the reply.
Lets consider the lines of that linker script again! First the
location counter is set to 0xfff0 and the output .reset section
starts from VMA=0xfff0. I think we both agree on that so far.
But after .reset section, .=15 forces the location counter to be 15!!
It means the location counter suddenly jumps from the top of memory to
some where in the bottom! and then linker asks for storing 0x00 in the
address of 15! or at the beginning of memory.
.=15 does not set the size of .reset as you wrote.
My suggestion was .=.+1 instead of .=15, or set VMA to one byte after
the final .reset and then ask for writing 0x00 at the address of
0x.
We are using . in the linker script file, it means VMA (virtual memory
address).
On Tue, Feb 1, 2011 at 8:15 PM, Patrick Georgi patr...@georgi-clan.de wrote:
Am 01.02.2011 12:46, schrieb ali hagigat:
SECTIONS {
/* Trigger an error if I have an unuseable start address */
_bogus = ASSERT(_start= 0x, _start too low. Please
decrease CONFIG_ROM_IMAGE_SIZE);
_ROMTOP = 0xfff0;
. = _ROMTOP;
.reset . : {
*(.reset)
. = 15 ;
BYTE(0x00);
}
}
--
What does (.=15;) mean? It seems a mistake! and can be: . = .+1;
. = 15; means set the location pointer to 15. With the byte that's written
right after that, this means that .reset is exactly 16 bytes.
If it's less, . = 15 pads the section to be larger, if it would have to be
larger, . = 15 makes the linker fail (because the location pointer must
not go backwards).
I guess that also answers why . = .+1 is no adequate substitute.
Patrick
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[coreboot] a question about reset16.lds
SECTIONS {
/* Trigger an error if I have an unuseable start address */
_bogus = ASSERT(_start = 0x, _start too low. Please
decrease CONFIG_ROM_IMAGE_SIZE);
_ROMTOP = 0xfff0;
. = _ROMTOP;
.reset . : {
*(.reset)
. = 15 ;
BYTE(0x00);
}
}
--
What does (.=15;) mean? It seems a mistake! and can be: . = .+1;
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[coreboot] Some questions about Intel 815EG GMCH
I wonder if you can introduce some active forums or mailing lists to discuss Intel chips in details technically except the Intel forums because they are virtually inactive and no question is answered i have tried it out before. I have questions about Intel 82815EG north bridge(it is connected to Pentium III). It has a display cache interface and up to 4 MB memory can be plugged into its AGP port. I wonder if anybody knows how can i map this 4 mega bytes memory above my main RAM physical memory because I want to see and check the content of that local memory. Also the manual of the chip talks about 32/64MB memory(and also another 512K) configurable by some config registers. The display cache memory can be configured to reside inside this 64 MB? What is this 64M, is it the display cache virtually or it is a different memory? Also the manual says: GMCH does not support VGA on local memory What does it mean? -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] one super i/o
I am looking for the data sheet and programming reference manual of a super I/O chip by ITE, IT8703F. I will be much appreciated if anybody can email it for me. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] .cb files
How .cb files are created? and what they are used for? -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] .cb files
Peter, Thank you. So devicetree.cb files are written by hand and the compilation process does not use them? They are just some information for the developers? About: file:///root/build/coreboot/coreboot-v4/src/mainboard/kontron/986lcd-m/devicetree.cb: #device pci 1e.2 off end # AC'97 Audio It means that AC'97 Audio is on Bus#=1 and Function#=2? But all the devices of the south bridge, ICH7 are on Bus number 0, as far as I know. Why you have not written, Bus number, Function number, Device number, Register number clearly. device pci 1d.0 on end, What does it mean, 1d.0? Regards On Mon, Jan 3, 2011 at 6:37 PM, Peter Stuge pe...@stuge.se wrote: ali hagigat wrote: How .cb files are created? As was pointed out already, by hand. and what they are used for? Describing fixed parts of a system. What buses there are and what devices are on them. Please suggest how we can improve the syntax of .cb files. I want them to be self-documenting enough so that you can understand the above from just looking at the files. Can you help? //Peter -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] hello
We have the following definition for CC: CC:=gcc -Wa,--divide -fno-stack-protector -Wl,--build-id=none I wonder if any one can explain the options, --divide and --build-id. Thank you. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] hello
Thank you for the reply but: Documentation does not explain --divide!! On Sat, Nov 27, 2010 at 12:58 PM, Tobias Diedrich ranma+coreb...@tdiedrich.de wrote: ali hagigat wrote: We have the following definition for CC: CC:=gcc -Wa,--divide -fno-stack-protector -Wl,--build-id=none I wonder if any one can explain the options, --divide and --build-id. Thank you. -Wl,foo is a linker option, please look at the ld manpage. Similarily, -Wa,foo is an assembler option. From the ld manpage: --build-id=style Request creation of .note.gnu.build-id ELF note section. The [...] -- Tobias PGP: http://8ef7ddba.uguu.de -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] protected_start and __protected_start!
Would you please tell me how Coreboot jumps to the label, protected_start in src/cpu/x86/32bit? There is a jump instruction (jmpprotected_start) in reset16.inc but it seems it will never be executed. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] a question about the file, coreboot_ram
We know that coreboot_ram is written in ROM. So how its linker file(src/arch/i386/coreboot_ram.ld), shows some text and data sections above CONFIG_RAMBASE(like above 1MB) in RAM? -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] printall target
My question is about the main makefile of Coreboot and the rule 'printall'. I wonder if anybody can write a 'sed' or 'awk' command or any other shell command to print the result of 'objs' , 'initobjs' , 'drivers' .on separate lines(each pathname is printed on a separate line and then there is a new line at the end of each line, second pathname of a file is written on the second line and continues...) Now spaces are separating the strings, make them difficult to read. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] How the file, c_start.d is made?
Thank you Peter to advice me to study the Coreboot source code and learn new things (my ultimate purpose is the same dear) but simple question is this: Where is the first lines of Coreboot to study? Where do I have to look at in the beginning to understand the algorithm of Coreboot? What will be the code/data flow? Answering to these questions make me return back to the build process to know the logical relationship of the source code fragments and another thing is how and where the source code functions and fragments have been written(I mean what physical addresses)? You say something but it can not be done in practice dear... How you are a Coreboot expert while you do not know even what will make c_start.d? When you start studying the files which will be built for Coreboot you will face with this dragon very soon. Sometimes a person wants to change a specific part of a source code and he has a professional manager, while his manager masters the code perfectly but he needs new changes and hires an engineer and take him over some responsibilities. This is one story, but another scenario is when a person is completely stranger to the code and must understand the whole project by himself. He must deal with any thing related to the project from build to the internal code, every thing. Best Regards On Tue, Oct 26, 2010 at 1:51 PM, Peter Stuge pe...@stuge.se wrote: ali hagigat wrote: what rule is making the file, c_start.d itself? It's very strange that you are so obsessed with the build system so many months after starting to look at coreboot. I first looked at coreboot nearly 10 years ago, and while I am not super active in the codebase there are still *so* many other *actual* things to work on and learn about *in the code*. You've mentioned that you want to study coreboot before you can work with it, but I would recommend that you stop studying the build system for now and look more at what coreboot *code* is actually doing. This is especially true if you are not already very skilled with the GNU toolchain and make, because building coreboot can sometimes require special tricks. To also answer your question, I suggest that you study the output from make V=1 and see which command creates the c_start.d file. Then you could probably locate it within the Makefiles. //Peter -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] How the file, c_start.d is made?
The only rule for building c_start.o from c_start.S is the following in build/arch/i386/lib/c_start.d: build/arch/i386/lib/c_start.o: src/arch/i386/lib/c_start.S \ /root/build/coreboot/coreboot-v4/build/config.h \ src/include/cpu/x86/post_code.h The question is that what rule is making the file, c_start.d itself? -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] an AMD based platform
I want to ask the experts about an AMD based motherboard to research on Coreboot, what you recommend will be valuable or please tell me what motherboard in the list of supported motherboards of Wiki-Coreboot is more modern and close to the following attributes: I am looking for a motherboard with CPU and chip set similar to Intel. For CPU, I want it to have IA-32 and IA-32e architecture, I mean 32 bit machine with 64 bit extension to support 32 and also 64 bits applications, with Vtx (virtual machine capability), muti-core, and SIMD instructions with front side bus. About Chipset, I want it to have regular logics of USB, SATA, PCIExpress, SDRAM controller, FWH/SPI protocol for BIOS chip, PCI bridge, IOAPIC, Integrated Graphics Controller, real time clock, LPC interface,a relatively modern board and superio with open documentation. Thank you to read my message. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] BBC EFI story
Dear Ron Minnich, I started with Wiki pages of Coreboot and i found Kontron, 986LCD-mITX as a supported mother board. I though its documentation is open because Coreboot is open source and ordered 4 motherboards, over 11000$. After investigating more about Intel manuals I found out that many registers of North bridge, 82945 have not been expressed!! and Intel gives this information to big BIOS companies ONLY. At least you could update Wiki pages to state this fact clearly to stop people waste money. How people can contribute the code while they do not have documentation and necessary information? On Sat, Oct 2, 2010 at 12:22 AM, ron minnich rminn...@gmail.com wrote: This story is full of errors. I thought I'd point out a few. New PCs could start in just seconds, thanks to an update to one of the oldest parts of desktop computers. I've got news for the UEFI forum: OLD computers, starting 10 years ago, have been starting in seconds, thanks to the coreboot project. We first showed a 12 second boot at the Atlanta Linux Symposium in Oct. 2000. It is hardly news that one can boot a computer quickly. The project then was called LinuxBIOS; the project today is called Coreboot. Coreboot works on embedded systems, desktops, laptops, and supercomputers. It has run in the iRobot packbot for 10 years, searching mines and saving lives. Some of the biggest supercomputers in the world have run coreboot. Work on coreboot was, in fact, funded first by the US Gov't (Dept. of Energy) and more recently by the German Government (see, for example, http://www.coreboot.org/pipermail/coreboot-announce/2010-May/07.html) So why, might you ask, did vendors not pick this technology up 10 years ago? Technology that worked on x86, 64-bit x86, Power PC, and DEC Alpha? The reason is simple: it's open source. And, while vendors finally did decide that an open source operating system might be acceptable, they have had a lot of trouble accepting an open source BIOS. They feel that too much information is divulged if the BIOS is open source. They make a lot of excuses, but in the end, they finally admit that the issue is that they don't want the hardware to be that open. The upgrade will spell the end for the 25-year-old PC start-up software known as Bios that initialises a machine so its operating system can get going. The BIOS could have been ended ten years ago, but for a simple fact: many customers don't much like EFI. It's clumsy, slow, and closed. And it's hard to work around, as it is designed to hide information. The code was not intended to live nearly this long, and adapting it to modern PCs is one reason they take as long as they do to warm up. There's a lot more to it than that. The closed nature of the BIOS software made it very hard to replace. And, again, the vendors have shown time and again that they prefer a closed, proprietary solution to an open source solution. That's the real problem. Alternatives to UEFI, such as Open Firmware and Coreboot, do exist and are typically used on computers that do not run chips based on Intel's x86 architecture. This statement is completely wrong. Coreboot has run on x86 systems from the start and, in fact, only runs on x86 systems now. Open Firmware also runs on x86 systems and is in fact the BIOS for the One Laptop Per Child project -- an x86 system. At the moment it can be 25-30 seconds of boot time before you see the first bit of OS sign-on, he said. With UEFI we're getting it under a handful of seconds. It's nice to see UEFI catching up only 10 years later; the first versions took 10 minutes to boot. Automobile computers, using ARM processors, and an open source BIOS called U-boot, boot Linux in 8/10 of a second. So, while UEFI is where coreboot was ten years ago, we've all moved on; seconds is kind of slow nowadays. He said that 2011 would be the year that sales of UEFI machines start to dominate. Dominate what? Certainly not cell phones. Certainly not the ipad. In fact, UEFI is going to dominate a segment that matters less and less nowadays -- PC-compatible desktops and laptops. I think you can do better than this article; the BBC is one of the finest news organizations in the world. It seems you took a puff-piece from the UEFI group and removed the quotes. I'm very disappointed in the BBC. Thanks Ron Minnich Founder, LinuxBIOS, which is now coreboot. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Intel datasheets require NDAs
I am afraid those unmentioned registers have a significant effect in understanding the function and logic of the internal parts of the IC and the standards used. First, one must study to know what is going on, how can i work without having enough information?! I am not going to keep on complaining but the incomplete documentation may be added to the first page of Wiki, in www.coreboot.org/Welcome_to_coreboot. On Sat, Oct 2, 2010 at 10:55 PM, Anders Jenbo and...@jenbo.dk wrote: I also would like to know what your goal is, this would probably make it much easyer to tell you what you need to know, instead of you complaning each time you find you need some thing you didn't know you needed when you started to do... somehting. -Anders -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] mkelfimage and coreboot.rom!!
can i build an elf file from the final coreboot image means coreboot.rom by using mkelfimage tool? Or it is used for Linux kernel only? Thank you to read my message -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] --divide!! and .xcompile
Is there any document or link to explain what changes has been done in GCC, binutils, gdb and it seems all GNU tool chain components have changed! If I do not change GNU tool chain, the final coreboot.rom will be an incorrect image and it can not be run? -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] --divide!! and .xcompile
Why the following link does not mention to execute util/crossgcc/buildgcc before doing make? http://www.coreboot.org/Build_HOWTO Anyway I ran util/crossgcc/buildgcc and here is the result: Welcome to the coresystems cross toolchain builder v1.01 (May 18th, 2010) Downloading tar balls ... * gmp-5.0.1.tar.bz2 (cached) * mpfr-2.4.2.tar.bz2 (cached) * mpc-0.8.2.tar.gz (cached) * libelf-0.8.13.tar.gz (cached) * gcc-core-4.4.4.tar.bz2 (cached) * binutils-2.20.1.tar.bz2 (downloading) * gdb-7.1.tar.bz2 (downloading) Downloaded tar balls ... ok Unpacking and patching ... * gmp-5.0.1.tar.bz2 bzip2: Compressed file ends unexpectedly; perhaps it is corrupted? *Possible* reason follows. bzip2: Inappropriate ioctl for device Input file = (stdin), output file = (stdout) It is possible that the compressed file(s) have become corrupted. You can use the -tvv option to test integrity of such files. You can use the `bzip2recover' program to attempt to recover data from undamaged sections of corrupted files. tar: Child returned status 2 tar: Exiting with failure status due to previous errors * mpfr-2.4.2.tar.bz2 o mpfr-2.4.2_allpatches_20100308.patch * mpc-0.8.2.tar.gz * libelf-0.8.13.tar.gz * gcc-core-4.4.4.tar.bz2 bzip2: Compressed file ends unexpectedly; perhaps it is corrupted? *Possible* reason follows. bzip2: Inappropriate ioctl for device Input file = (stdin), output file = (stdout) It is possible that the compressed file(s) have become corrupted. You can use the -tvv option to test integrity of such files. You can use the `bzip2recover' program to attempt to recover data from undamaged sections of corrupted files. tar: Unexpected EOF in archive tar: Unexpected EOF in archive tar: Error is not recoverable: exiting now * binutils-2.20.1.tar.bz2 * gdb-7.1.tar.bz2 Unpacked and patched ... ok Building GMP 5.0.1 ... failed -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] --divide!! and .xcompile
I found the following variable in .xcompile: CC:=gcc -Wa,--divide -fno-stack-protector -Wl,--build-id=none It seems that there is no definition of --divide option for GNU assembler. What is it supposed to do? -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] --divide!! and .xcompile
Thank you all for the replies. Peter, the link you wrote is broken! http://sourceware.org/binutils/docs/as/i386_002dOptions.html#i386_002dOptions Should i execute, util/crossgcc/buildgcc to change and patch the original Linux GCC? That will be all? or I may have to change some other things. Please excuse me if my question is a repeat. On Sat, Sep 4, 2010 at 5:50 PM, Peter Stuge pe...@stuge.se wrote: ali hagigat wrote: It seems that there is no definition of --divide option for GNU assembler. http://sourceware.org/binutils/docs/as/i386_002dOptions.html#i386_002dOptions -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] --divide!! and .xcompile
Many thanks Corey. The link is OK, i was mistaken. My machine is Linux, Fedora 12, should i execute util/crossgcc/buildgcc to change the GCC of the system? So how util/crossgcc/buildgcc works? because there is already a GCC rpm installed, then it will install another one and the previous version is uninstalled? If I use Fedora 12 GCC, when it executes 'gcc -Wa,--divide and the option(--divide) is unknown, how come it can compile the files by it without errors? On Sun, Sep 5, 2010 at 10:00 AM, Corey Osgood corey.osg...@gmail.com wrote: On Sun, Sep 5, 2010 at 1:15 AM, ali hagigat hagigat...@gmail.com wrote: Thank you all for the replies. Peter, the link you wrote is broken! http://sourceware.org/binutils/docs/as/i386_002dOptions.html#i386_002dOptions Works fine for me: --divide On SVR4-derived platforms, the character `/' is treated as a comment character, which means that it cannot be used in expressions. The `--divide' option turns `/' into a normal character. This does not disable `/' at the beginning of a line starting a comment, or affect using `#' for starting a comment. Should i execute, util/crossgcc/buildgcc to change and patch the original Linux GCC? No, crossgcc should fetch it's own known good version of gcc and patch it. Trying to patch some other version of gcc will probably fail. -Corey That will be all? or I may have to change some other things. Please excuse me if my question is a repeat. On Sat, Sep 4, 2010 at 5:50 PM, Peter Stuge pe...@stuge.se wrote: ali hagigat wrote: It seems that there is no definition of --divide option for GNU assembler. http://sourceware.org/binutils/docs/as/i386_002dOptions.html#i386_002dOptions -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] util directory
Inside util/abuild we have two files: abuild and abuild.1 What language do they have written with? What is their functions in short? Are they necessary for building a coreboot image? -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Coreboot-v4 and protected_stage0?
ljmp $ROM_CODE_SEG, $protected_stage0 Where is the definition of the symbol, protected_stage0? Thank you to read my message. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] dongle.py!!
update: dongle.py -c /dev/term/1 $(obj)/coreboot.rom EOF What was dongle.py in top makefile? -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] dongle.py!!
My main questions are not answered! Starting from top makefile, what is first rule that is executed? How this makefile causes other makefiles inside the subdirectories are called? Please mention the line which does this. Thank you. On Tue, Aug 10, 2010 at 7:41 PM, Patrick Georgi patr...@georgi-clan.dewrote: Am 10.08.2010 17:06, schrieb ali hagigat: update: dongle.py -c /dev/term/1 $(obj)/coreboot.rom EOF What was dongle.py in top makefile? dongle.py is a utility to control the Artec FlexyICE dongle (hence the name of the tool). The dongle serves as a PLCC emulator, with cuts down on roundtrip times for developers that use it. See http://www.coreboot.org/Artecgroup_programmable_LPC_dongle Given that you manage to ask only about the less important parts of the tree, I guess I can be happy to assume that you have no issues with the basic operation of the tree. Patrick -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] How Coreboot.rom is made?
I have listed all the lines that mentions the symbol, coreboot.rom in the top Makefile: coreboot: $(obj)/coreboot.rom update: dongle.py -c /dev/term/1 $(obj)/coreboot.rom EOF Where is dongle.py? How coreboot.rom is made? Where is the rule for it? -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Top Makefile
I want to know how coreboot.rom, means the final product is built. What rule makes it and where is it? How its format is CBFS while this format seems unknown for GNC tool chain like gcc? On Wed, Aug 4, 2010 at 8:10 PM, Joseph Smith j...@settoplinux.org wrote: On Wed, 4 Aug 2010 19:07:38 +0430, ali hagigat hagigat...@gmail.com wrote: When we execute the command: make What rule will be executed? We know that compiling and linking c/assembly files by GNU gcc tool produce object files with specific formats like elf, COFF,How the final Coreboot image is not in those formats, means it is not in elf, COFF formats? It is an executable file. Can you please explain why you are so interested in coreboot's build(make) process? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Top Makefile
When we execute the command: make What rule will be executed? We know that compiling and linking c/assembly files by GNU gcc tool produce object files with specific formats like elf, COFF,How the final Coreboot image is not in those formats, means it is not in elf, COFF formats? It is an executable file. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] error in FILO configuration
I have FILO source code in: /root/build/coreboot/filo and COREBOOT source code is in: /root/build/coreboot/coreboot-v4 When i execute the instruction below, it is followed by an error: /root/build/coreboot/filo make menuconfig Libpayload config for FILO. can't find file /root/build/coreboot/filo/../libpayload/Config.in make: *** [menuconfig] Error 1 How can i correct it? -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Coreboot Makefile
I wonder if any body can say what is the major effect of INNER_SCANBUILD symbol in making the project? -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Coreboot Makefile
Thank you very much for the reply. What is the name of the RPM of scanbuild or clang for Fedora, Linux? clang is the name of the package? On 7/26/10, Patrick Georgi patr...@georgi-clan.de wrote: Am 26.07.2010 11:58, schrieb ali hagigat: I wonder if any body can say what is the major effect of INNER_SCANBUILD symbol in making the project? It's used when building coreboot under scanbuild (part of clang), which does static analysis of the code. Unless you want to tweak that particular piece of the build system, you don't have to care about it. Patrick -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] CentraLUG meeting, 2 August
You can talk about the Makefile too. How Coreboot is built in a typical scenario and by what tools. On Thu, Jul 22, 2010 at 6:30 PM, Joseph Smith j...@settoplinux.org wrote: Brief summary about the presentation: 1. I plan on speaking a litle about myself, and how I got involved in coreboot (elaborate on above). 2. Give a brief history on coreboot and how it started. 3. Go over some of the features of coreboot. 4. Go over some of the great tools that have sprouted off of the coreboot tree. 5. Talk about how the code process flows and how you(audiance) can start to develop coreboot. 6. Open for Question and Answer time. -- Do you guys think there is anything else I should touch on? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] compiling coreboot
The reason some of you do not like to answer is not lack of time. It is because you do not want other people know about the details of the project, to disappoint people or make their progress slow. I do not ask trivial questions and far from the real knowledge necessary for the project. I ask the questions which hurts you guys because it targets your core knowledge you do not want to talk about. The same behaviour is seen in Linux Kernel mailing list... Knowledge expands by discussing the darkest areas of the matter not to keep it secrete in my opinion. Hey, Rudolf, you wrote 6 lines attacking me instead of write one line to answer my questions. What is the reason for it you think? Rudolf, answering my questions take you not more than a few minutes of your time and it is not a waste of time. Answering technical questions are not a waste of time, never, as it is a kind of practice and helps people keep their knowledge updated or refreshed. I did not ask you about economics, politics and the subjects unrelated to computer science, how can i waste your time? It is something you can benefit from if you think about it unless you have other reasons (that I am aware of!!) I asked some questions to understand the overall framework of the work without going into the details. I knew about the wiki site of Coreboot before, how could i register at this mailing list while I found it by Coreboot site!!? Go read wiki or the source code are the solutions I knew myself, i have the source and the Internet connection... On Tue, Jul 20, 2010 at 7:17 PM, and...@jenbo.dk and...@jenbo.dk wrote: All your questions are answered on the wiki, in the make file or in the docs. Go read them. Mvh Anders - Reply message - Fra: Rudolf Marek r.ma...@assembler.cz Dato: tir., jul. 20, 2010 15:52 Emne: [coreboot] compiling coreboot Til: ali hagigat hagigat...@gmail.com Cc: coreboot@coreboot.org You did not read my last email didn't you? Do you think we are an expert system to ask? Do you think we have time to waste with you? Of course not, if are not able to get this, go away and find some other people to bother. No, thanks, Rudolf Dne 20.7.2010 13:14, ali hagigat napsal(a): If i execute only this command at the root folder of Coreboot source tree : make Will the project be compiled with GCC of the system or GCC of the system will be patched and changed or it will be compiled exactly with regular GCC of the linux operating system? Besides will be the object files in elf format and when they are linked? Is there any possibility for other formats? -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] compiling coreboot
My first impression from the BIOS open source project was an effort to expand knowledge not to earn money!! If any one wants to earn money he will find a technical job, will get involved in deadlines of the project, will tolerate the pressure and stress of a challenging and rewarding work. I thought we were here to help each other to understand the details of the science and technology involved and become ready to invent something new or to become ready for the projects in the market. Though spending money for this case seems contrary to the first purposes of the project but money might be paid to responsible and eligible technical people. Who you recommend and where are those? I am ready to develop code for Coreboot but my knowledge is not enough and I suspect the knowledge of many users of this mailing list to be enough for it!! On Wed, Jul 21, 2010 at 3:56 PM, Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net wrote: Hi, let me explain a few things. On 21.07.2010 12:16, ali hagigat wrote: The reason some of you do not like to answer is not lack of time. It is because you do not want other people know about the details of the project, We will tell you about the details of our project if you are friendly and if you read the documentation. Rudolf, answering my questions take you not more than a few minutes of your time and it is not a waste of time. Answering technical questions are not a waste of time, never, as it is a kind of practice and helps people keep their knowledge updated or refreshed. I did not ask you about economics, politics and the subjects unrelated to computer science, how can i waste your time? It is something you can benefit from if you think about it unless you have other reasons (that I am aware of!!) We do not benefit from explaining things to you. You have shown an unwillingness to learn independently, so the project does not benefit from explaining things to you either. BUT... if you pay some of us _enough_ money, they will treat you as a customer and explain things to you even if you are unwilling to do any work yourself. Even if you promised to help us with developing coreboot, we would not benefit until the amount of development done by you saves other developers more time than they lose explaining things to you. We do not know you, and we have no way to make sure if you really intend to help or if you're just trolling. Your behaviour so far is pretty close to trolling. I asked some questions to understand the overall framework of the work without going into the details. I knew about the wiki site of Coreboot before, how could i register at this mailing list while I found it by Coreboot site!!? Apparently you found the wiki, but you're unwilling or unable to read and understand the main contents, and focused on the mailing list instructions instead. Go read wiki or the source code are the solutions I knew myself, i have the source and the Internet connection... And why don't you do that? You have three choices: 1. Be friendly. Read the source/documentation. We'll explain the rest. 2. Pay someone to explain this in private. 3. Leave. Regards, Carl-Daniel -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] compiling coreboot
If i execute only this command at the root folder of Coreboot source tree : make Will the project be compiled with GCC of the system or GCC of the system will be patched and changed or it will be compiled exactly with regular GCC of the linux operating system? Besides will be the object files in elf format and when they are linked? Is there any possibility for other formats? -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] .sv folder of coreboot
There is a .svn folder with some files and folders. How they are created? -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] romcc.c
What util/romcc/romcc.c does? It is over 25000 lines of code! -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] util files
Can any one mention a short comment for each directory inside util/ directory like abuild, amdtools, cbfstool, ., xcompile. What each tool does and what is its main functionality? I will be much appreciated. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] 3 questions about coreboot
Ok, thank you all for the replies, links and diagrams. But there are still some ambiguities in memory read/write after reset which is done by BIOS chip and then the memory controller !! Immediately after reset all memory read/write cycles are claimed by BIOS chip ultimately. The first question is that: Is memory controller enabled after reset before writing to its configuration space? If it is enabled, how it does not claim for memory addresses after reset? If it is not enabled and we enable the memory controller by writing to its configuration registers how we introduce the memory address range used by BIOS chip here? Because the memory controller should not claim the memory address range of the BIOS chip. I had a general look at the configuration registers of the memory controller, there is no register or registers to set this range of address!! Besides there is no enable bit or something similar!! These questions are repeated for BIOS chip and the PCI device connected to it. Do we have to write to their configuration registers to specify a specific range of address? Otherwise both memory controller and the PCI device connected to the BIOS chip will claim for that address!! Because they are being situated at the same PCI bus. On 7/7/10, FENG Yu Ning fengyuning1...@gmail.com wrote: Peter Stuge wrote: See http://stuge.se/pc2010.png for a sketch of the components in a contemporary PC. Great drawing, Peter. ali, I would like to add some detail. The picture mentioned by Peter show an architecture that is closer to the AMD ones, in which memory controller is integrated into the CPU. The 945 architecture has memory controller in the northbridge. The bridge chips have logic deciding if the coming address access should be responsed by it, or should be routed to somewhere else. As in 945, when an address comes from CPU, the northbridge decides whether the address access means a memory access, a configuration to the chip itself, or to other devices that connects to it. In the case of first instruction address, the northbridge will pass that request to southbridge. Read the chipset manual for more information. Some effort is is needed to extract what you want from the text. By the way, since my knowledge is still of the single core age and I know little about architectures other than Intel x86, my explanation may not be accurate. I think someone in the list will correct me if that was the case. yn -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] 3 questions about coreboot
Stefan, BIOS chip is not connected to CPU directly after reset!! It is connected to the south bridge and it is on the PCI bus. When CPU gets ready to read from F000:FFF0, this request travels to BIOS chip. I mean the hardware immediately accesses BIOS chip after reset but at some point all memory read/write cycles are claimed by 945 and memory controller? No, that assumption is not true. If not so what happens? CPU does not have address/data buses directly attached to the BIOS chip. Thank you to answer the questions. On Wed, Jul 7, 2010 at 2:16 PM, Stefan Reinauer stefan.reina...@coresystems.de wrote: On 7/7/10 6:42 AM, ali hagigat wrote: My chipset is Intel Core2Due/945/ICH7. I have 3 questions. First question: I wonder how PCI memory read cycles can read an instruction from F000:FFF0 right after reset which is the first instruction of BIOS. x86 CPUs are designed like that. Go read the Intel®64 and IA-32 Architectures Software Developer's Manuals: http://www.intel.com/products/processor/manuals/ Does Coreboot writes into PCI configuration space of Device 31 of ICH7-south bridge(LPC controller)? before initializing the configuration space of Device 0 of 82945(which is memory controller)? What do you mean by initializing the configuration space of Device 0 of 82945 ? Generally, a lot of work happens before RAM is initialized. Go read the source code for further details. I mean the hardware immediately accesses BIOS chip after reset but at some point all memory read/write cycles are claimed by 945 and memory controller? No, that assumption is not true. Second question: What is the code flow of Coreboot? Where does it start? and how it contines? It starts with the reset vector, which is in the bootblock. That bootblock loads further modules. Third question: Inside src/mainboard/kontron/986lcd- m/acpi we have some asl files. What language they have been written in? Like superio.asl The language is called ACPI Control Message Source Language (short: ASL). Go read http://www.acpi.info/DOWNLOADS/ACPIspec40a.pdf and http://acpica.org/documentation/ Stefan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Position Independent Code
Is Coreboot source code is a position independent code? I mean, will it be executed from any arbitrary location of the main memory? Can it be revoked and correctly executed by a bootloader like Grub if I make a binary image of it and make necessary changes to be read by Grub? -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] 3 questions about coreboot
My chipset is Intel Core2Due/945/ICH7. I have 3 questions. First question: I wonder how PCI memory read cycles can read an instruction from F000:FFF0 right after reset which is the first instruction of BIOS. Does Coreboot writes into PCI configuration space of Device 31 of ICH7-south bridge(LPC controller)? before initializing the configuration space of Device 0 of 82945(which is memory controller)? I mean the hardware immediately accesses BIOS chip after reset but at some point all memory read/write cycles are claimed by 945 and memory controller? Second question: What is the code flow of Coreboot? Where does it start? and how it contines? Third question: Inside src/mainboard/kontron/986lcd- m/acpi we have some asl files. What language they have been written in? Like superio.asl -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [commit] r5651 - trunk/util/superiotool
I have time 9 hours a day to help Coreboot project but I will never
write code before understanding all the details.
On 6/30/10, repository service s...@coreboot.org wrote:
Author: stepan
Date: Tue Jun 29 23:26:17 2010
New Revision: 5651
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5651
Log:
Add support to IT85xx series
Signed-off-by: Anton Kochkov anton.koch...@gmail.com
Acked-by: Stefan Reinauer ste...@coresystems.de
Modified:
trunk/util/superiotool/ite.c
Modified: trunk/util/superiotool/ite.c
==
--- trunk/util/superiotool/ite.c Tue Jun 29 23:13:20 2010(r5650)
+++ trunk/util/superiotool/ite.c Tue Jun 29 23:26:17 2010(r5651)
@@ -29,11 +29,110 @@
static const struct superio_registers reg_table[] = {
{0x8228, IT8228E, {
{EOT}}},
+ {0x8502, IT8502E/TE/G, {
+ {NOLDN, NULL,
+ {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29,
+ 0x2A,0x2B,0x2C,0x2D,0x2E,EOT},
+ {0x85,0x02,0x71,0x01,NANA,0x00,0x00,NANA,NANA,NANA,
+ NANA,NANA,NANA,0x00,NANA,EOT}},
+ {0x1, UART1,
+ {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0xf0,EOT},
+ {0x00,0x03,0xf8,0x00,0x00,0x04,0x02,0x00,EOT}},
+ {0x4, System Wake-Up,
+ {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0xf0,EOT},
+ {0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,EOT}},
+ {0x5, Mouse,
+ {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0xf0,EOT},
+ {0x01,0x00,0x00,0x00,0x00,0x0C,0x01,NANA,EOT}},
+ {0x6, Keyboard,
+ {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0xf0,EOT},
+ {0x01,0x00,0x60,0x00,0x64,0x01,0x01,NANA,EOT}},
+ {0xf, Shared Memory/Flash,
+ {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0xf4,0xf5,
+ 0xf6,EOT},
+ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,EOT}},
+ {0x10, BRAM,
+ {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0xf3,0xf4,
+ 0xf5,EOT},
+ {0x00,0x00,0x70,0x00,0x72,0x08,0x01,NANA,NANA,
+ NANA,EOT}},
+ {0x11, Power Channel 1,
+ {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT},
+
+ {0x00,0x00,0x62,0x00,0x66,0x01,0x01,EOT}},
+ {0x12, Power Channel 2,
+ {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT},
+ {0x00,0x00,0x68,0x00,0x6c,0x01,0x01,EOT}},
+ {0x17, Power Channel 3,
+ {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT},
+ {0x00,0x00,0x6a,0x00,0x6e,0x01,0x01,EOT}},
+ {EOT}}},
{0x8510, IT8510E/TE/G, {
{EOT}}},
{0x8511, IT8511E/TE/G, {
+ {NOLDN, NULL,
+ {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29,
+ 0x2A,0x2B,0x2C,0x2D,0x2E,EOT},
+ {0x85,0x11,0x10,0x01,NANA,0x00,0x00,NANA,NANA,NANA,
+ NANA,NANA,NANA,0x00,NANA,EOT}},
+ {0x4, System Wake-Up,
+ {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0xf0,EOT},
+ {0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,EOT}},
+ {0x5, Mouse,
+ {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0xf0,EOT},
+ {0x01,0x00,0x00,0x00,0x00,0x0C,0x03,NANA,EOT}},
+ {0x6, Keyboard,
+ {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0xf0,EOT},
+ {0x01,0x00,0x60,0x00,0x64,0x01,0x03,NANA,EOT}},
+ {0xf, Shared Memory/Flash,
+ {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0xf4,0xf5,
+ 0xf6,EOT},
+ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,EOT}},
+ {0x10, Real-Time Clock,
+ {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0xf0,0xf1,
+ 0xf2,0xf3,0xf4,0xf5,EOT},
+ {0x00,0x00,0x70,0x00,0x72,0x08,0x00,0x00,0x49,
+ 0x4A,NANA,NANA,NANA,EOT}},
+ {0x11, Power Channel 1,
+ {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT},
+ {0x00,0x00,0x62,0x00,0x66,0x01,0x03,EOT}},
+ {0x12, Power Channel 2,
+ {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT},
+ {0x00,0x00,0x68,0x00,0x6c,0x01,0x03,EOT}},
{EOT}}},
{0x8512, IT8512E/F/G, {
+ {NOLDN, NULL,
+ {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29,
+ 0x2A,0x2B,0x2C,0x2D,0x2E,EOT},
+ {0x85,0x12,0x22,0x01,NANA,0x00,0x00,NANA,NANA,NANA,
+
