[coreboot] [PATCH] i82801xx assign PIRQs in mainboard Config.lb or use default
This patch lets you assign PIRQs in mainboard Config.lb or use the default ones listed in i82801xx_lpc.c. Once and if everyone converts to the better way of assign PIRQs in mainboard Config.lb the option of using the defaults can be removed. The patch enables a margin of time to do so. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.orgIndex: src/southbridge/intel/i82801xx/i82801xx_lpc.c === --- src/southbridge/intel/i82801xx/i82801xx_lpc.c (revision 4250) +++ src/southbridge/intel/i82801xx/i82801xx_lpc.c (working copy) @@ -36,6 +36,8 @@ #define NMI_OFF 0 +typedef struct southbridge_intel_i82801xx_config config_t; + /* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control * 0x00 - = Reserved * 0x01 - 0001 = Reserved @@ -66,7 +68,11 @@ #define PIRQG 0x0A #define PIRQH 0x0B -/* Use 0x0ef8 for a bitmap to cover all these IRQ's. */ +/* + * Use 0x0ef8 for a bitmap to cover all these IRQ's. + * Use the defined IRQ values above or set mainboard + * specific IRQ values in your mainboards Config.lb. +*/ void i82801xx_enable_apic(struct device *dev) { @@ -114,18 +120,59 @@ static void i82801xx_pirq_init(device_t dev, uint16_t ich_model) { - /* Route PIRQA - PIRQD. */ - pci_write_config8(dev, PIRQA_ROUT, PIRQA); - pci_write_config8(dev, PIRQB_ROUT, PIRQB); - pci_write_config8(dev, PIRQC_ROUT, PIRQC); - pci_write_config8(dev, PIRQD_ROUT, PIRQD); + /* Get the chip configuration */ + config_t *config = dev->chip_info; + if (config->pirqa_routing) { + pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing); + } else { + pci_write_config8(dev, PIRQA_ROUT, PIRQA); + } + + if (config->pirqb_routing) { + pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing); + } else { + pci_write_config8(dev, PIRQB_ROUT, PIRQB); + } + + if (config->pirqc_routing) { + pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing); + } else { + pci_write_config8(dev, PIRQC_ROUT, PIRQC); + } + + if (config->pirqd_routing) { + pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing); + } else { + pci_write_config8(dev, PIRQD_ROUT, PIRQD); + } + /* Route PIRQE - PIRQH (for ICH2-ICH9). */ if (ich_model >= 0x2440) { - pci_write_config8(dev, PIRQE_ROUT, PIRQE); - pci_write_config8(dev, PIRQF_ROUT, PIRQF); - pci_write_config8(dev, PIRQG_ROUT, PIRQG); - pci_write_config8(dev, PIRQH_ROUT, PIRQH); + + if (config->pirqe_routing) { + pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing); + } else { + pci_write_config8(dev, PIRQE_ROUT, PIRQE); + } + + if (config->pirqf_routing) { + pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing); + } else { + pci_write_config8(dev, PIRQF_ROUT, PIRQF); + } + + if (config->pirqg_routing) { + pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing); + } else { + pci_write_config8(dev, PIRQG_ROUT, PIRQG); + } + + if (config->pirqh_routing) { + pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing); + } else { + pci_write_config8(dev, PIRQH_ROUT, PIRQH); + } } } Index: src/southbridge/intel/i82801xx/chip.h === --- src/southbridge/intel/i82801xx/chip.h (revision 4250) +++ src/southbridge/intel/i82801xx/chip.h (working copy) @@ -31,6 +31,18 @@ #define SOUTHBRIDGE_INTEL_I82801XX_CHIP_H struct southbridge_intel_i82801xx_config { + /** + * Interrupt Routing configuration + * If bit7 is 1, the interrupt is disabled. + */ + uint8_t pirqa_routing; + uint8_t pirqb_routing; + uint8_t pirqc_routing; + uint8_t pirqd_routing; + uint8_t pirqe_routing; + uint8_t pirqf_routing; + uint8_t pirqg_routing; + uint8_t pirqh_routing; }; extern struct chip_operations southbridge_intel_i82801xx_ops; -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] i82801xx assign PIRQs in mainboard Config.lb or use default
On Sat, 02 May 2009 11:15:32 -0400, Joseph Smith wrote: > This patch lets you assign PIRQs in mainboard Config.lb or use the default > ones listed in i82801xx_lpc.c. > Once and if everyone converts to the better way of assign PIRQs in > mainboard Config.lb the option of using the defaults can be removed. The > patch enables a margin of time to do so. > oh, thanks Stefan for the idea, tested, and Signed-off-by: Joseph Smith -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.orgIndex: src/southbridge/intel/i82801xx/i82801xx_lpc.c === --- src/southbridge/intel/i82801xx/i82801xx_lpc.c (revision 4250) +++ src/southbridge/intel/i82801xx/i82801xx_lpc.c (working copy) @@ -36,6 +36,8 @@ #define NMI_OFF 0 +typedef struct southbridge_intel_i82801xx_config config_t; + /* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control * 0x00 - = Reserved * 0x01 - 0001 = Reserved @@ -66,7 +68,11 @@ #define PIRQG 0x0A #define PIRQH 0x0B -/* Use 0x0ef8 for a bitmap to cover all these IRQ's. */ +/* + * Use 0x0ef8 for a bitmap to cover all these IRQ's. + * Use the defined IRQ values above or set mainboard + * specific IRQ values in your mainboards Config.lb. +*/ void i82801xx_enable_apic(struct device *dev) { @@ -114,18 +120,59 @@ static void i82801xx_pirq_init(device_t dev, uint16_t ich_model) { - /* Route PIRQA - PIRQD. */ - pci_write_config8(dev, PIRQA_ROUT, PIRQA); - pci_write_config8(dev, PIRQB_ROUT, PIRQB); - pci_write_config8(dev, PIRQC_ROUT, PIRQC); - pci_write_config8(dev, PIRQD_ROUT, PIRQD); + /* Get the chip configuration */ + config_t *config = dev->chip_info; + if (config->pirqa_routing) { + pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing); + } else { + pci_write_config8(dev, PIRQA_ROUT, PIRQA); + } + + if (config->pirqb_routing) { + pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing); + } else { + pci_write_config8(dev, PIRQB_ROUT, PIRQB); + } + + if (config->pirqc_routing) { + pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing); + } else { + pci_write_config8(dev, PIRQC_ROUT, PIRQC); + } + + if (config->pirqd_routing) { + pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing); + } else { + pci_write_config8(dev, PIRQD_ROUT, PIRQD); + } + /* Route PIRQE - PIRQH (for ICH2-ICH9). */ if (ich_model >= 0x2440) { - pci_write_config8(dev, PIRQE_ROUT, PIRQE); - pci_write_config8(dev, PIRQF_ROUT, PIRQF); - pci_write_config8(dev, PIRQG_ROUT, PIRQG); - pci_write_config8(dev, PIRQH_ROUT, PIRQH); + + if (config->pirqe_routing) { + pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing); + } else { + pci_write_config8(dev, PIRQE_ROUT, PIRQE); + } + + if (config->pirqf_routing) { + pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing); + } else { + pci_write_config8(dev, PIRQF_ROUT, PIRQF); + } + + if (config->pirqg_routing) { + pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing); + } else { + pci_write_config8(dev, PIRQG_ROUT, PIRQG); + } + + if (config->pirqh_routing) { + pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing); + } else { + pci_write_config8(dev, PIRQH_ROUT, PIRQH); + } } } Index: src/southbridge/intel/i82801xx/chip.h === --- src/southbridge/intel/i82801xx/chip.h (revision 4250) +++ src/southbridge/intel/i82801xx/chip.h (working copy) @@ -31,6 +31,18 @@ #define SOUTHBRIDGE_INTEL_I82801XX_CHIP_H struct southbridge_intel_i82801xx_config { + /** + * Interrupt Routing configuration + * If bit7 is 1, the interrupt is disabled. + */ + uint8_t pirqa_routing; + uint8_t pirqb_routing; + uint8_t pirqc_routing; + uint8_t pirqd_routing; + uint8_t pirqe_routing; + uint8_t pirqf_routing; + uint8_t pirqg_routing; + uint8_t pirqh_routing; }; extern struct chip_operations southbridge_intel_i82801xx_ops; -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] i82801xx assign PIRQs in mainboard Config.lb or use default
Very nice. Acked-by: Ronald G. Minnich -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] i82801xx assign PIRQs in mainboard Config.lb or use default
On Sat, 2 May 2009 13:39:53 -0700, ron minnich wrote: > Very nice. > > Acked-by: Ronald G. Minnich Thanks r4251 -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot