Re: [coreboot] G505s status (and test report)
Hi Florentin! As for adding support for Bolton and refactoring and unifying the FCH code, I would like to pick up the task, because I want to invest myself in coreboot dev again and I hope that I will have some time to spend in the near future... Great! IIRC someone in the IRC channel was also interested in the Bolton FCH; maybe you could work on that together. I don't remember the nickname though. But I need to understand a little bit more the current architecture of coreboot and also the impact of recent developpements like the (proposed) switch from AGESA to native init.. But just to have an idea of the complexity of this task (refactoring amd fch code) can you give me some details of what needs to be done? The FCH code of AGESA fam12, fam15tn and fam16kb isn't in a separate directory, but inside AGESA vendorcode. Which FCH code gets build, doesn't depend not on the southbridge Kconfig setting. Both fam12 and fam15tn trees include support for Hudson; the version in fam15tn is newer and likely has some bugfixes. The FCH code in fam16kb is different (Yangtze), but not too different. I'd try to move the FCH support out of the different vendorcode/agesa subtrees into one tree structure in vendorcode/ages. Maybe see http://review.coreboot.org/#/c/7782/ for something to begin your work. When moving the code out of the AGESA subtrees you should adapt the Kconfig stuff, so that the selection of the FCH code depends on the selected southbridge. That might involve some patching to the subtrees where you factor out the FCH support. When you have factored out the FCH vendorcode and somehow merged it into one directory structure where only the stuff relevant for one platform gets built, it should be relatively easy to extend the support for Bolton FCH. On the AGESA stuff: It seems that the internal tree has support for all different families in one tree and only the source code which is relevant for one family gets built for that family. Before the code drop for each family everything unneeded for that family was removed and the remaining stuff of that tree was released for that family. I can really recommend the 3 way folder compare mode of meld for the task of merging the 3 different FCH support code subtrees. fam12 and fam15tn have code for the same chips, but slightly different code; i'd use the newer version (fam15tn), since it likely contains some bugfixes. To get the XHCI support on Bolton working, you'd at least have to patch Hudson2XhciResetService.c; in that file the code matches onto the PCI ID of the XHCI controller, which changed between Hudson and Bolton. You likely need to patch some other stuff as well to get the XHCI controller working. When you have moved the FCH code out of the AGESA subtrees, it would be really great if you'd write native initialization for the FCH, which can be uses from both AGESA-based (maybe some glue code to AGESA is still needed for that) and native init based boards, but thats likely a non-trivial task. I hope that this helps you a bit; that was more or less everything i remember from working on that. The current state of the code isn't pretty, but you'll see that quite quickly... Also have a look at my (unfinished) Bolton support without working XHCI. Maybe it just needs the small patch that it also matches on the PCI ID of the XHCI controller in Bolton, but well, that would just be a hack. Regards Felix -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] G505s status (and test report)
Thank you Felix!
And also I see that your tool fch_xhci_rom_dumper is on github, great!..
As for adding support for Bolton and refactoring and unifying the FCH code, I
would like to pick up the task, because I want to invest myself in coreboot dev
again and I hope that I will have some time to spend in the near future...
But I need to understand a little bit more the current architecture of coreboot
and also the impact of recent developpements like the (proposed) switch from
AGESA to native init..
But just to have an idea of the complexity of this task (refactoring amd fch
code) can you give me some details of what needs to be done?
Regards,
Florentin
- Mail d'origine -
De: Felix Held <felix-coreb...@felixheld.de>
À: coreboot@coreboot.org
Envoyé: Sun, 08 Nov 2015 04:57:05 +0100 (CET)
Objet: Re: [coreboot] G505s status (and test report)
Hi Florentin!
> -3) The USB3 does NOT work : the 3rdparty xhci blob
> (${COREBOOT}/3rdparty/blobs/southbridge/amd/hudson/xhci.bin) is not correct!..
> PLEASE HELP : can someone give me a tip or advice, how to extract this blob
> (from uefi image or/sys/)?
You have to use the Bolton USB3 blob if you want to get USB3 somewhere
near working; it's in the blobs repo. The laptop uses a Bolton and not a
Hudson FCH, which have a newer version of the XHCI controller component
(I've verified that they have different boot-ROMs; my
fch_xhci_rom_dumper can extract both ).
I wrote some patch selecting the right blob (still somewhere in gerrit),
but you need to patch the vendorcode to get USB3 working (at least at
some place in the code it matches onto the PCI ID of the XHCI
controller, which is different). I stopped my efforts to add support for
Bolton to source AGESA, since doing stuff right would at least imply
refactoring and unifying the FCH code if not rewriting it and I'm not
really motivated to do that in my spare time.
Regards
Felix
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] G505s status (and test report)
Hi Florentin!
-3) The USB3 does NOT work : the 3rdparty xhci blob
(${COREBOOT}/3rdparty/blobs/southbridge/amd/hudson/xhci.bin) is not correct!..
PLEASE HELP : can someone give me a tip or advice, how to extract this blob (from
uefi image or/sys/)?
You have to use the Bolton USB3 blob if you want to get USB3 somewhere
near working; it's in the blobs repo. The laptop uses a Bolton and not a
Hudson FCH, which have a newer version of the XHCI controller component
(I've verified that they have different boot-ROMs; my
fch_xhci_rom_dumper can extract both ).
I wrote some patch selecting the right blob (still somewhere in gerrit),
but you need to patch the vendorcode to get USB3 working (at least at
some place in the code it matches onto the PCI ID of the XHCI
controller, which is different). I stopped my efforts to add support for
Bolton to source AGESA, since doing stuff right would at least imply
refactoring and unifying the FCH code if not rewriting it and I'm not
really motivated to do that in my spare time.
Regards
Felix
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] G505s status (and test report)
Hello all,
I would like to present here a brief report of my first tests with coreboot on
the G505s laptop.
First of all I would like to thank Zaolin for his enormous help (which went
even to hw hacking.. ;-)) and Paul Kocialkowski for his advices.
In a nutshell : it MOSTLY works with a recent release of coreboot => linux
(ubuntu 14.04) correctly boots in graphical mode and with networking support.
Test setup :
- Coreboot release : commit 439a527014fa0cb3e4ef60ba59e5c57c737b (head of
4.2 branch ?)
- Install method : external programmer (flashrom on beagleboard);
- OS : Ubuntu Trusty Tahr 14.04LTS
Problems:
-1) On the HW side : like with (almost) every laptop it is better to have an
interface for external flashing. But it is difficult to access the winbond
flash on the MB to solder wires for the flashing connecter : practically the
laptop has to be (almost) completely disassembled and the MB extracted;
-2) The video bios binary blob has to be extracted from the original bios and
added to the coreboot image. The method based on the unpacking of the original
uefi bios doesn't work (and also the id of the video device doesn't match!!..)
so the VBIOS image has to be dumped from /sys/devices//rom;
-3) The USB3 does NOT work : the 3rdparty xhci blob
(${COREBOOT}/3rdparty/blobs/southbridge/amd/hudson/xhci.bin) is not correct!..
PLEASE HELP : can someone give me a tip or advice, how to extract this blob
(from uefi image or /sys/)?
-4) The "internal" flashing method does NOT work : even after booting with
coreboot and "requesting a brick", flashrom says something like "read/write
methods not implemented" even after detencting the flash chip. (I was using the
"flashrom" of the ubuntu distrib..)
I will fix the wiki page for this laptop after doing some additional tests.
Best regards,
Florentin
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
