[coreboot] H8QME-2+ IRQ assignment and AMD 8132
Hello, over this week I've tried to do a proper IRQ assignment on the H8QME-2+ I've got here. So opened mp_tables.c and started changing the irq routing values with those I got form the board booting with a factory bios. Then I started giving the devices the irq they have when boot with factory bios and it booted without any problems except for two things first of all the two NICs still have irq 0 and thats because they are not pending on the mcp55 as they are on the "donator" board but on a AMD 8132 tunnel devices that is hanging on a different node: socketF(node3) --- socketF(node2) || socketF(node1) --- socketF(node0) || |ht |ht || AMD8132MCP55 |-- LAN| |-- SCSI |-- SATA |-- ATI ES 1000 |-- USB |-- PCI | lpc SIO I started adding the AMD8132 to the get_bus_conf.c code, by adding I mean stealing code from other boards pasting it to get_bus_conf and trying to make it work ;). So the problem there is that coreboot won't boot with the new code but not because the code is incorrect because it wasn't even executed, I know that because coreboot soft resets in middle of cpu initialization. I already increased Stack size up to 0x1 more makes the boot sequence fail. My second problem is the, irq_tables.c code I tried to customize for this board. I first tried the handy tool that comes with coreboot that auto-generates the irq_tables.c file but it doesn't compile with my board but I at least was able to use the information to modify the already existing irq_tables.c. So before doing changes the dump_irq output look like that: Interrupt routing table found at address 0xf55bb: Version 106.117, size 0x8366 Interrupt router is device 3d:17.4 PCI exclusive interrupt mask: 0x0fde [1,2,3,4,6,7,8,9,10,11] Compatible router: vendor 0x device 0x6075 Device d2:00.2 (slot 106): INTA: link 0x54, irq mask 0x0005 [0,2] INTB: link 0x40, irq mask 0xc839 [0,3,4,5,11,14,15] INTC: link 0x72, irq mask 0x84f7 [0,1,2,4,5,6,7,10,15] INTD: link 0xd2, irq mask 0x4275 [0,2,4,5,6,9,14] Device 83:19.2 (slot 195): INTA: link 0xff, irq mask 0x74b8 [3,4,5,7,10,12,13,14] INTB: link 0x74, irq mask 0x000f [0,1,2,3] INTC: link 0xe8, irq mask 0x9f77 [0,1,2,4,5,6,8,9,10,11,12,15] INTD: link 0xff, irq mask 0x89ff [0,1,2,3,4,5,6,7,8,11,15] Interrupt router at 3d:17.4: Could not read router info from /proc/bus/pci/3d/17.4. and after compiling with the new irq_tables.c I've got the exact same output! So no changes were applied, I cleaned everything before compiling so no doubt I compiled the correct file. So why is it still the same? (I attached a dump_irq output from the board with factory bios). And last but not least, at linux bootup it complains to find only 2 cpus but 16 cores later doing a lspci I can see all 4 cpus (18.0, 19,0 1a.0, 1b.0) and Linux only recognizes 8GB of ram but there are 16GB installed! Thanks in advanced and have a nice weekend, Knut Kujat. Interrupt routing table found at address 0xf4e30: Version 1.0, size 0x01b0 Interrupt router is device 00:01.0 PCI exclusive interrupt mask: 0x [] Compatible router: vendor 0x10de device 0x0364 Device 00:01.0 (slot 0): ISA bridge INTA: link 0x02, irq mask 0x4ca0 [5,7,10,11,14] INTB: link 0x05, irq mask 0x4ca0 [5,7,10,11,14] Device 00:02.0 (slot 0): USB Controller INTA: link 0x08, irq mask 0x4ca0 [5,7,10,11,14] INTB: link 0x03, irq mask 0x4ca0 [5,7,10,11,14] Device 00:08.0 (slot 0): INTA: link 0x0a, irq mask 0x4ca0 [5,7,10,11,14] Device 00:09.0 (slot 0): INTA: link 0x09, irq mask 0x4ca0 [5,7,10,11,14] Device 00:05.0 (slot 0): IDE interface INTA: link 0x07, irq mask 0x4ca0 [5,7,10,11,14] INTB: link 0x06, irq mask 0x4ca0 [5,7,10,11,14] INTC: link 0x0f, irq mask 0x4ca0 [5,7,10,11,14] Device 00:06.0 (slot 0): PCI bridge INTB: link 0x0b, irq mask 0x4ca0 [5,7,10,11,14] Device 00:0f.0 (slot 0): PCI bridge INTA: link 0x85, irq mask 0x4ca0 [5,7,10,11,14] INTB: link 0x86, irq mask 0x4ca0 [5,7,10,11,14] INTC: link 0x87, irq mask 0x4ca0 [5,7,10,11,14] INTD: link 0x84, irq mask 0x4ca0 [5,7,10,11,14] Device 07:00.0 (slot 32): INTA: link 0x85, irq mask 0x4ca0 [5,7,10,11,14] INTB: link 0x86, irq mask 0x4ca0 [5,7,10,11,14] INTC: link 0x87, irq mask 0x4ca0 [5,7,10,11,14] INTD: link 0x84, irq mask 0x4ca0 [5,7,10,11,14] Device 00:0e.0 (slot 0): PCI bridge INTA: link 0x86, irq mask 0x4ca0 [5,7,10,11,14] INTB: link 0x87, irq mask 0x4ca0 [5,7,10,11,14] INTC: link 0x84, irq mask 0x4ca0 [5,7,10,11,
Re: [coreboot] H8QME-2+ IRQ assignment and AMD 8132
Knut Kujat escribió: > Hello, > > over this week I've tried to do a proper IRQ assignment on the H8QME-2+ > I've got here. So opened mp_tables.c and started changing the irq > routing values with those I got form the board booting with a factory > bios. Then I started giving the devices the irq they have when boot with > factory bios and it booted without any problems except for two things > first of all the two NICs still have irq 0 and thats because they are > not pending on the mcp55 as they are on the "donator" board but on a AMD > 8132 tunnel devices that is hanging on a different node: > > socketF(node3) --- socketF(node2) >|| > socketF(node1) --- socketF(node0) >|| >|ht |ht >|| > AMD8132MCP55 >|-- LAN| >|-- SCSI |-- SATA > |-- ATI ES 1000 > |-- USB > |-- PCI > | lpc > SIO > I started adding the AMD8132 to the get_bus_conf.c code, by adding I > mean stealing code from other boards pasting it to get_bus_conf and > trying to make it work ;). So the problem there is that coreboot won't > boot with the new code but not because the code is incorrect because it > wasn't even executed, I know that because coreboot soft resets in middle > of cpu initialization. I already increased Stack size up to 0x1 more > makes the boot sequence fail. > > My second problem is the, irq_tables.c code I tried to customize for > this board. I first tried the handy tool that comes with coreboot that > auto-generates the irq_tables.c file but it doesn't compile with my > board but I at least was able to use the information to modify the > already existing irq_tables.c. So before doing changes the dump_irq > output look like that: > > Interrupt routing table found at address 0xf55bb: > Version 106.117, size 0x8366 > Interrupt router is device 3d:17.4 > PCI exclusive interrupt mask: 0x0fde [1,2,3,4,6,7,8,9,10,11] > Compatible router: vendor 0x device 0x6075 > > Device d2:00.2 (slot 106): > INTA: link 0x54, irq mask 0x0005 [0,2] > INTB: link 0x40, irq mask 0xc839 [0,3,4,5,11,14,15] > INTC: link 0x72, irq mask 0x84f7 [0,1,2,4,5,6,7,10,15] > INTD: link 0xd2, irq mask 0x4275 [0,2,4,5,6,9,14] > > Device 83:19.2 (slot 195): > INTA: link 0xff, irq mask 0x74b8 [3,4,5,7,10,12,13,14] > INTB: link 0x74, irq mask 0x000f [0,1,2,3] > INTC: link 0xe8, irq mask 0x9f77 [0,1,2,4,5,6,8,9,10,11,12,15] > INTD: link 0xff, irq mask 0x89ff [0,1,2,3,4,5,6,7,8,11,15] > > Interrupt router at 3d:17.4: > Could not read router info from /proc/bus/pci/3d/17.4. > > and after compiling with the new irq_tables.c I've got the exact same > output! So no changes were applied, I cleaned everything before > compiling so no doubt I compiled the correct file. So why is it still > the same? (I attached a dump_irq output from the board with factory bios). > > And last but not least, at linux bootup it complains to find only 2 cpus > but 16 cores later doing a lspci I can see all 4 cpus (18.0, 19,0 1a.0, > 1b.0) and Linux only recognizes 8GB of ram but there are 16GB installed! > > Thanks in advanced and have a nice weekend, > Knut Kujat. > Hello, I fixed the 2 cpu and just 8 GB ram issues, now linux finds all 4 cpus and 16 GB. But I'm still having trouble adding AMD 8132 for giving the NICs IRQ. THX, Knut Kujat. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] H8QME-2+ IRQ assignment and AMD 8132
Knut Kujat wrote: > I fixed the 2 cpu and just 8 GB ram issues, How? //Peter -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] H8QME-2+ IRQ assignment and AMD 8132
Peter Stuge escribió: > Knut Kujat wrote: > >> I fixed the 2 cpu and just 8 GB ram issues, >> > > How? > > > //Peter > > The board I'm porting from has only 2 CPUs and 8 memory slots so I had spd_addr.h configured only for those 8 memory slots. The H8QME-2+ has 4 CPUs and 16 memory slots so I had to add those extra 8 slots for 2 new nodes to that file. THX, Knut Kujat. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] H8QME-2+ IRQ assignment and AMD 8132
Knut Kujat wrote: > >> I fixed the 2 cpu and just 8 GB ram issues, > > > > How? > > The board I'm porting from has only 2 CPUs and 8 memory slots so I had > spd_addr.h configured only for those 8 memory slots. The H8QME-2+ has 4 > CPUs and 16 memory slots so I had to add those extra 8 slots for 2 new > nodes to that file. Aha! Thanks for the explanation! :) //Peter -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
