[coreboot] IMB-A180 based design question regarding interrupts
We are testing coreboot with our new IMB-A180 based AGESA design, and DMA interrupts are not functioning. I am looking into the Coreboot Options, but is there a recipie for enabling legacy interrupts in AGESA? We configure in Linux at IRQ 17. Thanks in advance, Mark Mason Engineering Design Team -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] IMB-A180 based design question regarding interrupts
Mark C. Mason [mailto:m...@edt.com] wrote: ]We are testing coreboot with our new IMB-A180 based AGESA design, ]and DMA interrupts are not functioning. I am looking into the Coreboot ]Options, but is there a recipie for enabling legacy interrupts in AGESA? ]We configure in Linux at IRQ 17. ] ]Thanks in advance, ] ]Mark Mason ]Engineering Design Team By legacy interrupts, do you mean the interrupt configuration when PIC mode interrupt handling is in use, or do you mean the routing of interrupts from a legacy device to an I/O APIC interrupt number? You mention Linux so I think the latter. It looks like agesa programs only APIC mode interrupt routing, and not the PIC mode routing used by older operating systems. The agesa programming is not configurable, as far as I can tell (see FchInternalDeviceIrqForApicMode[] in file HwAcpiLate.c). Your own code reprogram this routing. See IOC00 Pci_Intr_Index in the Kabini BKDG: http://developer.amd.com/resources/documentation-articles/developer-guides-manuals/ Thanks, Scott -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] IMB-A180 based design question regarding interrupts
We were able to resolve this by enabling MSI interrupts in our PCIe core and our Linux device driver. Thanks go to Scott Duplichan for his helpful guidance. Mark Mason Engineering Design Team We are testing coreboot with our new IMB-A180 based AGESA design, and DMA interrupts are not functioning. I am looking into the Coreboot Options, but is there a recipie for enabling legacy interrupts in AGESA? We configure in Linux at IRQ 17. Thanks in advance, Mark Mason Engineering Design Team -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] IMB-A180 based design question regarding interrupts
Mark C. Mason wrote: > We were able to resolve this by enabling MSI interrupts in our PCIe core > and our Linux device driver. That's a good workaround, but clearly doesn't actually resolve the problem. The problem still exists; coreboot fails to initialize the system completely in some cases. I don't think that's very useful. It is perfectly fine to have known limitations, we are all short on time, but all coreboot developers out there, please hear this plea: If you contribute some code which you know to leave huge gaps in functionality gaping open then you need to DOCUMENT that, or of course ideally close the gaps before publishing the code in the first place. If you *don't know* whether there are gaps, then you can be pretty sure that there are plenty of them. Worthless coreboot code is worthless. I don't think we are all working on coreboot so that we can create a hotchpotch of random blobs and million line code drops - at least I'm not. Are you? //Peter -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] IMB-A180 based design question regarding interrupts
Mark, You may want to look at two patches that are still in review... http://review.coreboot.org/#/c/6065/ ports the CIMX changes to agesa http://review.coreboot.org/#/c/5948/ makes use of the PCI INT support on hp/abm (as an example) Dave On Thu, Jun 19, 2014 at 1:42 PM, Peter Stuge wrote: > Mark C. Mason wrote: > > We were able to resolve this by enabling MSI interrupts in our PCIe core > > and our Linux device driver. > > That's a good workaround, but clearly doesn't actually resolve the > problem. The problem still exists; coreboot fails to initialize the > system completely in some cases. > > I don't think that's very useful. It is perfectly fine to have known > limitations, we are all short on time, but all coreboot developers > out there, please hear this plea: > > If you contribute some code which you know to leave huge gaps in > functionality gaping open then you need to DOCUMENT that, or of > course ideally close the gaps before publishing the code in the > first place. > > If you *don't know* whether there are gaps, then you can be pretty > sure that there are plenty of them. > > Worthless coreboot code is worthless. > > I don't think we are all working on coreboot so that we can create a > hotchpotch of random blobs and million line code drops - at least I'm not. > > Are you? > > > //Peter > > -- > coreboot mailing list: coreboot@coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
