[coreboot] Query regarding CoreBoot
Hi, I wanted to ask if coreboot is capable of booting macOS. There are bootloaders like clover and opencore that does the job but does coreboot do this thing with more efficiency? ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Query related to GSoC 2020
Hey, I am Shridhara Hegde, a 2nd year Computer Science & Engineering student from Bangalore, India. I came across the coreboot GSoC page and noticed C programming listed as a technology used in the projects. I have a decent understanding of the basics of C such as pointers, dynamic memory allocation and file handling. Kindly let me know if these skills are even remotely sufficient to be of any good use at any coreboot projects and what more do I need to learn in order get selected as a part of GSoC in the future. Thank YouShridhara. ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
Re: [coreboot] Query to release the code for new board
Hi Mayuri, coreboot does not share the TXE or descriptor.bin files for the boards. In the instructions from Intel for the BayleyBay CRB, it tells you to build coreboot as a 3MB rom file and to flash that to the top of the ROM chip, so as to not overwrite the TXE & Descriptor on the board. That said, since you own a Minnowboard Turbot, you can get the full UEFI rom file and extract the descriptor & TXE files from there using ifdtool -x. See the build script for the Minnowboard Max: https://review.coreboot.org/gitweb/cgit/board-status.git/tree/intel/minnowmax/4.2-429-g4013469/2015-11-30T20_21_41Z/mk_minnowmax.sh Martin On Thu, Jul 14, 2016 at 1:23 PM, Mayuri Tendulkar wrote: > Hi Team > > > > I would like to know how process of releasing code for new board works in > coreboot community? > > > > For example, when BayleyBay CRB or Minnowboard Max was release, is it only > code changes released, mainly related to Mainboard. > > > > How TXE and Descriptor.bin for these openly available boards are shared with > community? > > > > Regards > > Mayuri > > "DISCLAIMER: This message is proprietary to Aricent and is intended solely > for the use of the individual to whom it is addressed. It may contain > privileged or confidential information and should not be circulated or used > for any purpose other than for what it is intended. If you have received > this message in error, please notify the originator immediately. If you are > not the intended recipient, you are notified that you are strictly > prohibited from using, copying, altering, or disclosing the contents of this > message. Aricent accepts no responsibility for loss or damage arising from > the use of the information transmitted by this email including damage from > virus." > > -- > coreboot mailing list: coreboot@coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Query to release the code for new board
Hi Team I would like to know how process of releasing code for new board works in coreboot community? For example, when BayleyBay CRB or Minnowboard Max was release, is it only code changes released, mainly related to Mainboard. How TXE and Descriptor.bin for these openly available boards are shared with community? Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Query regarding coreboot for new intel customized board
Hello Mayuri, You need to play (maybe, just a kludge) a bit with Coreboot "make menuconfig", and there with console setup: [image: Inline image 1] You also might want to install on your Linux distro PuTTY console (given UBUNTU apt-get and Fedora dnf commands), to set your Rx terminal correctly (at least, I know PuTTY well, always worked for me): sudo apt-get/dnf install putty Zoran On Thu, May 26, 2016 at 6:33 AM, Mayuri Tendulkar < mayuri.tendul...@aricent.com> wrote: > Thanks Vim. > > > > Currently I am not able to get any serial prints out on my reference board. > > > > My board is based on Intel ISX board based on Baytrail-I soc E3825 given > below. > > > > > https://www-ssl.intel.com/content/www/us/en/embedded/design-tools/evaluation-platforms/atom-e3800-dev-kit-isx-ref-design-product-brief.html > > > > I have built coreboot for this, but unable to get serial prints. > > > > How I should debug this further. > > > > Regards > > Mayuri > > > > *From:* Wim Vervoorn [mailto:wvervo...@eltan.com] > *Sent:* 24 May 2016 13:26 > *To:* Mayuri Tendulkar > *Subject:* Re: Query regarding coreboot for new intel customized board > > > > Hello Mayuri, > > > > If your rom image is the same it could be due to the lack of support for > the flash device you are using. The MRC cache is preserved in flash so you > need to be able to write it. > > > > For the others the numbers etc you mention are informational for the OS. > They are not strictly required but the OS builds a registry of the items it > retrieves from the SMBIOS. If you don’t require this you could also disable > the functionality. > > > > > > Best Regards, > > Wim Vervoorn > > > > Eltan B.V. > > Ambachtstraat 23 > > 5481 SM Schijndel > > The Netherlands > > > > T : +31-(0)73-594 46 64 > > E : wvervo...@eltan.com > > W : http://www.eltan.com > > "THIS MESSAGE CONTAINS CONFIDENTIAL INFORMATION. UNLESS YOU ARE THE > INTENDED RECIPIENT OF THIS MESSAGE, ANY USE OF THIS MESSAGE IS STRICTLY > PROHIBITED. IF YOU HAVE RECEIVED THIS MESSAGE IN ERROR, PLEASE IMMEDIATELY > NOTIFY THE SENDER BY TELEPHONE +31-(0)73-5944664 OR REPLY EMAIL, AND > IMMEDIATELY DELETE THIS MESSAGE AND ALL COPIES." > > > > > > > > > > > > *From:* coreboot [mailto:coreboot-boun...@coreboot.org > ] *On Behalf Of *Mayuri Tendulkar > *Sent:* Tuesday, May 24, 2016 7:26 AM > *To:* coreboot > *Subject:* [coreboot] Query regarding coreboot for new intel customized > board > > > > Hi team > > > > I am working on building coreboot for one of our customized board. This is > based on Intel ISX board reference design, reference can be taken as > Minnowboard or BayleyBay CRB. > > > > As per documentation given under coreboot, I created folder with my board > name under src/intel/mainboard/xxx and did changes required. > > > > If I tried the coreboot with these changes on minnowboard, it got stuck at > FSP MRC Cache not found. > > > > But if the same code changes I copied under src/intel/mainboard/minnowmax > and built, it booted fine. > > > > I would like to know what is the importance of these board names, SMBIOS > table name, serial no which are defined for Minnowmax. > > > > Is there some master registry where all these are stored, and if any new > entry comes, how we should add it. > > > > Regards > > Mayuri > > > > > > "DISCLAIMER: This message is proprietary to Aricent and is intended solely > for the use of the individual to whom it is addressed. It may contain > privileged or confidential information and should not be circulated or used > for any purpose other than for what it is intended. If you have received > this message in error, please notify the originator immediately. If you are > not the intended recipient, you are notified that you are strictly > prohibited from using, copying, altering, or disclosing the contents of > this message. Aricent accepts no responsibility for loss or damage arising > from the use of the information transmitted by this email including damage > from virus." > "DISCLAIMER: This message is proprietary to Aricent and is intended solely > for the use of the individual to whom it is addressed. It may contain > privileged or confidential information and should not be circulated or used > for any purpose other than for what it is intended. If you have received > this message in error, please notify the originator immediately. If you are > not the intended recipient, you are notified that you are strictly > prohibited from using, copying, altering, or disclosing the contents of > this message. Aricent accepts no responsibility for loss or damage arising > from the use of the information transmitted by this email including damage > from virus." > > -- > coreboot mailing list: coreboot@coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot > -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Query regarding coreboot for new intel customized board
That looks a lot like the Valley Island design. I was able to get serial output by overwriting coreboot (last 2MB of the 8MB bios chip) on the bios that comes with it. However as you will see in the history of emails still get stuck during the boot process. Hope the above helps you get further. From: coreboot [mailto:coreboot-boun...@coreboot.org] On Behalf Of Mayuri Tendulkar Sent: Thursday, 26 May 2016 12:33 PM To: Wim Vervoorn; coreboot Subject: Re: [coreboot] Query regarding coreboot for new intel customized board Thanks Vim. Currently I am not able to get any serial prints out on my reference board. My board is based on Intel ISX board based on Baytrail-I soc E3825 given below. https://www-ssl.intel.com/content/www/us/en/embedded/design-tools/evaluation-platforms/atom-e3800-dev-kit-isx-ref-design-product-brief.html I have built coreboot for this, but unable to get serial prints. How I should debug this further. Regards Mayuri From: Wim Vervoorn [mailto:wvervo...@eltan.com] Sent: 24 May 2016 13:26 To: Mayuri Tendulkar mailto:mayuri.tendul...@aricent.com>> Subject: Re: Query regarding coreboot for new intel customized board Hello Mayuri, If your rom image is the same it could be due to the lack of support for the flash device you are using. The MRC cache is preserved in flash so you need to be able to write it. For the others the numbers etc you mention are informational for the OS. They are not strictly required but the OS builds a registry of the items it retrieves from the SMBIOS. If you don't require this you could also disable the functionality. Best Regards, Wim Vervoorn Eltan B.V. Ambachtstraat 23 5481 SM Schijndel The Netherlands T : +31-(0)73-594 46 64 E : wvervo...@eltan.com<mailto:wvervo...@eltan.com> W : http://www.eltan.com "THIS MESSAGE CONTAINS CONFIDENTIAL INFORMATION. UNLESS YOU ARE THE INTENDED RECIPIENT OF THIS MESSAGE, ANY USE OF THIS MESSAGE IS STRICTLY PROHIBITED. IF YOU HAVE RECEIVED THIS MESSAGE IN ERROR, PLEASE IMMEDIATELY NOTIFY THE SENDER BY TELEPHONE +31-(0)73-5944664 OR REPLY EMAIL, AND IMMEDIATELY DELETE THIS MESSAGE AND ALL COPIES." From: coreboot [mailto:coreboot-boun...@coreboot.org] On Behalf Of Mayuri Tendulkar Sent: Tuesday, May 24, 2016 7:26 AM To: coreboot mailto:coreboot@coreboot.org>> Subject: [coreboot] Query regarding coreboot for new intel customized board Hi team I am working on building coreboot for one of our customized board. This is based on Intel ISX board reference design, reference can be taken as Minnowboard or BayleyBay CRB. As per documentation given under coreboot, I created folder with my board name under src/intel/mainboard/xxx and did changes required. If I tried the coreboot with these changes on minnowboard, it got stuck at FSP MRC Cache not found. But if the same code changes I copied under src/intel/mainboard/minnowmax and built, it booted fine. I would like to know what is the importance of these board names, SMBIOS table name, serial no which are defined for Minnowmax. Is there some master registry where all these are stored, and if any new entry comes, how we should add it. Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Query regarding coreboot for new intel customized board
Thanks Vim. Currently I am not able to get any serial prints out on my reference board. My board is based on Intel ISX board based on Baytrail-I soc E3825 given below. https://www-ssl.intel.com/content/www/us/en/embedded/design-tools/evaluation-platforms/atom-e3800-dev-kit-isx-ref-design-product-brief.html I have built coreboot for this, but unable to get serial prints. How I should debug this further. Regards Mayuri From: Wim Vervoorn [mailto:wvervo...@eltan.com] Sent: 24 May 2016 13:26 To: Mayuri Tendulkar Subject: Re: Query regarding coreboot for new intel customized board Hello Mayuri, If your rom image is the same it could be due to the lack of support for the flash device you are using. The MRC cache is preserved in flash so you need to be able to write it. For the others the numbers etc you mention are informational for the OS. They are not strictly required but the OS builds a registry of the items it retrieves from the SMBIOS. If you don't require this you could also disable the functionality. Best Regards, Wim Vervoorn Eltan B.V. Ambachtstraat 23 5481 SM Schijndel The Netherlands T : +31-(0)73-594 46 64 E : wvervo...@eltan.com<mailto:wvervo...@eltan.com> W : http://www.eltan.com "THIS MESSAGE CONTAINS CONFIDENTIAL INFORMATION. UNLESS YOU ARE THE INTENDED RECIPIENT OF THIS MESSAGE, ANY USE OF THIS MESSAGE IS STRICTLY PROHIBITED. IF YOU HAVE RECEIVED THIS MESSAGE IN ERROR, PLEASE IMMEDIATELY NOTIFY THE SENDER BY TELEPHONE +31-(0)73-5944664 OR REPLY EMAIL, AND IMMEDIATELY DELETE THIS MESSAGE AND ALL COPIES." From: coreboot [mailto:coreboot-boun...@coreboot.org] On Behalf Of Mayuri Tendulkar Sent: Tuesday, May 24, 2016 7:26 AM To: coreboot mailto:coreboot@coreboot.org>> Subject: [coreboot] Query regarding coreboot for new intel customized board Hi team I am working on building coreboot for one of our customized board. This is based on Intel ISX board reference design, reference can be taken as Minnowboard or BayleyBay CRB. As per documentation given under coreboot, I created folder with my board name under src/intel/mainboard/xxx and did changes required. If I tried the coreboot with these changes on minnowboard, it got stuck at FSP MRC Cache not found. But if the same code changes I copied under src/intel/mainboard/minnowmax and built, it booted fine. I would like to know what is the importance of these board names, SMBIOS table name, serial no which are defined for Minnowmax. Is there some master registry where all these are stored, and if any new entry comes, how we should add it. Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Query regarding coreboot for new intel customized board
Hi team I am working on building coreboot for one of our customized board. This is based on Intel ISX board reference design, reference can be taken as Minnowboard or BayleyBay CRB. As per documentation given under coreboot, I created folder with my board name under src/intel/mainboard/xxx and did changes required. If I tried the coreboot with these changes on minnowboard, it got stuck at FSP MRC Cache not found. But if the same code changes I copied under src/intel/mainboard/minnowmax and built, it booted fine. I would like to know what is the importance of these board names, SMBIOS table name, serial no which are defined for Minnowmax. Is there some master registry where all these are stored, and if any new entry comes, how we should add it. Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Query
Hi Damany, On 03/08/2016 12:00 PM, Damany Reid wrote: Good Day, My name is Damany and I’m new to the area of open source software contributing. I learnt of the opportunities afforded through Google Summer of Code and I’m just wondering if I’m qualified enough to participate in your project. Im first year in university learning c which i would have completed it by the end of this semester, before summer. Thanks in advance, Damany Please feel free to look around, see if you like the project, and could imagine contributing to one of our GSoC projects: https://www.coreboot.org/GSoC You will find the requirements and sub projects there. Of course you can also suggest your own project. Stefan -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Query
Good Day, My name is Damany and I’m new to the area of open source software contributing. I learnt of the opportunities afforded through Google Summer of Code and I’m just wondering if I’m qualified enough to participate in your project. Im first year in university learning c which i would have completed it by the end of this semester, before summer. Thanks in advance, Damany -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Query regarding gsoc project
Respected sir, I am a computer engineering student.Sir I have been reading all the available resources on the net about the firmwares and seriously I am very upset at the present trend.Sir I am preparing one project using coreboot but I have a doubt.Sir if I can understand all the working of current uefi I will need my own hardware to implement it that is a bit impractical... For now and for the hardware vendors to accept my proposal I will need to propose a design better than uefi and make them believe acctually it is better...which will take a long time so y don't we just get a way in between these two and somehow try to reverse engineer the RAM cryptography of uefi is it possible???will it help??? -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Query regarding gsoc project
Hi Kumar, Thanks for your interest in coreboot GSoC. I recommend that you focus on a small part of coreboot and become more familiar with how it works. You should get it booting in qemu. Having hardware to work on is important, so you should identify which hardware is most relevant to you and see what is supported and what support you would need to add. Regards, Marc On Sat, Mar 21, 2015 at 9:40 AM Kushagra Kumar wrote: > Respected sir, I am a computer engineering student.Sir I have been reading > all the available resources on the net about the firmwares and seriously I > am very upset at the present trend.Sir I am preparing one project using > coreboot but I have a doubt.Sir if I can understand all the working of > current uefi I will need my own hardware to implement it that is a bit > impractical... For now and for the hardware vendors to accept my proposal I > will need to propose a design better than uefi and make them believe > acctually it is better...which will take a long time so y don't we just get > a way in between these two and somehow try to reverse engineer the RAM > cryptography of uefi is it possible???will it help??? > -- > coreboot mailing list: coreboot@coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Query 2
Do we need to do it without making the uefi mainframe aware...and we don't need to break the chain of trust or else I will lend up in a hash? -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Query regarding gsoc project
Respected sir, I am a computer engineering student.Sir I have been reading all the available resources on the net about the firmwares and seriously I am very upset at the present trend.Sir I am preparing one project using coreboot but I have a doubt.Sir if I can understand all the working of current uefi I will need my own hardware to implement it that is a bit impractical... For now and for the hardware vendors to accept my proposal I will need to propose a design better than uefi and make them believe acctually it is better...which will take a long time so y don't we just get a way in between these two and somehow try to reverse engineer the RAM cryptography of uefi is it possible???will it help??? -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Query, known-good CPUs to use in a H8DME-2 mb?
On Fri, May 07, 2010 at 01:59:12PM -0400, Joe Korty wrote: > What AMD Processor model numbers have you folks been using > on the SuperMicro H8DME-2 mainboards? I'd like to buy a > pair of known-working CPUs. > > I currently have a pair of AMD model #2378 Processors, > which are of the fam10 line, with a pair of model # > CPUs, which are of the K8 line. The port for that board was done on a pair of 2216 HE CPUs. You may be hard pressed to find those for sale these days... Thanks, Ward. -- Ward Vandewege Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Query, known-good CPUs to use in a H8DME-2 mb?
On Fri, May 07, 2010 at 09:37:54AM -0400, Ward Vandewege wrote: > On Fri, May 07, 2010 at 07:30:08AM -0600, Myles Watson wrote: >> This looks like the bootup code for gen f Opterons. >> It doesn't look like the h8dme has a fam10 variant yet, >> which is what you need for the 2378 CPUs. >> >> I'm surprised you found a revision that works, since >> it has never supported fam10. I think it would be more >> fruitful for you to look at one of the boards that has >> both fam10 and k8 support, and try to put together an >> h8dme_fam10 port. > > For the record, I've been trying to get that going for a > while, but have not had much success - very early hangs > in the fam10 code on this board. Cf. the problems Knut > is having, I think... What AMD Processor model numbers have you folks been using on the SuperMicro H8DME-2 mainboards? I'd like to buy a pair of known-working CPUs. I currently have a pair of AMD model #2378 Processors, which are of the fam10 line, with a pair of model # CPUs, which are of the K8 line. Thoughts? Regards, Joe -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
